ES7210ConfidentialDS.pdf

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1. Pin Out and Description

2. typical APPLICATION CIRCUIT

3. Clock Modes and Sampling Frequencies

4. Micro-controller configuration Interface

5. Digital Audio Interface

6. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

Recommended Operating Conditions

ADC Analog and Filter Characteristics and Specifications

Power Consumption Characteristics

Serial Audio Port Switching Specifications

I2C Switching Specifications

7. Configuration Register Definition

8. Package

9. CORPORATe INFORMATION

High Performance Four Channels Audio ADC APPLICATIONS ES7210 FEATURES • High performance multi-bit delta-sigma audio ADC -85 dB THD+N • 102 dB signal to noise ratio • • 24-bit, 8 to 200 kHz sampling frequency I2S/PCM master or slave serial data port • • Support TDM • 256/384Fs, USB 12/24 MHz and other • non standard audio system clocks Low power standby mode • Mic array • Smart speaker • Far field voice capture ORDERING INFORMATION ES7210 -40°C ~ +85°C QFN-32 BLOCK DIAGRAM MIC1P/MIC1N MIC2P/MIC2N MIC3P/MIC3N MIC4P/MIC4N DSP Multi-bit Delta-sigma Modulator Clock Manager Sample Rate Detector SDOUT2/TDMIN Audio Data Interface I2C Interface MCLK CCLK CDATA AD0 AD1 SDOUT1/TDMOUT SCLK LRCK 1

Everest Semiconductor Confidential ES7210 1. PIN OUT AND DESCRIPTION ................................................................................................ 4 2. TYPICAL APPLICATION CIRCUIT .......................................................................................... 5 3. CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 5 4. MICRO-CONTROLLER CONFIGURATION INTERFACE ...................................................... 5 5. DIGITAL AUDIO INTERFACE .................................................................................................. 7 6. ELECTRICAL CHARACTERISTICS ....................................................................................... 9 ABSOLUTE MAXIMUM RATINGS .................................................................................................. 9 RECOMMENDED OPERATING CONDITIONS ................................................................................ 9 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS .......................................... 9 POWER CONSUMPTION CHARACTERISTICS .............................................................................. 10 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ................................................................... 10 I2C SWITCHING SPECIFICATIONS ............................................................................................... 11 7. CONFIGURATION REGISTER DEFINITION ........................................................................ 12 REGISTER 0X00 – RESET CONTROL, DEFAULT 00110010 .......................................................... 12 REGISTER 0X01 – CLOCK OFF, DEFAULT 00100000 ................................................................... 12 REGISTER 0X02 – MAIN CLOCK CONTROL, DEFAULT 00000010 ............................................... 12 REGISTER 0X03 – MASTER CLOCK CONTROL, DEFAULT 00000100 ........................................... 13 REGISTER 0X04 – MASTER LRCK DIVIDER 1, DEFAULT 00000001 ............................................. 13 REGISTER 0X05 – MASTER LRCK DIVIDER 0, DEFAULT 00000000 ............................................. 13 REGISTER 0X06 – POWER DOWN, DEFAULT 00000000 ............................................................ 13 REGISTER 0X07 – ADC OSR CONFIG, DEFAULT 00100000 ......................................................... 13 REGISTER 0X08 – MODE CONFIG, DEFAULT 00010000 ............................................................. 13 REGISTER 0X09 – TIME CONTROL 0 FOR CHIP INITIALIZATION, DEFAULT 01000000 ............... 14 REGISTER 0X0A – TIME CONTROL 1 FOR CHIP INITIALIZATION, DEFAULT 01000000 ............... 14 REGISTER 0X0B – CHIP STATUS, DEFAULT 00000000 ................................................................ 14 REGISTER 0X0C – INTERRUPT CONTROL, DEFAULT 00000000 .................................................. 14 REGISTER 0X0D – MISC. CONTROL, DEFAULT 00001001 .......................................................... 15 REGISTER 0X10 – DMIC CONTROL, DEFAULT 00000000 ........................................................... 15 REGISTER 0X11 – SDP INTERFACE CONFIG 1, DEFAULT 00000000 ........................................... 15 REGISTER 0X12 – SDP INTERFACE CONFIG 2, DEFAULT 00000000 ........................................... 16 REGISTER 0X13 – ADC AUTOMUTE CONTROL, DEFAULT 00000000 ......................................... 16 REGISTER 0X14 – ADC34 MUTE CONTROL, DEFAULT 00000000 ............................................... 16 REGISTER 0X15 – ADC12 MUTE CONTROL, DEFAULT 00000000 ............................................... 17 REGISTER 0X16 – ALC SELECT, DEFAULT 00000000 .................................................................. 17 REGISTER 0X17 – ALC COMMON CONFIG 1, DEFAULT 00000000 ............................................. 18 Revision 2.0 2 February 2018

Everest Semiconductor Confidential ES7210 REGISTER 0X18 – ADC34 ALC LEVEL, DEFAULT 11110111 ......................................................... 18 REGISTER 0X19 – ADC12 ALC LEVEL, DEFAULT 11110111 ........................................................ 19 REGISTER 0X1A – ALC COMMON CONFIG2, DEFAULT 00000000 ............................................. 20 REGISTER 0X1B – ADC4 MAX GAIN, DEFAULT 10111111 .......................................................... 20 REGISTER 0X1C – ADC3 MAX GAIN, DEFAULT 10111111 .......................................................... 20 REGISTER 0X1D – ADC2 MAX GAIN, DEFAULT 10111111 .......................................................... 20 REGISTER 0X1E – ADC1 MAX GAIN, DEFAULT 10111111 .......................................................... 21 REGISTER 0X20 – ADC34 HPF2, DEFAULT 00100110 ................................................................. 21 REGISTER 0X21 – ADC34 HPF1, DEFAULT 00100110 ................................................................. 21 REGISTER 0X22 – ADC12 HPF1, DEFAULT 00000110 ................................................................. 21 REGISTER 0X23 – ADC12 HPF2, DEFAULT 00100110 ................................................................. 21 REGISTER 0X24 TO 3X37 – EQ COEFFICIENTS AUTOMATICLLY GENERATED BY MATLAB ......... 22 REGISTER 0X3D – CHIP ID1, DEFAULT 01110010 ...................................................................... 22 REGISTER 0X3E – CHIP ID0, DEFAULT 00010000 ....................................................................... 22 REGISTER 0X3F – CHIP VERSION, DEFAULT 00000000 .............................................................. 22 REGISTER 0X40 – ANALOG SYSTEM, DEFAULT 10000000 ......................................................... 22 REGISTER 0X41 – MIC1/2 BIAS, DEFAULT 01110001 ................................................................. 22 REGISTER 0X42 – MIC3/4 BIAS, DEFAULT 01110001 ................................................................. 23 REGISTER 0X43 – MIC1 GAIN, DEFAULT 00000000 ................................................................... 23 REGISTER 0X44 – MIC2 GAIN, DEFAULT 00000000 ................................................................... 24 REGISTER 0X45 – MIC3 GAIN, DEFAULT 00000000 ................................................................... 24 REGISTER 0X46 – MIC4 GAIN, DEFAULT 00000000 ................................................................... 24 REGISTER 0X47 – MIC1 LOW POWER, DEFAULT 00000000 ...................................................... 25 REGISTER 0X48 – MIC2 LOW POWER, DEFAULT 00000000 ...................................................... 25 REGISTER 0X49 – MIC3 LOW POWER, DEFAULT 00000000 ...................................................... 25 REGISTER 0X4A – MIC4 LOW POWER, DEFAULT 00000000 ...................................................... 26 REGISTER 0X4B – MIC1/2 POWER DOWN, DEFAULT 11111111 ............................................... 26 REGISTER 0X4C – MIC3/4 POWER DOWN, DEFAULT 11111111 ............................................... 26 8. PACKAGE .............................................................................................................................. 28 9. CORPORATE INFORMATION .............................................................................................. 29 Revision 2.0 3 February 2018

Everest Semiconductor Confidential ES7210 1. PIN OUT AND DESCRIPTION R E F P 3 4 R E F Q 3 4 I M C 3 P I M C 4 P I M C 4 N I M C B A S 3 4 I R E F Q M I M C 3 N 1 2 3 4 5 6 7 8 AD0 AD1 CDATA CCLK MCLK VDDP VDDD GNDD 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 ES7210 1 0 1 1 1 2 1 3 1 4 1 5 1 6 9 I M C 1 N I M C 1 P I N T I D M C _ C L K S C L K L R C K S D O U T 2 / T D M N I S D O U T 1 / T D M O U T 24 23 22 21 20 19 18 17 MICBIAS12 VDDM VDDA GNDA MIC2N MIC2P REFQ12 REFP12 Pin Name CCLK, CDATA AD0, AD1 MCLK SCLK LRCK SDOUT1/TDMOUT SDOUT2/TDMIN INT DMIC_CLK MIC1P, MIC1N MIC2P, MIC2N MIC3P, MIC3N MIC4P, MIC4N MICBIAS12 MICBIAS34 VDDP VDDD, GNDD VDDA, GNDA VDDM REFP12, REFP34 REFQ12, REFQ34 REFQM Pin number 3, 4 1, 2 5 9 10 11 12 13 14 16, 15 19, 20 31, 32 28, 27 24 26 6 7, 8 22, 21 23 17, 30 18, 29 25 Input or Output I/O I I I/O I/O O I/O O I Pin Description I2C clock and data I2C address Master clock Serial data bit clock Serial data left and right channel frame clock Serial data output or TDM data input and output Interrupt Digital mic clock Analog Mic input Analog Analog Analog Analog Analog Analog Analog Analog Mic bias Power supply for the digital input and output Digital power supply Analog power supply Analog power supply Filtering capacitor connection Filtering capacitor connection Filtering capacitor connection Revision 2.0 4 February 2018

Everest Semiconductor Confidential ES7210 2. TYPICAL APPLICATION CIRCUIT AGND 10uF 10uF 10uF 10uF 10uF 9 2 0 3 5 2 8 1 7 1 1 2 3 2 10uF AGND 10uF 2 2 AGND 4 3 Q F E R 4 3 P F E R M Q F E R 2 1 Q F E R 2 1 P F E R A D N G A D D V M D D V MICBIAS34 ES7210 Everest MIC4P MIC4N MIC3P MIC3N VDDP VDDD GNDD AD0 AD1 CDATA CCLK 26 28 27 31 32 AGND 2.2uF 2.2uF 2.2uF 2.2uF 10uF 100nF VDDP VDDC 1uF 100nF 6 7 1uF 100nF 8 IIC IIS 1 2 3 4 5 9 10 11 12 GPIO MCLK SCLK LRCK SDOUT1/TDMOUT SDOUT2/TDMIN DMIC_CLK/GPIO INT 14 13 VDDP 1R 100nF 1R 100nF AGND 10uF 100nF VDDM VDDA AGND AGND AGND 10nF 10nF 10nF 10nF 2K 2K 2K 2K Mic4 Mic3 AGND AGND AGND 2.2uF 2.2uF For best performance,decoupling and filter capacitor should be located as close to the device package as possible 100K MICBIAS12 MIC2P MIC2N 24 19 20 MIC1P MIC1N 16 15 10nF 10nF 10nF 10nF 2K 2K 2K 2K 2.2uF 2.2uF Mic2 Mic1 3. CLOCK MODES AND SAMPLING FREQUENCIES The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and some common non standard audio clocks (25 MHz, 26 MHz, etc). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 4. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External micro- controller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (CDATA) and a serial clock line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the CDATA low. The transfer rate of this interface can be up to 400 kbps. Revision 2.0 5 February 2018

Everest Semiconductor Confidential ES7210 A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at CDATA while CCLK is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode start Chip Address 001000 AD0 R/W 0 ACK Register Address RAM ACK Data to be written DATA ACK Stop Chip Addr Write ACK bit 1 to 7 Reg Addr bit 1 to 8 CDATA CCLK START ACK Write Data ACK bit 1 to 8 STOP Figure 1a I2C Write Timing Table 2 Read Data from Register in I2C Interface Mode Chip Address 001000 Chip Address 001000 AD0 AD0 R/W 0 R/W 1 Register Address RAM Data to be read Data ACK NACK Stop ACK ACK ACK Chip Addr Read ACK Read Data NO ACK bit 1 to 7 bit 1 to 8 Start Start CDATA CCLK START Chip Addr Write ACK Reg Addr bit 1 to 7 bit 1 to 8 START Figure 1b I2C Read Timing STOP Revision 2.0 6 February 2018

Everest Semiconductor Confidential ES7210 5. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the output from the ADC through LRCK, SCLK and SDOUT pins. These formats are I2S, left justified, DSP/PCM mode and TDM. ADC data is out at SDOUT on the falling edge of SCLK. The relationships of SDOUT, SCLK and LRCK with these formats are shown through Figure 2a to Figure 2h. ES7210 can be cascaded up to 16-ch through single I2S or TDM, please refer to the user guide for detail description. 1 SCLK R Channel LSB Figure 2a I2S Serial Audio Data Format MSB LSB R Channel MSB LSB Figure 2b Left Justified Serial Audio Data Format 1 SCLK L Channel MSB L Channel MSB LSB 1 SCLK L Channel R Channel MSB LSB MSB LSB LRCK SCLK SDOUT LRCK SCLK SDOUT LRCK SCLK SDOUT LRCK SCLK SDOUT Figure 2c DSP/PCM Mode A Serial Audio Data Format L Channel R Channel MSB LSB MSB LSB Figure 2d DSP/PCM Mode B Serial Audio Data Format 7 February 2018 Revision 2.0

Everest Semiconductor Confidential ES7210 1 SCLK Channel 1 Channel 3 MSB LSB MSB LSB 1 SCLK Channel 2 Channel 4 MSB LSB MSB LSB Figure 2e TDM I2S Serial Audio Data Format LRCK SCLK SDOUT LRCK SCLK SDOUT LRCK SCLK SDOUT LRCK SCLK SDOUT LSB Channel 1 Channel 3 MSB LSB MSB LSB Channel 2 Channel 4 MSB LSB MSB Figure 2f TDM Left Justified Serial Audio Data Format 1 SCLK Channel 1 Channel 2 Channel 3 Channel 4 MSB LSB MSB LSB MSB LSB MSB LSB Figure 2g TDM DSP/PCM Mode A Serial Audio Data Format Channel 1 Channel 2 Channel 3 Channel 4 MSB LSB MSB LSB MSB LSB MSB LSB Figure 2h TDM DSP/PCM Mode B Serial Audio Data Format Revision 2.0 8 February 2018

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