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    Writing Testbenches: Functional Verification of HDL Models
    Copyright
    Table of Contents
    About the Cover
    Foreword
    Preface
    Ch1 What is Verification?
    What is Testbench?
    Importance of Verification
    Reconvergence Model
    Human Factor
    Automation
    Poka-Yoka
    Redundancy
    What is being Verified?
    Formal Verification
    Equivalence Checking
    Model Checking
    Functional Verification
    Testbench Generation
    Functional Verification Approaches
    Black-Box Verification
    White-Box Verification
    Grey-Box Verification
    Testing vs Verification
    Scan-Based Testing
    Design for Verification
    Verification & Design Reuse
    Reuse is about Trust
    Verification for Reuse
    Cost of Verification
    Summary
    Ch2 Verification Tools
    Linting Tools
    Limitations of Linting Tools
    Linting Verilog Source Code
    Linting VHDL Source Code
    Code Reviews
    Simulators
    Stimulus & Response
    Event-Driven Simulation
    Cycle-Based Simulation
    Co-Simulators
    Third-Party Models
    Hardware Modelers
    Waveform Viewers
    Code Coverage
    Statement Coverage
    Path Coverage
    Expression Coverage
    What does 100% Coverage Mean?
    Verification Language
    Revision Control
    Software Engineering Experience
    Configuration Management
    Working with Releases
    Issue Tracking
    What is an Issue?
    Grapevine System
    Post-it System
    Procedural System
    Computerized System
    Metrics
    Code-Related Metrics
    Quality-Related Metrics
    Interpreting Metrics
    Summary
    Ch3 Verification Plan
    Role of Verification Plan
    Specifying Verification
    Defining First-Time Success
    Levels of Verification
    Unit-Level Verification
    Reusable Components Verification
    ASIC & FPGA Verification
    System-Level Verification
    Board-Level Verification
    Verification Strategies
    Verifying Response
    Random Verification
    From Specification to Features
    Component-Level Features
    System-Level Features
    Error Types to Look for
    From Features to Testcases
    Prioritize
    Group into Testcases
    Design for Verification
    From Testcases to Testbenches
    Verifying Testbenches
    Summary
    Ch4 Behavioral Hardware Description Languages
    Behavioral vs RTL Thinking
    Contrasting Approaches
    You Gotta Have Style!
    Question of Discipline
    Optimize Right Thing
    Good Comments Improve Maintainability
    Structure of Behavioral Code
    Encapsulation Hides Implementation Details
    Encapsulating Useful Subprograms
    Encapsulating Bus-Functional Models
    Data Abstraction
    Real Values
    Records
    Multi-Dimensional Arrays
    Lists
    Files
    Interfacing High-Level Data Types
    HDL Parallel Engine
    Connectivity, Time & Concurrency
    Connectivity, Time & Concurrency in HDLs
    Problems with Concurrency
    Emulating Parallelism on Sequential Processor
    Simulation Cycle
    Parallel vs Sequential
    Fork/Join Statement
    Difference between Driving & Assigning
    Verilog Portability Issues
    Read/Write Race Conditions
    Write/Write Race Conditions
    Initialization Races
    Guidelines for Avoiding Race Conditions
    Events from Overwritten Scheduled Values
    Disabled Scheduled Values
    Output Arguments on Disabled Tasks
    Non-Reentrant Tasks
    Summary
    Ch5 Stimulus & Response
    Simple Stimulus
    Generating Simple Waveform
    Generating Complex Waveform
    Generating Synchronized Waveforms
    Aligning Waveforms in Delta-Time
    Generating Synchronous Data Waveforms
    Encapsulating Waveform Generation
    Abstracting Waveform Generation
    Verifying Output
    Visual Inspection of Response
    Producing Simulation Results
    Minimizing Sampling
    Visual Inspection of Waveforms
    Self-Checking Testbenches
    Input & Output Vectors
    Golden Vectors
    Run-Time Result Verification
    Complex Stimulus
    Feedback between Stimulus & Design
    Recovering from Deadlocks
    Asynchronous Interfaces
    CPU Operations
    Configurable Operations
    Complex Response
    What is Complex Response?
    Handling Unknown or Variable Latency
    Abstracting Output Operations
    Generic Output Monitors
    Monitoring Multiple Possible Operations
    Monitoring Bi-Directional Interfaces
    Predicting Output
    Data Formatters
    Packet Processors
    Complex Transformations
    Summary
    Ch6 Architecting Testbenches
    Reusable Verification Components
    Procedural Interface
    Development Process
    Verilog Implementation
    Packaging Bus-Functional Models
    Utility Packages
    VHDL Implementation
    Packaging Bus-Functional Procedures
    Creating a Test Harness
    Abstracting Client/Server Protocol
    Managing Control Signals
    Multiple Server Instances
    Utility Packages
    Autonomous Generation & Monitoring
    Autonomous Stimulus
    Random Stimulus
    Injecting Errors
    Autonomous Monitoring
    Autonomous Error Detection
    Input & Output Paths
    Programmable Testbenches
    Configuration Files
    Concurrent Simulations
    Compile-Time Configuration
    Verifying Configurable Designs
    Configurable Testbenches
    Top Level Generics & Parameters
    Summary
    Ch7 Simulation Management
    Behavioral Models
    Behavioral vs Synthesizable Models
    Example of Behavioral Modeling
    Characteristics of Behavioral Model
    Modeling Reset
    Writing Good Behavioral Models
    Behavioral Models are Faster
    Cost of Behavioral Models
    Benefits of Behavioral Models
    Demonstrating Equivalence
    Pass or Fail?
    Managing Simulations
    Configuration Management
    Verilog Configuration Management
    VHDL Configuration Management
    SDF Back-Annotation
    Output File Management
    Regression
    Running Regressions
    Regression Management
    Summary
    AppA Coding Guidelines
    Directory Structure
    VHDL Specific
    Verilog Specific
    General Coding Guidelines
    Comments
    Syntax
    Debugging
    Naming Guidelines
    Capitalization
    Identifiers
    Constants
    HDL Specific
    Filenames
    HDL Coding Guidelines
    Structure
    Layout
    VHDL Specific
    Verilog Specific
    Afterwords
    Index
    WRITING TESTBENCHES Functional Verification of HDL Models
    This Page Intentionally Left Blank
    WRITING TESTBENCHES Functional Verification of HDL Models Janick Bergeron Qualis Design Corporation KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
    eBook ISBN: 0-306-47687-8 0-7923-7766-4 Print ISBN: ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2000 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com
    TABLE OF CONTENTS About the Cover Foreword Preface Why This Book Is Important What This Book Is About What Prior Knowledge You Should Have Reading Paths VHDL versus Verilog For More Information Acknowledgements CHAPTER 1 What is Verification? What is a Testbench? The Importance of Verification Reconvergence Model The Human Factor Automation Poka-Yoka Writing Testbenches: Functional Verification of HDL Models xiii xv xvii xvii xviii xix xx xx xxii xxii 1 1 2 4 5 6 6 v
    Table of Content Redundancy What Is Being Verified? Formal Verification Equivalence Checking Model Checking Functional Verification Testbench Generation Functional Verification Approaches Black-Box Verification White-Box Verification Grey-Box Verification Testing Versus Verification Scan-Based Testing Design for Verification Verification and Design Reuse Reuse Is About Trust Verification for Reuse The Cost of Verification Summary CHAPTER 2 Verification Tools Linting Tools The Limitations of Linting Tools Linting Verilog Source Code Linting VHDL Source Code Code Reviews Simulators Stimulus and Response Event-Driven Simulation Cycle-Based Simulation Co-Simulators Third-Party Models Hardware Modelers Waveform Viewers Code Coverage Statement Coverage Path Coverage Expression Coverage 6 7 7 8 9 10 11 11 12 13 13 13 14 16 16 16 17 17 19 21 22 23 25 26 28 28 29 29 31 34 36 37 38 40 42 44 45 vi Writing Testbenches: Functional Verification of HDL Models
    What Does 100 Percent Coverage Mean? Verification Languages Revision Control The Software Engineering Experience Configuration Management Working with Releases Issue Tracking What Is an Issue? The Grapevine System The Post-It System The Procedural System Computerized System Metrics Code-Related Metrics Quality-Related Metrics Interpreting Metrics Summary CHAPTER 3 The Verification Plan The Role of the Verification Plan Specifying the Verification Defining First-Time Success Levels of Verification Unit-Level Verification Reusable Components Verification ASIC and FPGA Verification System-Level Verification Board-Level Verification Verification Strategies Verifying the Response Random Verification From Specification to Features Component-Level Features System-Level Features Error Types to Look For From Features to Testcases Prioritize Group into Testcases Design for Verification Writing Testbenches: Functional Verification of HDL Models 45 46 47 48 50 51 52 52 53 54 55 55 57 57 58 59 60 61 62 62 63 64 65 66 67 68 68 69 70 71 72 73 73 74 75 75 76 77 vii
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