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Effective Coding with VHDL Principles and Best Practice 无水印原版pdf.pdf
Cover
Copyright
Contents
Preface
Part I Design Principles
1 A VHDL Refresher
1.1 Why This Book?
1.2 What Is VHDL?
1.2.1 Key Features of VHDL
1.2.2 The LRM
1.2.3 VHDL versus General-Purpose Languages
1.3 Levels of Abstraction in Digital Systems
1.4 A Summary of VHDL
1.4.1 Entities and Architectures
1.4.2 Statements in VHDL
1.4.3 Concurrent Statements
1.4.4 Sequential Statements
1.4.5 Subprograms
1.4.6 Expressions
1.4.7 Packages
1.4.8 Data Types
1.4.9 Predefined Attributes
1.4.10 Generics
1.5 VHDL-2008
2 Design and Architecture
2.1 What Is Design?
2.2 Quality Measures
2.2.1 Design Qualities
2.2.2 Business Qualities
2.3 Architecture
3 Design Challenges
3.1 Complexity
3.2 Changes
3.3 Dependencies
3.4 Duplicate Information
3.5 Technical Debt
3.6 Your Wetware
3.6.1 Recognition versus Recall
4 Design Principles
4.1 Modularity
4.1.1 What Is a Module?
4.1.2 Key Benefits of Modularity
4.1.3 Effectively Decomposing a System into Modules
4.2 Abstraction
4.2.1 Levels of Abstraction
4.2.2 Key Benefits of Abstraction
4.2.3 Using Abstraction Effectively
4.3 Hierarchy
4.3.1 Key Benefits of Hierarchy
4.4 Loose Coupling
4.4.1 Types of Coupling
4.4.2 Decoupling
4.5 Strong Cohesion
4.6 The Single Responsibility Principle
4.7 Orthogonality
4.7.1 Guidelines for Creating Orthogonal Systems
4.8 Single Source of Truth (The DRY Principle)
Part II Basic Elements of VHDL
5 Analysis, Elaboration, and Execution
5.1 VHDL in the System Design Flow
5.2 The Design Processing Flow
5.3 Overview of the Analysis and Elaboration Process
5.4 Detailed View of the Analysis Phase
5.4.1 Lexical Analysis
5.4.2 Lexical Elements
5.4.3 Syntax Analysis
5.4.4 Semantic Analysis
5.5 Detailed View of the Elaboration Phase
5.6 The Execution Phase
5.6.1 Discrete-Event Simulation
5.6.2 Drivers
5.6.3 Initialization Phase
5.6.4 The Simulation Cycle
6 VHDL Design Units
6.1 Design Units
6.1.1 Entity Declaration
6.1.2 Architecture Body
6.1.3 Package Declaration and Package Body
6.2 Design Libraries and Library Units
6.3 Guidelines and Recommendations for VHDL Design Units
7 Statements, Declarations, and Expressions
7.1 Statements
7.2 Declarations
7.2.1 Scope
7.2.2 Visibility
7.2.3 Overloading
7.2.4 Scope, Visibility, and Overloading
7.2.5 Use Clauses
7.2.6 Live Time and Span
7.3 Expressions
7.4 Guidelines and Recommendations for Statements, Declarations, and Expressions
8 Operators, Operands, and Attributes
8.1 Operators
8.1.1 Condition Operator (??)
8.1.2 Logical Operators
8.1.3 Relational Operators
8.1.4 Shift Operators
8.1.5 Adding Operators
8.1.6 Operator Overloading
8.2 Operands
8.2.1 Literals
8.2.2 Aggregates
8.2.3 Names
8.2.4 Aliases
8.2.5 Other Kinds of Operands
8.3 Attributes
8.4 Guidelines and Recommendations for Operators, Operands, and Attributes
Part III Statements
9 Concurrent Statements
9.1 Introduction
9.2 The process Statement
9.2.1 The Ins and Outs of VHDL Processes
9.2.2 The Sensitivity List
9.2.3 Equivalence between Processes and Other Concurrent Statements
9.2.4 Guidelines and Recommendations for Writing Processes
9.3 The Concurrent Procedure Call Statement
9.4 The Component Instantiation Statement
9.5 The generate Statement
9.5.1 General Remarks about generate Statements
9.6 Other Concurrent Statements
9.6.1 The block Statement
9.6.2 The Concurrent Signal Assignment Statement
9.6.3 The Concurrent Assertion Statement
10 Sequential Statements
10.1 Control Structures
10.1.1 The Problems with Deep Nesting
10.2 The if Statement
10.2.1 Guidelines for the if Statement
10.3 The case Statement
10.3.1 Guidelines for the case Statement
10.4 Loops
10.4.1 Kinds of Loops
10.4.2 Auxiliary Loop Control Statements
10.4.3 Loops in Hardware
10.4.4 Guidelines for Using Loops
10.5 The wait Statement
10.5.1 Synthesizable wait Statements
10.6 The assert Statement
10.6.1 When to Use an Assertion
10.6.2 When Not to Use an Assertion
10.6.3 Severity Levels
10.7 The null Statement
11 Assignment Statements
11.1 Kinds of Assignments in VHDL
11.1.1 Classification by Target Class (Signal vs. Variable)
11.1.2 Classification by Assignment Statement (Simple vs. Conditional vs. Selected)
11.1.3 Classification by Kind of VHDL Code (Sequential vs. Concurrent)
11.2 Assignment Sources and Targets
11.2.1 Assignment Sources
11.2.2 Assignment Targets
11.3 Assignments with Timing and Delay
11.3.1 Delay Mechanisms
11.4 Force and Release Assignments
Part IV Types and Objects
12 Categories of Types in VHDL
12.1 Overview of Data in VHDL
12.1.1 Types in VHDL
12.1.2 Objects in VHDL
12.1.3 Object Classes
12.1.4 Use of the Terms class and object in VHDL and Object-Oriented Languages
12.1.5 What Does Strongly Typed Mean?
12.2 VHDL Type Hierarchy
12.2.1 Scalar Types
12.2.2 Composite Types
12.2.3 Access Types
12.2.4 File Types
12.2.5 Protected Types
12.3 Subtypes
12.4 Resolved Types
13 Predefined and User-Defined Types
13.1 Predefined and Standard Types
13.2 Types and Packages for Integer Values and Operations
13.3 Converting between Types
13.4 Abstract Data Types
13.5 Other Recommendations on Using Types
14 VHDL Data Objects
14.1 Constants
14.1.1 Why Use Constants?
14.1.2 Recommendations for Using Constants
14.2 Variables
14.3 Signals
14.4 Signals versus Variables
14.5 Shared Variables
14.6 Files
14.7 Object Initial Values
Part V Practical Coding Recommendations
15 Excellent Routines
15.1 What Is a Routine?
15.2 Why Use Routines?
15.3 Functions versus Procedures
15.3.1 Functions
15.3.2 Procedures
15.3.3 Choosing between Functions and Procedures
15.4 Writing Great Routines
15.5 Parameters
15.5.1 Formal versus Actual Parameters
15.5.2 Interface Objects
15.5.3 Subprogram Calls
15.5.4 Guidelines for Using Parameters
15.6 Where Should Routines Go?
16 Excellent Names
16.1 How Long Should a Name Be?
16.2 General Naming Guidelines
16.3 Guidelines for Naming Data Objects
16.4 Guidelines for Naming Routines
16.5 Guidelines for Naming Other VHDL Constructs
17 Excellent Comments
17.1 Comments: Good or Bad?
17.2 Basic Principles
17.3 Types of Comments
17.3.1 Good Comments
17.3.2 Double-Edged Comments
17.3.3 Bad Comments
17.4 Comment Layout
17.4.1 Comment Syntax in VHDL
17.4.2 Comment Layout Choices
17.5 Commenting Guidelines
17.5.1 Layout Guidelines
17.5.2 Language and Content
17.5.3 General Commenting Guidelines
17.5.4 Guidelines for Specific Kinds of Code
17.6 Self-Documenting Code
18 Excellent Style
18.1 Programming Style
18.1.1 Programming Style Matters
18.2 Code Layout
18.2.1 Layout Goals
18.2.2 Basic Layout Types
18.3 Indentation
18.4 Paragraphs of Code
18.5 Line Length
18.5.1 Wrapping Long Lines
18.6 Spaces and Punctuation
18.7 Letter Case
18.8 Other Layout and Style Recommendations
Part VI Synthesis and Testbenches
19 Synthesis
19.1 Introduction
19.2 What Is the Difference?
19.2.1 Syntactic Restrictions
19.2.2 Semantic Restrictions
19.2.3 Synthesizable Types
19.3 Creating Synthesizable Designs
19.3.1 RTL Design Methodology
19.3.2 Synchronous Circuits
19.4 Inferring Hardware Elements
19.4.1 Combinational Logic
19.4.2 Sequential Logic
19.4.3 Three-State Logic
19.4.4 ROM Memories
19.4.5 RAM Memories
19.5 Initialization and Reset
19.6 Pragmas
19.6.1 Synthesis Attributes
19.6.2 Metacomments
20 Testbenches
20.1 Introduction
20.1.1 Test or Verification?
20.1.2 Functional Verification
20.1.3 What Should We Test?
20.1.4 Self-Checking Testbenches
20.1.5 Basic Parts of a Testbench
20.1.6 What is the Output of a Testbench?
20.1.7 Test-Driven Development
20.2 Example #1: Testbench for a Combinational Circuit
20.3 Example #2: Testbench for a Clocked Circuit
20.4 Example #3: Testbench for an FSM
20.5 Example #4: Testbenches with File I/O
20.6 Random Stimulus and Functional Coverage
20.6.1 Functional Coverage
20.6.2 Directed Testing
20.6.3 Random-Based Verification
20.6.4 Intelligent Coverage
20.6.5 Coverage Bins
20.6.6 VHDL and Random-Based Verification
20.7 Example #5: Testbench with Random Stimulus and Functional Coverage
20.8 Example #6: FSM Transition Coverage
20.9 Conclusion
Notes
Bibliography
Index
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Effective Coding with
VHDL
Principles and Best Practice
Ricardo Jasinski
This book addresses an often-neglected aspect of the creation of VHDL designs. A VHDL
description is also source code, and VHDL designers can use the best practices of software
development to write high-quality code and to organize it in a design. This book presents this
unique set of skills, teaching VHDL designers of all experience levels how to apply the best
design principles and coding practices from the software world to the world of hardware. The
concepts introduced here will help readers write code that is easier to understand and more
likely to be correct, with improved readability, maintainability, and overall quality.
After a brief review of VHDL, the book presents fundamental design principles for writing
code, discussing such topics as design, quality, architecture, modularity, abstraction, and
hierarchy. Building on these concepts, the book then introduces and provides recommenda-
tions for each basic element of VHDL code, including statements, design units, types, data
objects, and subprograms. The book covers naming data objects and functions, commenting
the source code, and visually presenting the code on the screen. All recommendations are
supported by detailed rationales. Finally, the book explores two uses of VHDL: synthesis and
testbenches. It examines the key characteristics of code intended for synthesis (distinguish-
ing it from code meant for simulation) and then demonstrates the design and implementa-
tion of testbenches with a series of examples that verify different kinds of models, including
combinational, sequential, and FSM code. Examples from the book are also available on a
companion website, enabling the reader to experiment with the complete source code.
Ricardo Jasinski is Founder and Lead Developer at Solvis Ltd.
“This is the book that so many of us have been waiting for. It goes way beyond teaching VHDL
language to address the principles of design. Ricardo Jasinski takes the wisdom learned from
software gurus like Martin Fowler and Ward Cunningham and translates it to hardware design.
It will challenge you to be a better coder and a better designer.”
—Philippe Faes, PhD, CEO of Sigasi
ISBN 978-0-262-03422-7
“Hardware designers tend to produce poorly structured VHDL while software designers often
do not adequately consider resource constraints of size, speed, and real-time response. This
sorely needed book shows readers how to implement and verify projects that not only meet
the hardware functionality requirements but do so with concise, readable, and reusable VHDL.”
—Donald W. Bouldin, Professor Emeritus of Electrical Engineering and Computer
Science, University of Tennessee
THE MIT PRESS
Massachusetts Institute of Technology
Cambridge, Massachusetts 02142
http://mitpress.mit.edu
978-0-262-03422-7
9 780262 034227
90000
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Effective Coding with
VHDL
PRINCIPLES AND BEST PRACTICE
Ricardo Jasinski
Effective Coding with VHDL
Effective Coding with VHDL
Principles and Best Practice
Ricardo Jasinski
The MIT Press
Cambridge, Massachusetts
London, England
© 2016 Massachusetts Institute of Technology
All rights reserved. No part of this book may be reproduced in any form by any electronic or me-
chanical means (including photocopying, recording, or information storage and retrieval) with-
out permission in writing from the publisher.
This book was set in Stone Serif and Stone Sans by Toppan Best-set Premedia Limited Printed
and bound in the United States of America.
Library of Congress Cataloging-in-Publication Data
Names: Jasinski, Ricardo, author.
Title: Effective coding with VHDL : principles and best practice / Jasinski, Ricardo.
Description: Cambridge, MA : The MIT Press, [2015] | Includes bibliographical references and
index.
Identifi ers: LCCN 2015039698 | ISBN 9780262034227 (hardcover : alk. paper)
Subjects: LCSH: VHDL (Computer hardware description language) | Computer programming.
Classifi cation: LCC TK7885.7 .J57 2015 | DDC 621.39/2—dc23 LC record available at http://
lccn.loc.gov/2015039698
10 9 8 7 6 5 4 3 2 1
Contents
Preface xiii
Part I
D esign Principles 1
1
A VHDL Refresher 3
1.1 Why This Book? 3
1.2 What Is VHDL? 4
1.2.1 Key Features of VHDL 5
1.2.2 The LRM 6
1.2.3 VHDL versus General-Purpose Languages 7
1.3 Levels of Abstraction in Digital Systems 7
1.4 A Summary of VHDL 9
1.4.1 Entities and Architectures 9
1.4.2 Statements in VHDL 11
1.4.3 Concurrent Statements 11
1.4.4 Sequential Statements 16
1.4.5 Subprograms 21
1.4.6 Expressions 22
1.4.7 Packages 23
1.4.8 Data Types 24
1.4.9 Predefined Attributes 28
1.4.10 Generics 29
1.5 VHDL-2008 31
2
Design and Architecture 35
2.1 What Is Design? 35
2.2 Quality Measures 37
2.2.1 Design Qualities 38
2.2.2 Business Qualities 47
2.3 Architecture 50
Contents
vi
3
Design Challenges 53
3.1 Complexity 53
3.2 Changes 55
3.3 Dependencies 56
3.4 Duplicate Information 57
3.5 Technical Debt 58
3.6 Your Wetware 60
3.6.1 Recognition versus Recall 61
4
Design Principles 63
4.1 Modularity 63
4.1.1 What Is a Module? 63
4.1.2 Key Benefits of Modularity 64
4.1.3 Effectively Decomposing a System into Modules 65
4.2 Abstraction 69
4.2.1 Levels of Abstraction 69
4.2.2 Key Benefits of Abstraction 71
4.2.3 Using Abstraction Effectively 72
4.3 Hierarchy 74
4.3.1 Key Benefits of Hierarchy 75
4.4 Loose Coupling 78
4.4.1 Types of Coupling 79
4.4.2 Decoupling 80
4.5 Strong Cohesion 81
4.6 The Single Responsibility Principle 83
4.7 Orthogonality 84
4.7.1 Guidelines for Creating Orthogonal Systems 85
4.8 Single Source of Truth (The DRY Principle) 86
Part II Basic Elements of VHDL 89
5
Analysis, Elaboration, and Execution 91
5.1 VHDL in the System Design Flow 91
5.2 The Design Processing Flow 93
5.3 Overview of the Analysis and Elaboration Process 96
5.4 Detailed View of the Analysis Phase 98
5.4.1 Lexical Analysis 98
5.4.2 Lexical Elements 99
5.4.3 Syntax Analysis 101
5.4.4 Semantic Analysis 103
5.5 Detailed View of the Elaboration Phase 104
Contents
vii
5.6 The Execution Phase 107
5.6.1 Discrete-Event Simulation 107
5.6.2 Drivers 108
5.6.3
5.6.4 The Simulation Cycle 111
Initialization Phase 111
6
VHDL Design Units 113
6.1 Design Units 113
6.1.1 Entity Declaration 114
6.1.2 Architecture Body 118
6.1.3 Package Declaration and Package Body 119
6.2 Design Libraries and Library Units 121
6.3 Guidelines and Recommendations for VHDL Design Units 123
7
Statements, Declarations, and Expressions 129
7.1 Statements 129
7.2 Declarations 132
7.2.1 Scope 132
7.2.2 Visibility 133
7.2.3 Overloading 134
7.2.4 Scope, Visibility, and Overloading 136
7.2.5 Use Clauses 136
7.2.6 Live Time and Span 139
7.3 Expressions 140
7.4 Guidelines and Recommendations for Statements, Declarations, and
Expressions 142
8
Operators, Operands, and Attributes 147
8.1 Operators 147
8.1.1 Condition Operator (??) 149
8.1.2 Logical Operators 150
8.1.3 Relational Operators 152
8.1.4 Shift Operators 154
8.1.5 Adding Operators 154
8.1.6 Operator Overloading 156
8.2 Operands 158
8.2.1 Literals 159
8.2.2 Aggregates 161
8.2.3 Names 165
8.2.4 Aliases 168
8.2.5 Other Kinds of Operands 171
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