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OV2718 DATASHEET.pdf
applications
features
key specifications (typical)
table of contents
list of figures
list of tables
1 application system
1.1 overview
1.2 signal description and pin assignment
table 1-1 signal descriptions (sheet 1 of 3)
table 1-2 pin states under various conditions
table 1-3 GPIO control registers
figure 1-1 pin diagram
table 1-4 pad equivalent circuit (sheet 1 of 2)
1.3 reference design
figure 1-2 OV2718 MIPI reference schematic
figure 1-3 OV2718 DVP reference schematic
1.3.1 external components
figure 1-4 OV2718 power supplies and recommended external decoupling
1.3.2 power on reset (POR) generation
1.4 power up sequence/ boot sequence
figure 1-5 power on timing diagram
table 1-5 power on timing
1.4.1 power down sequence
1.4.2 operating modes
1.4.3 activation sequence
1.4.4 deactivation sequence
1.4.5 early activation
2 sensor architecture
figure 2-1 OV2718 block diagram
3 image sensor core
figure 3-1 sensor core block diagram
3.1 pixel array structure
figure 3-2 pixel array region color filter layout
figure 3-3 integration time diagram
3.2 pixel array access
figure 3-4 pixel array access diagram
3.3 mirror and flip
table 3-1 register setting for mirror
figure 3-5 horizontal mirror and vertical flip samples
3.4 sub-sampling
figure 3-6 horizontal and vertical sub-sampling
3.5 frame timing and maximum frame rate
figure 3-7 row address versus time graph
figure 3-8 frame output timing diagram
table 3-2 supported output formats and frame rates for MIPI/LVDS
table 3-3 supported output formats and frame rates for DVP
table 3-4 timing control registers
3.6 exposure control
table 3-5 exposure control registers
3.7 black level calibration (BLC)
3.7.1 advanced operation of the BLC
table 3-6 BLC control registers (sheet 1 of 5)
3.8 PLL
figure 3-9 PLL1 control diagram
figure 3-10 PLL2 control diagram
table 3-7 PLL control registers (sheet 1 of 2)
3.9 temperature sensor
table 3-8 temperature sensor registers
4 image processor
figure 4-1 image processor block diagram
4.1 test pattern
4.1.1 analog color bar overlay
figure 4-2 color bar types
4.1.2 digital test patterns
figure 4-3 vertical bars test pattern
figure 4-4 vertical bars with vertical gradient test pattern
figure 4-5 vertical bars with horizontal gradient test pattern
figure 4-6 vertical bars with diagonal gradient test pattern
figure 4-7 vertical bars with rolling line test pattern
figure 4-8 random image test pattern
figure 4-9 color squares test pattern
figure 4-10 black and white squares test pattern
figure 4-11 chart test pattern
table 4-1 test pattern control registers
4.2 lens correction (LENC)
figure 4-12 coefficient gain graph
table 4-2 LENC control registers (sheet 1 of 2)
4.3 auto white balance gain (AWB gain)
table 4-3 AWB control registers (sheet 1 of 4)
4.4 defective pixel cancellation (DPC)
figure 4-13 threshold gain curve
figure 4-14 defect pattern examples
figure 4-15 adaptive thresholds
figure 4-16 connected case thresholds
table 4-4 DPC registers (sheet 1 of 8)
5 image output interface
5.1 image output format
table 5-1 image output format summary
table 5-2 interface control register
table 5-3 register setting for different output formats
5.2 data compression algorithm
5.2.1 12b to 10b
figure 5-1 12-bit to 10-bit PWL compression
5.3 staggered HDR output
5.3.1 MIPI
figure 5-2 staggered HDR with MIPI virtual channel diagram
figure 5-3 staggered HDR with MIPI virtual channel detail diagram
figure 5-4 staggered HDR without MIPI virtual channel overview diagram
figure 5-5 staggered HDR without MIPI virtual channel detail diagram
table 5-4 supported output formats and frame rates for MIPI
figure 5-6 12b linear mode diagram
figure 5-7 10b linear mode diagram
figure 5-8 12b (10b) HCG or LCG + 12b (10b) VS dual HDR diagram
5.3.2 LVDS
figure 5-9 staggered HDR with LVDS dedicated lane (4-lane) diagram
figure 5-10 staggered HDR with LVDS dedicated lane (2-lane) diagram
table 5-5 supported output formats and frame rates for LVDS
figure 5-11 12 bits linear mode diagram
figure 5-12 10 bits linear mode diagram
figure 5-13 12b (10b) HCG or LCG + 12b (10b) VS dual HDR diagram
5.3.3 DVP
figure 5-14 staggered HDR with DVP diagram
table 5-6 supported output formats and frame rates for DVP
figure 5-15 12 bits linear mode diagram
figure 5-16 10 bits linear mode diagram
figure 5-17 12b HCG or LCG + 12b VS diagram
5.4 instructions for backend control
5.4.1 VS data path delay
figure 5-18 sensor frame control signals diagram
table 5-7 VS data path delay register s
5.5 register writing
5.5.1 suggestion for writing register value just after VSYNC or FS
5.6 embedded data
5.6.1 embedded data format at output
figure 5-19 embedded data layout diagram
table 5-8 embedded data registers
5.7 group hold
table 5-9 group hold control registers (sheet 1 of 2)
6 SCCB interface
6.1 SCCB timing
figure 6-1 SCCB interface timing
table 6-1 SCCB interface timing specifications
6.2 direct access mode
6.2.1 message format
figure 6-2 message type
6.2.2 read / write operation
figure 6-3 SCCB single read from random location
figure 6-4 SCCB single read from current location
figure 6-5 SCCB sequential read from random location
figure 6-6 SCCB sequential read from current location
figure 6-7 SCCB single write to random location
figure 6-8 SCCB sequential write to random location
7 operating specifications
7.1 absolute maximum ratings
table 7-1 absolute maximum ratings
7.2 functional temperature
table 7-2 functional temperature
7.3 DC characteristics
table 7-3 DC characteristics (-30°C < TJ < 85°C)
7.4 AC characteristics
table 7-4 AC characteristics (TA = 25°C, VDD3.3 = 3.3V, VDD1.8 = 1.8V)
table 7-5 timing characteristics
8 mechanical specifications
8.1 physical specifications
figure 8-1 package specifications
table 8-1 package dimensions
8.2 IR reflow specifications
figure 8-2 IR reflow ramp rate requirements
table 8-2 reflow conditions
9 optical specifications
9.1 sensor array center
figure 9-1 sensor array center
9.2 lens chief ray angle (CRA)
figure 9-2 chief ray angle (CRA)
table 9-1 CRA versus image height plot
appendix A register table
revision history
datasheet
PRELIMINARY SPECIFICATION
1/2.9" color CMOS 1080p (1920 x 1080) high dynamic range (HDR)
high definition (HD) image sensor
8
1
7
2
V
O
1
color CMOS 1080p (1920x1080) high dynamic range (HDR) high definition image sensor
OV2718
00Copyright ©2015 OmniVision Technologies, Inc. All rights reserved.
This document is provided “as is” with no warranties whatsoever, including any warranty of merchantability,
non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification,
or sample.
OmniVision Technologies, Inc. and all its affiliates disclaim all liability, including liability for infringement of any proprietary
rights, relating to the use of information in this document. No license, expressed or implied, by estoppel or otherwise, to
any intellectual property rights is granted herein.
The information contained in this document is considered proprietary to OmniVision Technologies, Inc. and all its
affiliates. This information may be distributed to individuals or organizations authorized by OmniVision Technologies, Inc.
to receive said information. Individuals and/or organizations are not allowed to re-distribute said information.
Trademark Information
OmniVision and the OmniVision logo are registered trademarks of OmniVision Technologies, Inc. OmniBSI-2 is a
trademark of OmniVision Technologies, Inc.
All other trademarks used herein are the property of their respective owners.
color CMOS 1080p (1920x1080) high dynamic range (HDR) high definition image sensor
datasheet (CSP5)
PRELIMINARY SPECIFICATION
version 1.11
july 2015
To learn more about OmniVision Technologies, visit www.ovt.com.
OmniVision Technologies is publicly traded on NASDAQ under the symbol OVTI.
2
iii
Since it is
note
impossible to check
compatibility with all
displays, check the
interoperability before
committing to mass
production.
To reduce
note
image artifacts from
Infrared light, and
provide the best image
quality, OmniVision
recommends an IR cut
filter
00applications
security and surveillance cameras
ordering information
OV02718-A77A-Z (color, lead-free)
77-pin CSP5
00features
support for image size: 1920x1080, VGA, QVGA and
any cropped size
high dynamic range
high sensitivity
low power consumption
image sensor processor functions: lens correction,
defective pixel cancelation, and automatic black level
correction
supported output formats: RAW
00key specifications (typical)
active array size: 1920 x 1080
power supply:
analog: 3.14 ~ 3.47V
digital: 1.14 ~ 1.26V
DOVDD: 1.7 ~ 1.9V
AVDD: 1.7 ~ 1.9V
power requirements:
active: TBD
standby: TBD
temperature range:
operating: -40°C to 85°C sensor ambient
temperature and -30°C to 85°C junction
temperature (see table 7-2)
output interfaces: up to 4-lane MIPI CSI-2/LVDS,
12-bit DVP
input clock frequency: 6 ~ 36 MHz
lens size: 1/2.9"
horizontal and vertical sub-sampling
SCCB for register programming
high speed serial data transfer with MIPI CSI-2/LVDS
parallel 12-bit DVP output
external frame synchronization capability
embedded temperature sensor
one time programmable (OTP) memory
lens chief ray angle: 9° (see figure 9-2)
output formats: linear - 12-bit RAW, 10-bit
compressed RAW; 2x12 bit RAW; dual exposure
HDR - 12-bit (10-bit) RAW (HCG or LCG) + 12-bit
(10-bit) VS
scan mode: progressive
shutter: rolling shutter
maximum image transfer rate: 60 fps full resolution
sensitivity: TBD
max S/N ratio: TBD
dynamic range: TBD
pixel size: 2.8 µm x 2.8 µm
dark current: TBD
image area: 5482.35 μm x 3202 μm
package dimensions: 6534 μm x 5724 μm
version 1.11, july 21, 2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
3
color CMOS 1080p (1920x1080) high dynamic range (HDR) high definition image sensor
OV2718
00table of contents
1 application system
1.1 overview
1.2 signal description and pin assignment
1.3 reference design
1.3.1 external components
1.3.2 power on reset (POR) generation
1.4 power up sequence/ boot sequence
1.4.1 power down sequence
1.4.2 operating modes
1.4.3 activation sequence
1.4.4 deactivation sequence
1.4.5 early activation
2 sensor architecture
3 image sensor core
3.1 pixel array structure
3.2 pixel array access
3.3 mirror and flip
3.4 sub-sampling
3.5 frame timing and maximum frame rate
3.6 exposure control
3.7 black level calibration (BLC)
3.7.1 advanced operation of the BLC
3.8 PLL
3.9 temperature sensor
4 image processor
4.1 test pattern
4.1.1 analog color bar overlay
4.1.2 digital test patterns
4.2 lens correction (LENC)
4.3 auto white balance gain (AWB gain)
4.4 defective pixel cancellation (DPC)
5 image output interface
5.1 image output format
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28
30
31
32
33
37
39
39
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47
48
49
49
50
53
56
60
70
70
version 1.11, july 21, 2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
4
v
5.2 data compression algorithm
5.2.1 12b to 10b
5.3 staggered HDR output
5.3.1 MIPI
5.3.2 LVDS
5.3.3 DVP
5.4 instructions for backend control
5.4.1 VS data path delay
5.5 register writing
5.5.1 suggestion for writing register value just after VSYNC or FS
5.6 embedded data
5.6.1 embedded data format at output
5.7 group hold
6 SCCB interface
6.1 SCCB timing
6.2 direct access mode
6.2.1 message format
6.2.2 read / write operation
7 operating specifications
7.1 absolute maximum ratings
7.2 functional temperature
7.3 DC characteristics
7.4 AC characteristics
8 mechanical specifications
8.1 physical specifications
8.2 IR reflow specifications
9 optical specifications
9.1 sensor array center
9.2 lens chief ray angle (CRA)
appendix A register table
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79
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82
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83
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87
90
90
90
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92
93
93
94
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97
version 1.11, july 21, 2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
5
color CMOS 1080p (1920x1080) high dynamic range (HDR) high definition image sensor
OV2718
00list of figures
pin diagram
figure 1-1
OV2718 MIPI reference schematic
figure 1-2
OV2718 DVP reference schematic
figure 1-3
OV2718 power supplies and recommended external decoupling
figure 1-4
power on timing diagram
figure 1-5
OV2718 block diagram
figure 2-1
sensor core block diagram
figure 3-1
pixel array region color filter layout
figure 3-2
integration time diagram
figure 3-3
pixel array access diagram
figure 3-4
horizontal mirror and vertical flip samples
figure 3-5
horizontal and vertical sub-sampling
figure 3-6
row address versus time graph
figure 3-7
frame output timing diagram
figure 3-8
figure 3-9
PLL1 control diagram
figure 3-10 PLL2 control diagram
figure 4-1
figure 4-2
figure 4-3
figure 4-4
figure 4-5
figure 4-6
figure 4-7
figure 4-8
figure 4-9
figure 4-10 black and white squares test pattern
figure 4-11 chart test pattern
figure 4-12 coefficient gain graph
figure 4-13 threshold gain curve
figure 4-14 defect pattern examples
figure 4-15 adaptive thresholds
figure 4-16 connected case thresholds
image processor block diagram
color bar types
vertical bars test pattern
vertical bars with vertical gradient test pattern
vertical bars with horizontal gradient test pattern
vertical bars with diagonal gradient test pattern
vertical bars with rolling line test pattern
random image test pattern
color squares test pattern
17
20
21
22
23
26
28
28
29
30
31
32
33
34
44
45
48
49
50
50
50
50
51
51
51
51
52
53
60
60
61
61
version 1.11, july 21, 2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
6
vii
12-bit to 10-bit PWL compression
figure 5-1
staggered HDR with MIPI virtual channel diagram
figure 5-2
staggered HDR with MIPI virtual channel detail diagram
figure 5-3
staggered HDR without MIPI virtual channel overview diagram
figure 5-4
staggered HDR without MIPI virtual channel detail diagram
figure 5-5
12b linear mode diagram
figure 5-6
10b linear mode diagram
figure 5-7
12b (10b) HCG or LCG + 12b (10b) VS dual HDR diagram
figure 5-8
staggered HDR with LVDS dedicated lane (4-lane) diagram
figure 5-9
figure 5-10 staggered HDR with LVDS dedicated lane (2-lane) diagram
figure 5-11 12 bits linear mode diagram
figure 5-12 10 bits linear mode diagram
figure 5-13 12b (10b) HCG or LCG + 12b (10b) VS dual HDR diagram
figure 5-14 staggered HDR with DVP diagram
figure 5-15 12 bits linear mode diagram
figure 5-16 10 bits linear mode diagram
figure 5-17 12b HCG or LCG + 12b VS diagram
figure 5-18 sensor frame control signals diagram
figure 5-19 embedded data layout diagram
figure 6-1
figure 6-2
figure 6-3
figure 6-4
figure 6-5
figure 6-6
figure 6-7
figure 6-8
figure 8-1
figure 8-2
figure 9-1
figure 9-2
SCCB interface timing
message type
SCCB single read from random location
SCCB single read from current location
SCCB sequential read from random location
SCCB sequential read from current location
SCCB single write to random location
SCCB sequential write to random location
package specifications
IR reflow ramp rate requirements
sensor array center
chief ray angle (CRA)
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79
79
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version 1.11, july 21, 2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
7
color CMOS 1080p (1920x1080) high dynamic range (HDR) high definition image sensor
OV2718
00list of tables
table 1-1
table 1-2
table 1-3
table 1-4
table 1-5
table 3-1
table 3-2
table 3-3
table 3-4
table 3-5
table 3-6
table 3-7
table 3-8
table 4-1
table 4-2
table 4-3
table 4-4
table 5-1
table 5-2
table 5-3
table 5-4
table 5-5
table 5-6
table 5-7
table 5-8
table 5-9
table 6-1
table 7-1
table 7-2
table 7-3
table 7-4
table 7-5
signal descriptions
pin states under various conditions
GPIO control registers
pad equivalent circuit
power on timing
register setting for mirror
supported output formats and frame rates for MIPI/LVDS
supported output formats and frame rates for DVP
timing control registers
exposure control registers
BLC control registers
PLL control registers
temperature sensor registers
test pattern control registers
LENC control registers
AWB control registers
DPC registers
image output format summary
interface control register
register setting for different output formats
supported output formats and frame rates for MIPI
supported output formats and frame rates for LVDS
supported output formats and frame rates for DVP
VS data path delay register s
embedded data registers
group hold control registers
SCCB interface timing specifications
absolute maximum ratings
functional temperature
DC characteristics (-30°C < TJ < 85°C)
AC characteristics (TA = 25°C, VDD3.3 = 3.3V, VDD1.8 = 1.8V)
timing characteristics
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90
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92
version 1.11, july 21, 2015
PRELIMINARY SPECIFICATION
proprietary to OmniVision Technologies
8
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