MAX II Device Handbook
Contents
Chapter Revision Dates
About this Handbook
How to Contact Altera
Typographic Conventions
Section I. MAX II Device Family Data Sheet
Revision History
1. Introduction
Introduction
Features
Referenced Documents
Document Revision History
2. MAX II Architecture
Introduction
Functional Description
Logic Array Blocks
LAB Interconnects
LAB Control Signals
Logic Elements
LUT Chain and Register Chain
addnsub Signal
LE Operating Modes
MultiTrack Interconnect
Global Signals
User Flash Memory Block
UFM Storage
Internal Oscillator
Program, Erase, and Busy Signals
Auto-Increment Addressing
Serial Interface
UFM Block to Logic Array Interface
MultiVolt Core
I/O Structure
Fast I/O Connection
I/O Blocks
I/O Standards and Banks
Schmitt Trigger
Output Enable Signals
Programmable Drive Strength
Slew-Rate Control
Open-Drain Output
Programmable Ground Pins
Bus Hold
Programmable Pull-Up Resistor
Programmable Input Delay
MultiVolt I/O Interface
Referenced Documents
Document Revision History
3. JTAG and In-System Programmability
Introduction
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
JTAG Block
In System Programmability
IEEE 1532 Support
Jam Standard Test and Programming Language (STAPL)
Programming Sequence
UFM Programming
In-System Programming Clamp
Real-Time ISP
Design Security
Programming with External Hardware
Referenced Documents
Document Revision History
4. Hot Socketing and Power-On Reset in MAX II Devices
Introduction
MAX II Hot-Socketing Specifications
Devices Can Be Driven before Power-Up
I/O Pins Remain Tri-Stated during Power-Up
Signal Pins Do Not Drive the VCCIO or VCCINT Power Supplies
AC and DC Specifications
Hot Socketing Feature Implementation in MAX II Devices
Power-On Reset Circuitry
Power-Up Characteristics
Referenced Documents
Document Revision History
5. DC and Switching Characteristics
Introduction
Operating Conditions
Absolute Maximum Ratings
Recommended Operating Conditions
Programming/Erasure Specifications
DC Electrical Characteristics
Output Drive Characteristics
I/O Standard Specifications
Bus Hold Specifications
Power-Up Timing
Power Consumption
Timing Model and Specifications
Preliminary and Final Timing
Performance
Internal Timing Parameters
External Timing Parameters
External Timing I/O Delay Adders
Maximum Input and Output Clock Rates
JTAG Timing Specifications
Referenced Documents
Document Revision History
6. Reference and Ordering Information
Software
Device Pin-Outs
Ordering Information
Referenced Documents
Document Revision History
Section II. PCB Layout Guidelines
Revision History
7. Package Information
Introduction
Board Decoupling Guidelines
Device and Package Cross Reference
Thermal Resistance
Package Outlines
68-Pin Micro FineLine Ball-Grid Array (MBGA) – Wire Bond
100-Pin Plastic Thin Quad Flat Pack (TQFP)
100-Pin Micro FineLine Ball-Grid Array (MBGA)
100-Pin FineLine Ball-Grid Array (FBGA)
144-Pin Plastic Thin Quad Flat Pack (TQFP)
144-Pin Micro FineLine Ball-Grid Array (MBGA) – Wire Bond
256-Pin Micro FineLine Ball-Grid Array (MBGA)
256-Pin FineLine Ball-Grid Array (FBGA)
324-Pin FineLine Ball-Grid Array (FBGA)
Document Revision History
8. Using MAX II Devices in Multi-Voltage Systems
Introduction
I/O Standards
MultiVolt Core and I/O Operation
5.0-V Device Compatibility
Recommended Operating Condition for 5.0-V Compatibility
Hot Socketing
Power-Up Sequencing
Power-On Reset
Conclusion
Referenced Documents
Document Revision History
Section III. User Flash Memory
Revision History
9. Using User Flash Memory in MAX II Devices
Introduction
UFM Array Description
Memory Organization Map
Using and Accessing UFM Storage
UFM Functional Description
UFM Address Register
UFM Data Register
UFM Program/Erase Control Block
Oscillator
UFM Operating Modes
Read/Stream Read
Program
Erase
Programming and Reading the UFM with JTAG
Software Support for UFM Block
Inter-Integrated Circuit
Serial Peripheral Interface
Parallel Interface
None (Altera Serial Interface)
Creating Memory Content File
Simulation Parameters
Conclusion
Referenced Documents
Document Revision History
10. Replacing Serial EEPROMs with MAX II User Flash Memory
Introduction
Design Considerations
List of Vendors and Devices
Conclusion
Referenced Documents
Document Revision History
Section IV. In-System Programmability
Revision History
11. In-System Programmability Guidelines for MAX II Devices
Introduction
General ISP Guidelines
Operating Conditions
UFM Operations During In-System Programming
Interrupting In-System Programming
MultiVolt Devices and Power-Up Sequences
I/O Pins Tri-Stated during In-System Programming
Pull-Up and Pull-Down of JTAG Pins During In-System Programming
IEEE Std. 1149.1 Signals
TCK Signal
Programming via a Download Cable
Disabling IEEE Std. 1149.1 Circuitry
Working with Different Voltage Levels
Sequential versus Concurrent Programming
Sequential Programming
Concurrent Programming
ISP Troubleshooting Guidelines
Invalid ID and Unrecognized Device Messages
Troubleshooting Tips
ISP via Embedded Processors
Processor and Memory Requirements
Porting the Jam Player
ISP via In-Circuit Testers
Conclusion
Referenced Documents
Document Revision History
12. Real-Time ISP and ISP Clamp for MAX II Devices
Introduction
Real-Time ISP
How Real-Time ISP Works
Real-Time ISP with the Quartus II Software
Real-Time ISP with Jam and JBC Players
ISP Clamp
How ISP Clamp Works
Using ISP Clamp in the Quartus II Software
ISP Clamp with Jam/JBC Files
Conclusion
Referenced Documents
Document Revision History
13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for MAX II Devices
Introduction
IEEE Std. 1149.1 BST Architecture
IEEE Std. 1149.1 Boundary-Scan Register
Boundary-Scan Cells of a MAX II Device I/O Pin
JTAG Pins and Power Pins
IEEE Std. 1149.1 BST Operation Control
SAMPLE/PRELOAD Instruction Mode
EXTEST Instruction Mode
BYPASS Instruction Mode
IDCODE Instruction Mode
USERCODE Instruction Mode
CLAMP Instruction Mode
HIGHZ Instruction Mode
I/O Voltage Support in JTAG Chain
BST for Programmed Devices
Disabling IEEE Std. 1149.1 BST Circuitry
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
Boundary-Scan Description Language (BSDL) Support
Conclusion
Referenced Documents
Document Revision History
14. Using Jam STAPL for ISP via an Embedded Processor
Introduction
Embedded Systems
Connecting the JTAG Chain to the Embedded Processor
Board Layout
Software Development
Jam Files (.jam and .jbc)
Generating Jam Files
Jam Players
Updating Devices Using Jam
MAX II Jam/JBC Actions and Procedure Commands
Conclusion
Referenced Documents
Document Revision History
15. Using the Agilent 3070 Tester for In- System Programming
Introduction
New PLD Product for Agilent 3070
Device Support
Agilent 3070 Development Flow without the PLD ISP Software
Step 1: Create a PCB and Test Fixture
Step 2: Create a Serial Vector Format File
Step 3: Convert SVF Files to PCF Files
Step 4: Create Executable Tests from Files
Step 5: Compile the Executable Tests
Step 6: Debug the Test
Development Flow for Agilent 3070 with PLD ISP Software
Programming Times
Guidelines
Conclusion
Referenced Documents
Document Revision History
Section V. Design Considerations
Revision History
16. Understanding Timing in MAX II Devices
Introduction
External Timing Parameters
Internal Timing Parameters
Internal Timing Parameters for MAX II UFM
Timing Models
Calculating Timing Delays
Programmable Input Delay
Timing Model versus Quartus II Timing Analyzer
Conclusion
Referenced Documents
Document Revision History
17. Understanding and Evaluating Power in MAX II Devices
Introduction
Power in MAX II Devices
MAX II Power Estimation Using the PowerPlay Early Power Estimator
PowerPlay Early Power Estimator Inputs
Input Parameters
Clock Section
Logic Section
UFM Section
I/O Section
Other Input Information
Power Estimation Summary
Power
Thermal Analysis
Power Supply Current
Power Saving Techniques
Conclusion
Referenced Documents
Document Revision History