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FlexRay协议V2.1A.pdf
Chapter 1 Introduction
1.1 Scope
1.2 References
1.2.1 FlexRay consortium documents
[EPL05]
[EPLAN05]
[DLLCT05]
[Req05]
[Mül01]
[Ung02]
1.2.2 Non-consortium documents
[Cas93]
[Koo02]
[Pet72]
[Rau02]
[Wad01]
[Wel88]
[Z100]
1.3 Revision history
Table 1-1: Revision history
1.4 Terms and definitions
application data
bus
bus driver
bus guardian
channel
channel idle
clique
cluster
coldstart node
communication channel
communication controller (CC)
communication cycle
communication slot
cycle counter
cycle time
dynamic segment
dynamic communication slot
frame
frame identifier
gateway
global time
Hamming distance
host
macrotick
medium idle
microtick
minislot
network
network topology
node
null frame
physical communication link
precision
slot
star
startup frame
startup slot
static communication slot
static segment
sync frame
sync slot
1.5 Acronyms and abbreviations
1.6 Notational conventions
1.6.1 Parameter prefix conventions
Table 1-2: Parameter prefix 1.
Table 1-3: Parameter prefix 2.
1.6.2 Color coding
1.7 SDL conventions
1.7.1 General
1.7.2 SDL Notational Conventions
1.7.3 SDL Extensions
1.7.3.1 Microtick, macrotick and sample tick timers
1.7.3.2 Microtick behavior of the 'now' - expression
1.7.3.3 Channel-specific process replication
1.7.3.4 Handling of Priority Input Symbols
1.8 Network topology considerations
1.8.1 Passive bus topology
Figure 1-1: Dual channel bus configuration.
1.8.2 Active star topology
Figure 1-2: Dual channel single star configuration.
Figure 1-3: Single channel cascaded star configuration.
Figure 1-4: Dual channel cascaded star configuration.
1.8.3 Active star topology combined with a passive bus topology
Figure 1-5: Single channel hybrid example.
Figure 1-6: Dual channel hybrid example.
1.9 Example node architecture
1.9.1 Objective
1.9.2 Overview
Figure 1-7: Logical interfaces.
1.9.3 Host - communication controller interface
Figure 1-8: Host - communication controller interfaces.
1.9.4 Communication controller - bus driver interface
Figure 1-9: Communication controller - bus driver interface.
1.9.5 Bus driver - host interface
1.9.5.1 Hard wired signals (option A)
Figure 1-10: Example bus driver - host interface (option A).
1.9.5.2 Serial Peripheral Interface (SPI) (option B)
Figure 1-11: Example bus driver - host interface (option B).
1.9.6 Bus driver - power supply interface (optional)
Figure 1-12: Bus driver - power supply interface.
1.10 Testability Requirements
Chapter 2 Protocol Operation Control
2.1 Principles
2.1.1 Communication controller power moding
Figure 2-1: Power moding of the communication controller.
Table 2-1: Communication controller power moding thresholds.
2.2 Description
Figure 2-2: Protocol operation control context.
2.2.1 Operational overview
2.2.1.1 Host commands
Table 2-2: CHI host command summary.
2.2.1.2 Error conditions
2.2.1.2.1 Errors causing immediate entry to the POC:halt state
2.2.1.2.2 Errors handled by the degradation model
2.2.1.3 POC status
Definition 2-1: Formal definition of T_POCStatus.
Definition 2-2: Formal definition of T_POCState.
Definition 2-3: Formal definition of T_SlotMode.
Definition 2-4: Formal definition of T_ErrorMode.
Definition 2-5: Formal definition of T_WakeupStatus.
Definition 2-6: Formal definition of T_StartupState.
2.2.1.4 SDL considerations for single channel nodes
2.3 The Protocol Operation Control process
Figure 2-3: Overview of protocol operation control.
2.3.1 POC SDL utilities
Figure 2-4: Macros to mode the core mechanisms for transitions to the POC:ready and POC:halt stat...
Figure 2-5: Macros for creating and terminating processes [POC].
2.3.2 SDL organization
2.3.3 Preempting commands
Figure 2-6: POC preempting commands [POC].
2.3.4 Reaching the POC:ready state
Figure 2-7: Reaching the POC:ready state [POC].
2.3.5 Reaching the POC:normal active state
Figure 2-8: POC behavior in preparation for normal operation [POC].
2.3.5.1 Wakeup and startup support
Figure 2-9: Conditions detected in support of the wakeup and startup procedures [POC].
Definition 2-7: Formal definition of T_ChannelBoolArray.
Definition 2-8: Formal definition of T_Channel.
2.3.6 Behavior during normal operation
2.3.6.1 Asynchronous commands
Figure 2-10: Capture of asynchronous host commands for end-of-cycle processing [POC].
2.3.6.2 Cyclical behavior
2.3.6.2.1 Cycle counter
Figure 2-11: POC determination of the cycle counter value [POC].
2.3.6.2.2 POC:normal active state
Figure 2-12: Cyclical behavior in the POC:normal active state [POC].
2.3.6.2.3 POC:normal passive state
Figure 2-13: Cyclical behavior in the POC:normal passive state [POC].
2.3.6.2.4 Error checking during normal operation
2.3.6.2.4.1 Error checking overview
2.3.6.2.4.2 Error checking details for the POC:normal active state
Figure 2-14: Error checking in the POC:normal active state [POC].
2.3.6.2.4.3 Error checking details for the POC:normal passive state
Figure 2-15: Error checking in the POC:normal passive state [POC].
Chapter 3 Coding and Decoding
3.1 Principles
3.2 Description
Figure 3-1: Coding / Decoding context
3.2.1 Frame and symbol encoding
3.2.1.1 Frame encoding
3.2.1.1.1 Transmission start sequence
3.2.1.1.2 Frame start sequence
3.2.1.1.3 Byte start sequence
3.2.1.1.4 Frame end sequence
3.2.1.1.5 Dynamic trailing sequence
3.2.1.1.6 Frame bit stream assembly
Figure 3-2: Frame encoding in the static segment.
Figure 3-3: Frame encoding in the dynamic segment.
3.2.1.2 Symbol encoding
3.2.1.2.1 Collision avoidance symbol and media access test symbol
Figure 3-4: CAS and MTS symbol encoding.
3.2.1.2.2 Wakeup symbol
Figure 3-5: Wakeup pattern consisting of two wakeup symbols.
Figure 3-6: Wakeup symbol collision and wakeup pattern reception.
3.2.2 Sampling and majority voting
Figure 3-7: Sampling and majority voting of the RxD input.
3.2.3 Bit clock alignment and bit strobing
Figure 3-8: Bit synchronization.
3.2.4 Channel idle detection
3.2.5 Action point and time reference point
Figure 3-9: TSS truncation and propagation.
Figure 3-10: Time reference point definitions.
3.2.6 Frame and symbol decoding
3.2.6.1 Frame decoding
Figure 3-11: Received frame bit stream.
3.2.6.2 Symbol decoding
3.2.6.2.1 Collision avoidance symbol and media access test symbol decoding
Figure 3-12: Received symbol bit stream.
3.2.6.2.2 Wakeup symbol decoding
3.2.6.3 Decoding error
Figure 3-13: Start of frame with FSS BSS decoding.
3.2.7 Signal integrity
3.3 Coding and decoding process
3.3.1 Operating modes
Definition 3-1: Formal definition of T_CodecMode.
Figure 3-14: Overview of processes and transitions in the encoder/decoder.
3.3.2 Coding and decoding process behavior
Figure 3-15: CODEC process [CODEC_A].
Figure 3-16: Mode control of the CODEC process [CODEC_A].
Figure 3-17: Termination of the CODEC process [CODEC_A].
3.3.3 Encoding behavior
Definition 3-2: Formal definition of T_TransmitFrame.
Definition 3-3: Formal definition of T_BitLevel.
Definition 3-4: Formal definition of T_BitStreamArray.
Figure 3-18: Frame encoding [CODEC_A].
Definition 3-5: Formal definition of T_Type.
3.3.4 Encoding macros
Figure 3-19: Encoding macro TRANSMIT_FES [CODEC_A].
Figure 3-20: Encoding macro TRANSMIT_DTS [CODEC_A].
Figure 3-21: Encoding macro TRANSMIT_BIT_STREAM [CODEC_A].
Figure 3-22: Encoding macro WUP_ENCODING [CODEC_A].
Figure 3-23: Macro WUSTXIDLE_DECODING [CODEC_A].
3.3.5 Decoding behavior
Figure 3-24: Macro DECODING [CODEC_A].
3.3.6 Decoding macros
Definition 3-6: Formal definition of T_ByteArray.
Definition 3-7: Formal definition of T_ByteStreamArray.
Definition 3-8: Formal definition of T_CRCCheckPassed.
Definition 3-9: Formal definition of T_MicrotickTime.
Definition 3-10: Formal definition of T_ReceiveFrame.
Figure 3-25: Decoding macro WAIT_FOR_CE_START [CODEC_A].
Figure 3-26: Decoding macro TSS_DECODING [CODEC_A].
Figure 3-27: Decoding macro SYMBOL_DECODING [CODEC_A].
Figure 3-28: Decoding macro FSS_BSS_DECODING [CODEC_A].
Figure 3-29: Decoding macro HEADER_DECODING [CODEC_A].
Figure 3-30: Procedure for Byte Decoding [CODEC_A].
Figure 3-31: Procedure for BSS Decoding [CODEC_A].
Figure 3-32: Decoding macro FES_DECODING [CODEC_A].
Figure 3-33: Decoding macro PAYLOAD_DECODING [CODEC_A].
Figure 3-34: Decoding macro TRAILER_DECODING [CODEC_A].
3.4 Bit strobing process
3.4.1 Operating modes
Definition 3-11: Formal definition of T_StrbMode.
3.4.2 Bit strobing process behavior
Figure 3-35: BITSTRB process [BITSTRB_A].
Figure 3-36: BITSTRB process macro CE_AND_IDLE_CHECK [BITSTRB_A].
Figure 3-37: BITSTRB process control and process termination [BITSTRB_A].
3.5 Wakeup pattern decoding process
3.5.1 Operating modes
Definition 3-12: Formal definition of T_WupDecMode.
3.5.2 Wakeup decoding process behavior
Figure 3-38: Control of the wakeup pattern detection process and its termination [WUPDEC_A].
3.5.3 Wakeup decoding macros
Figure 3-39: Wakeup pattern decoding Macro [WUPDEC_A].
Chapter 4 Frame Format
4.1 Overview
Figure 4-1: FlexRay frame format.
4.2 FlexRay header segment (5 bytes)
4.2.1 Reserved bit (1 bit)
Definition 4-1: Formal definition of T_Reserved.
4.2.2 Payload preamble indicator (1 bit)
Definition 4-2: Formal definition of T_PPIndicator.
4.2.3 Null frame indicator (1 bit)
Definition 4-3: Formal definition of T_NFIndicator.
4.2.4 Sync frame indicator (1 bit)
Definition 4-4: Formal definition of T_SyFIndicator.
4.2.5 Startup frame indicator (1 bit)
Definition 4-5: Formal definition of T_SuFIndicator.
4.2.6 Frame ID (11 bits)
Definition 4-6: Formal definition of T_FrameID.
4.2.7 Payload length (7 bits)
Definition 4-7: Formal definition of T_Length.
4.2.8 Header CRC (11 bits)
Definition 4-8: Formal definition of T_HeaderCRC.
4.2.9 Cycle count (6 bits)
Definition 4-9: Formal definition of T_CycleCounter.
4.2.10 Formal header definition
Definition 4-10: Formal definition of T_Header.
4.3 FlexRay payload segment (0 - 254 bytes)
Definition 4-11: Formal definition of T_Payload.
4.3.1 NMVector (optional)
Figure 4-2: Payload segment of frames transmitted in the static segment.
4.3.2 Message ID (optional, 16 bits)
Figure 4-3: Payload segment of frames transmitted in the dynamic segment.
4.4 FlexRay trailer segment
Definition 4-12: Formal definition of T_FrameCRC.
4.5 CRC calculation details
4.5.1 CRC calculation algorithm
4.5.2 Header CRC calculation
4.5.3 Frame CRC calculation
Chapter 5 Media Access Control
5.1 Principles
5.1.1 Communication cycle
Figure 5-1: Timing hierarchy within the communication cycle.
5.1.2 Communication cycle execution
Figure 5-2: Time base triggered communication cycle.
5.1.3 Static segment
5.1.3.1 Structure of the static segment
5.1.3.2 Execution and timing of the static segment
Figure 5-3: Structure of the static segment.
Figure 5-4: Timing within the static segment.
5.1.4 Dynamic segment
5.1.4.1 Structure of the dynamic segment
5.1.4.2 Execution and timing of the dynamic segment
Figure 5-5: Structure of the dynamic segment.
Figure 5-6: Timing within a minislot.
Figure 5-7: Timing within the dynamic segment.
Figure 5-8: Timing at the boundary between the static and dynamic segments.
5.1.5 Symbol window
Figure 5-9: Timing within the symbol window.
5.1.6 Network idle time
5.2 Description
Figure 5-10: Media access control context.
5.2.1 Operating modes
Definition 5-1: Formal definition of T_MacMode.
5.2.2 Significant events
5.2.2.1 Reception-related events
Figure 5-11: Reception-related events for MAC.
5.2.2.2 Transmission-related events
Figure 5-12: Transmission-related events for MAC.
5.2.2.3 Timing-related events
5.3 Media access control process
5.3.1 Initialization and state MAC:standby
Figure 5-13: Media access process [MAC_A].
Figure 5-14: Media access control [MAC_A].
Figure 5-15: Termination of the MAC process [MAC_A].
5.3.2 Static segment related states
5.3.2.1 State machine for the static segment media access control
Figure 5-16: Media access in the static segment [MAC_A].
Figure 5-17: Media access in the static segment [MAC_A].
Definition 5-2: Formal definition of T_TransmitFrame.
Definition 5-3: Formal definition of T_SlotCounter.
5.3.2.2 Transmission conditions and frame assembly in the static segment
Definition 5-4: Formal definition of T_CHITransmission.
Definition 5-5: Formal definition of T_Assignment.
Figure 5-18: Frame assembly in the static segment [MAC_A].
5.3.3 Dynamic segment related states
5.3.3.1 State machine for the dynamic segment media access control
Figure 5-19: Media access in the dynamic segment [MAC_A].
Figure 5-20: Media access in the dynamic segment start [MAC_A].
Figure 5-21: Media access in the dynamic segment arbitration [MAC_A].
Figure 5-22: Minislot counting during transmission [MAC_A].
Figure 5-23: Dynamic segment termination in the event of slot counter exhaustion [MAC_A].
5.3.3.2 Transmission conditions and frame assembly in the dynamic segment
Figure 5-24: Frame assembly in the dynamic segment [MAC_A].
5.3.4 Symbol window related states
5.3.4.1 State machine for the symbol window media access control
Figure 5-25: Media access in the symbol window [MAC_A].
Figure 5-26: Media access in the symbol window [MAC_A].
5.3.4.2 Transmission condition in the symbol window
5.3.5 Network idle time
Figure 5-27: Network idle time [MAC_A].
Chapter 6 Frame and Symbol Processing
6.1 Principles
6.2 Description
Figure 6-1: Frame and symbol processing context.
6.2.1 Operating modes
Definition 6-1: Formal definition of T_FspMode.
6.2.2 Significant events
6.2.2.1 Reception-related events
Figure 6-2: Reception-related events for FSP.
Definition 6-2: Formal definition of T_ReceiveFrame.
6.2.2.2 Decoding-related events
6.2.2.3 Timing-related events
Figure 6-3: Timing-related events for FSP.
6.2.3 Status data
Definition 6-3: Formal definition of T_SlotStatus.
Definition 6-4: Formal definition of T_Segment.
6.3 Frame and symbol processing process
Figure 6-4: State overview of the FSP state machine (shown for one channel).
6.3.1 Initialization and state FSP:standby
Figure 6-5: FSP process [FSP_A].
Figure 6-6: FSP control [FSP_A].
Figure 6-7: Termination of the FSP process [FSP_A].
6.3.2 Macro SLOT_SEGMENT_END_A
Figure 6-8: Slot and segment end macro [FSP_A].
6.3.3 State FSP:wait for CE start
Figure 6-9: Transitions from the FSP:wait for CE start state [FSP_A].
6.3.4 State FSP:decoding in progress
Figure 6-10: Transitions from the FSP:decoding in progress state [FSP_A].
Figure 6-11: Transitions from the FSP:decoding in progress state [FSP_A].
6.3.4.1 Frame reception checks during non-TDMA operation
Figure 6-12: Frame acceptance checks during non-TDMA operation [FSP_A].
6.3.4.2 Frame reception checks during TDMA operation
6.3.4.2.1 Frame reception checks in the static segment
Figure 6-13: Frame reception timing for a static slot.
Figure 6-14: Frame acceptance checks for the static segment [FSP_A].
6.3.4.2.2 Frame reception checks in the dynamic segment
Figure 6-15: Frame reception timing for a dynamic slot.
Figure 6-16: Frame acceptance checks for the dynamic segment [FSP_A].
6.3.5 State FSP:wait for CHIRP
Figure 6-17: Transitions from the FSP:wait for CHIRP state [FSP_A].
6.3.6 State FSP:wait for transmission end
Figure 6-18: Transitions from the FSP:wait for transmission end state [FSP_A].
Chapter 7 Wakeup and Startup
7.1 Cluster wakeup
7.1.1 Principles
7.1.2 Description
Figure 7-1: Protocol operation control context.
7.1.3 Wakeup support by the communication controller
7.1.3.1 Wakeup state diagram
Figure 7-2: Structure of the wakeup state machine [POC].
7.1.3.2 The POC:wakeup listen state
Figure 7-3: Transitions from the POC:wakeup listen state [POC].
7.1.3.3 The POC:wakeup send state
Figure 7-4: Transitions from the state POC:wakeup send state [POC].
7.1.3.4 The POC:wakeup detect state
Figure 7-5: Transitions from the state POC:wakeup detect state [POC].
7.1.4 Wakeup application notes
7.1.4.1 Wakeup initiation by the host
7.1.4.1.1 Single-channel nodes
7.1.4.1.2 Dual-channel nodes
Figure 7-6: A short example of how the wakeup of two channels can be accomplished in a fault- tol...
7.1.4.1.2.1 Wakeup pattern reception by the bus driver
7.1.4.1.2.2 Wakeup pattern reception by the communication controller
7.1.4.2 Host reactions to status flags signaled by the communication controller
7.1.4.2.1 Frame header reception without coding violation
7.1.4.2.2 Wakeup pattern reception
7.1.4.2.3 Wakeup pattern transmission
7.1.4.2.4 Termination due to unsuccessful wakeup pattern transmission
7.1.4.3 Retransmission of wakeup patterns
7.1.4.4 Transition to startup
7.2 Communication startup and reintegration
7.2.1 Principles
7.2.1.1 Definition and properties
7.2.1.2 Principle of operation
7.2.1.2.1 Startup performed by the coldstart nodes
7.2.1.2.2 Integration of the non-coldstart nodes
7.2.2 Description
Figure 7-7: Protocol operation control context.
7.2.3 Coldstart inhibit mode
7.2.4 Startup state diagram
Figure 7-8: Startup state diagram [POC].
Figure 7-9: Helpful macros for startup [POC].
Figure 7-10: Example of state transitions for a fault-free startup.
7.2.4.1 Path of the node initiating the coldstart (leading coldstart node)
7.2.4.2 Path of the integrating coldstart nodes (following coldstart nodes)
7.2.4.3 Path of a non-coldstart node
7.2.4.4 The POC:coldstart listen state
Figure 7-11: Transitions from the state POC:coldstart listen state [POC].
7.2.4.5 The POC:coldstart collision resolution state
Figure 7-12: Transitions from the POC:coldstart collision resolution state [POC].
7.2.4.6 The POC:coldstart consistency check state
Figure 7-13: Transitions from the state POC:coldstart consistency check state [POC].
7.2.4.7 The POC:coldstart gap state
Figure 7-14: Transitions from the POC:coldstart gap state [POC].
7.2.4.8 The POC:initialize schedule state
Figure 7-15: Transitions from the POC:initialize schedule state [POC].
7.2.4.9 The POC:integration coldstart check state
Figure 7-16: Transitions from the POC:integration coldstart check state [POC].
7.2.4.10 The POC:coldstart join state
Figure 7-17: Transitions from the POC:coldstart join state [POC].
7.2.4.11 The POC:integration listen state
Figure 7-18: Transitions from the POC:integration listen state [POC].
7.2.4.12 The POC:integration consistency check state
Figure 7-19: Transitions from the POC:integration consistency check state [POC].
Chapter 8 Clock Synchronization
8.1 Introduction
Figure 8-1: Clock synchronization context.
8.2 Time representation
8.2.1 Timing hierarchy
Figure 8-2: Timing hierarchy.
8.2.2 Global and local time
8.2.3 Parameters and variables
Definition 8-1: Formal definition of T_Macrotick and T_Microtick.
8.3 Synchronization process
Figure 8-3: Timing relationship between clock synchronization, media access schedule, and the exe...
Definition 8-2: Formal definition of T_EvenOdd and T_Deviation.
Definition 8-3: Formal definition of T_CspMode and T_SyncCalcResult.
Definition 8-4: Formal definition of T_ArrayIndex, T_SyncNodes, and T_FrameIDTable.
Figure 8-4: Clock synchronization process overview [CSP].
Figure 8-5: Clock synchronization control [CSP].
8.4 Startup of the clock
Figure 8-6: Integration control [CSP].
8.4.1 Cold start startup
8.4.2 Integration startup
Figure 8-7: Clock synchronization startup control [CSS_A].
Figure 8-8: Clock synchronization startup process on channel A [CSS_A].
8.5 Time measurement
Figure 8-9: Data structure example used in the following explanations.
8.5.1 Data structure
Definition 8-5: Formal definition of T_DevValid.
Definition 8-6: Formal definition of T_ChannelDev, T_EOChDev, and T_DevTable.
8.5.2 Initialization
Figure 8-10: Initialization of the data structure for measurement [CSP].
8.5.3 Time measurement storage
Figure 8-11: Measurement and storage of the deviation values [CSP].
8.6 Correction term calculation
8.6.1 Fault-tolerant midpoint algorithm
Table 8-1: FTM term deletion as a function of list size.
Figure 8-12: Algorithm for clock correction value calculation (k=2).
Figure 8-13: Fault Tolerant Midpoint Procedure.
8.6.2 Calculation of the offset correction value
Definition 8-7: Formal definition of T_DeviationTable.
Figure 8-14: Calculation of the offset correction value [CSP].
8.6.3 Calculation of the rate correction value
Figure 8-15: Calculation of the rate correction value [CSP].
8.6.4 Value limitations
8.6.5 External clock synchronization
Table 8-2: External clock correction states.
Definition 8-8: Formal definition of T_ExternCorrection.
8.7 Clock correction
Figure 8-16: Termination of the macrotick generation process [MTG].
Figure 8-17: Macrotick generation [MTG].
8.8 Sync frame configuration rules
Table 8-3: Configuration rules for the distributed clock synchronization.
Chapter 9 Controller Host Interface
9.1 Principles
Figure 9-1: Conceptual architecture of the controller host interface.
9.2 Description
Figure 9-2: Controller host interface context.
9.3 Interfaces
9.3.1 Protocol data interface
9.3.1.1 Protocol configuration data
9.3.1.1.1 Communication cycle timing-related protocol configuration data
9.3.1.1.2 Protocol operation-related protocol configuration data
9.3.1.1.3 Frame-related protocol configuration data
9.3.1.1.4 Symbol-related protocol configuration data
9.3.1.2 Protocol control data
9.3.1.2.1 Control of the protocol operation control
9.3.1.2.2 Control of MTS transmission
9.3.1.2.3 Control of external clock synchronization
9.3.1.3 Protocol status data
9.3.1.3.1 Protocol operation control-related status data
9.3.1.3.2 Startup-related status data
9.3.1.3.3 Time-related status data
9.3.1.3.4 Synchronization frame-related status data
9.3.1.3.5 Symbol window-related status data
Table 9-1: Symbol window status interpretation.
9.3.1.3.6 NIT-related status data
9.3.1.3.7 Aggregated channel status-related status data
9.3.1.3.8 Wakeup-related status data
9.3.1.3.9 Dynamic segment-related status data
9.3.2 Message data interface
9.3.2.1 Message transmission
9.3.2.1.1 Transmission slot assignment
9.3.2.1.2 Transmit buffer assignment
9.3.2.1.3 Transmit buffer identification for message retrieval
9.3.2.1.4 Transmit buffer-related status data
9.3.2.2 Message reception
9.3.2.2.1 Reception slot subscription and receive buffer assignment
9.3.2.2.2 Receive buffer contents
9.3.2.2.2.1 Slot status-related data
Table 9-2: Slot status interpretation.
9.3.2.2.2.2 Frame contents-related data
9.3.3 CHI Services
9.3.3.1 Macrotick timer service
9.3.3.1.1 Absolute timers
9.3.3.1.2 Relative timers
9.3.3.2 Interrupt service
9.3.3.3 Message ID filtering service
9.3.3.4 Network management service
Appendix A System Parameters
A.1 Protocol constants
Table A-1: Protocol constants.
A.1.1 cdCASRxLowMin
A.2 Physical layer constants
Table A-2: Physical layer constants.
A.2.1 cdTxMax
Table A-3: Calculation of maximum values for adTxMax.
A.3 Performance Constants
Table A-4: Performance constants.
Appendix B Configuration Constraints
B.1 General
B.2 Global cluster parameters
B.2.1 Protocol relevant
Table B-1: Global protocol relevant parameters.
B.2.2 Protocol related
Table B-2: Global protocol related parameters.
B.2.3 Physical layer relevant
B.3 Node parameters
B.3.1 Protocol relevant
Table B-3: Local node protocol relevant parameters.
B.3.2 Protocol related
Table B-4: Local node protocol related parameters.
B.3.3 Physical layer relevant
Table B-5: Local node physical layer related parameters.
B.4 Calculation of configuration parameters
B.4.1 Attainable precision
B.4.1.1 Propagation Delay
Table B-6: Maximum propagation delay in a cluster. Maximum values for LineLength, pdBDTx, pdBDRx ...
B.4.1.2 Worst-case precision
Table B-7: Calculation of the worst-case precision.
B.4.1.3 Best-case precision
Table B-8: Calculation of the best-case precision.
B.4.1.4 Assumed precision
B.4.2 Definition of microtick and macrotick
Table B-9: pdMicrotick[µs] depending on pSamplesPerMicrotick and gdSampleClockPeriod.
Table B-10: gdMacrotick[µs] depending on pMicroPerMacroNom and pdMicrotick.
B.4.3 gdMaxInitializationError
B.4.4 pdAcceptedStartupRange
B.4.5 pClusterDriftDamping
B.4.6 gdActionPointOffset
Table B-11: Calculation of values for gdActionPointOffset.
B.4.7 gdMinislotActionPointOffset
B.4.8 gdMinislot
B.4.9 gdStaticSlot
Table B-12: Calculation of minimum and maximum values for gdStaticSlot.
B.4.10 gdSymbolWindow
Table B-13: Calculation of values of gdSymbolWindow.
B.4.11 gMacroPerCycle
Table B-14: Calculation of the maximum value of gMacroPerCycle.
Table B-15: Calculation of the minimum value of gMacroPerCycle.
B.4.12 pMicroPerCycle
Table B-16: Calculation of the minimum of pMicroPerCycle.
Table B-17: Calculation of the maximum of pMicroPerCycle.
B.4.13 gdDynamicSlotIdlePhase
Table B-18: Calculation of the minimum and maximum of gdDynamicSlotIdlePhase.
B.4.14 gNumberOfMinislots
Table B-19: Calculation of maximum values for gNumberOfMinislots.
B.4.15 pRateCorrectionOut
Table B-20: Calculation of the minimum of pRateCorrectionOut.
Table B-21: Calculation of the maximum of pRateCorrectionOut.
B.4.16 Offset Correction
B.4.16.1 gOffsetCorrectionMax
Table B-22: Calculation of the minimum and maximum of gOffsetCorrectionMax.
B.4.16.2 pOffsetCorrectionOut
Table B-23: Calculation of the minimum and maximum of pOffsetCorrectionOut.
B.4.17 gOffsetCorrectionStart
B.4.18 gdNIT
Table B-24: Calculation of the maximum of gdNIT.
B.4.19 pExternRateCorrection
B.4.20 pExternOffsetCorrection
B.4.21 pdMaxDrift
Table B-25: Calculation of the maximum of pdMaxDrift.
Table B-26: Calculation of the minimum of pdMaxDrift.
B.4.22 pdListenTimeout
Table B-27: Calculation of the maximum of pdListenTimeout.
Table B-28: Calculation of the minimum of pdListenTimeout.
B.4.23 pDecodingCorrection
Table B-29: Calculation of minimum and maximum values of pDecodingCorrection.
B.4.24 pMacroInitialOffset
Table B-30: Calculation of minimum and maximum values of pMacroInitialOffset[Ch].
B.4.25 pMicroInitialOffset
Table B-31: Calculation of minimum and maximum values of pMicroInitialOffset[Ch].
B.4.26 pLatestTx
Table B-32: Calculation of the maximum values of pLatestTx.
B.4.27 gdTSSTransmitter
Table B-33: Calculation of minimum and maximum values of gdTSSTransmitter.
B.4.28 gdCASRxLowMax
Table B-34: Calculation of values of gdCASRxLowMax.
B.4.29 gdWakeupSymbolTxIdle
Table B-35: Calculation of values of gdWakeupSymbolTxIdle.
B.4.30 gdWakeupSymbolTxLow
Table B-36: Calculation of values of gdWakeupSymbolTxLow.
B.4.31 gdWakeupSymbolRxIdle
Table B-37: Calculation of values of gdWakeupSymbolRxIdle.
B.4.32 gdWakeupSymbolRxLow
Table B-38: Calculation of minimum and maximum values of gdWakeupSymbolRxLow.
B.4.33 gdWakeupSymbolRxWindow
Table B-39: Calculation of values of gdWakeupSymbolRxWindow.
FlexRay Communications System
Protocol Specification
Version 2.1
Revision A
2.1 Revision A
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FlexRay Protocol Specification
Disclaimer
Disclaimer
This specification as released by the FlexRay Consortium is intended for the purpose of information only.
The use of material contained in this specification requires membership within the FlexRay Consortium or
an agreement with the FlexRay Consortium. The FlexRay Consortium will not be liable for any unauthorized
use of this Specification.
Following the completion of the development of the FlexRay Communications System Specifications
commercial exploitation licenses will be made available to End Users by way of an End User's License
Agreement. Such licenses shall be contingent upon End Users granting reciprocal licenses to all Core
Partners and non-assertions in favor of all Premium Associate Members, Associate Members and Devel-
opment Members.
All details and mechanisms concerning the bus guardian concept are defined in the FlexRay Bus Guardian
Specifications.
The FlexRay Communications System is currently specified for a baud rate of 10 Mbit/s. It may be extended
to additional baud rates.
No part of this publication may be reproduced or utilized in any form or by any means, electronic or
mechanical, including photocopying and microfilm, without permission in writing from the publisher.
The word FlexRay and the FlexRay logo are registered trademarks.
Copyright © 2004-2005 FlexRay Consortium. All rights reserved.
The Core Partners of the FlexRay Consortium are BMW AG, DaimlerChrysler AG, Freescale Halbleiter
Deutschland GmbH, General Motors Corporation, Philips GmbH, Robert Bosch GmbH, and Volkswagen
AG.
Version 2.1 Revision A
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FlexRay Protocol Specification
Table of Contents
Table of Contents
Chapter 1
Introduction.............................................................................................................. 10
1.1 Scope .............................................................................................................................................10
1.2 References .....................................................................................................................................10
1.2.1 FlexRay consortium documents ........................................................................................... 10
1.2.2 Non-consortium documents.................................................................................................. 10
1.3 Revision history ..............................................................................................................................12
1.4 Terms and definitions .....................................................................................................................13
1.5 Acronyms and abbreviations ..........................................................................................................16
1.6 Notational conventions ...................................................................................................................18
1.6.1 Parameter prefix conventions............................................................................................... 18
1.6.2 Color coding ......................................................................................................................... 18
1.7 SDL conventions ............................................................................................................................19
1.7.1 General................................................................................................................................. 19
1.7.2 SDL Notational Conventions ................................................................................................ 19
1.7.3 SDL Extensions .................................................................................................................... 20
1.7.3.1 Microtick, macrotick and sample tick timers ................................................................. 20
1.7.3.2 Microtick behavior of the 'now' - expression ................................................................. 20
1.7.3.3 Channel-specific process replication ............................................................................ 21
1.7.3.4 Handling of Priority Input Symbols ............................................................................... 21
1.8 Network topology considerations....................................................................................................21
1.8.1 Passive bus topology............................................................................................................ 22
1.8.2 Active star topology .............................................................................................................. 22
1.8.3 Active star topology combined with a passive bus topology................................................. 24
1.9 Example node architecture.............................................................................................................25
1.9.1 Objective............................................................................................................................... 25
1.9.2 Overview............................................................................................................................... 25
1.9.3 Host - communication controller interface ............................................................................ 26
1.9.4 Communication controller - bus driver interface ................................................................... 26
1.9.5 Bus driver - host interface..................................................................................................... 27
1.9.5.1 Hard wired signals (option A) ....................................................................................... 27
1.9.5.2 Serial Peripheral Interface (SPI) (option B) .................................................................. 27
1.9.6 Bus driver - power supply interface (optional) ...................................................................... 28
1.10 Testability Requirements ..............................................................................................................28
Chapter 2
Protocol Operation Control .................................................................................... 29
2.1 Principles ........................................................................................................................................29
2.1.1 Communication controller power moding ............................................................................. 29
2.2 Description......................................................................................................................................31
2.2.1 Operational overview............................................................................................................ 32
2.2.1.1 Host commands............................................................................................................ 33
2.2.1.2 Error conditions ............................................................................................................ 33
2.2.1.2.1 Errors causing immediate entry to the POC:halt state ..........................................33
2.2.1.2.2 Errors handled by the degradation model .............................................................34
2.2.1.3 POC status ................................................................................................................... 34
2.2.1.4 SDL considerations for single channel nodes .............................................................. 36
2.3 The Protocol Operation Control process ........................................................................................36
2.3.1 POC SDL utilities.................................................................................................................. 37
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FlexRay Protocol Specification
Table of Contents
2.3.2 SDL organization .................................................................................................................. 38
2.3.3 Preempting commands......................................................................................................... 39
2.3.4 Reaching the POC:ready state............................................................................................. 40
2.3.5 Reaching the POC:normal active state ................................................................................ 41
2.3.5.1 Wakeup and startup support ........................................................................................ 43
2.3.6 Behavior during normal operation ........................................................................................ 45
2.3.6.1 Asynchronous commands ............................................................................................ 45
2.3.6.2 Cyclical behavior .......................................................................................................... 45
2.3.6.2.1 Cycle counter.........................................................................................................46
2.3.6.2.2 POC:normal active state........................................................................................46
2.3.6.2.3 POC:normal passive state.....................................................................................47
2.3.6.2.4 Error checking during normal operation ................................................................49
2.3.6.2.4.1 Error checking overview ................................................................................50
2.3.6.2.4.2 Error checking details for the POC:normal active state.................................50
2.3.6.2.4.3 Error checking details for the POC:normal passive state ..............................51
Chapter 3
Coding and Decoding ............................................................................................. 54
3.1 Principles ........................................................................................................................................54
3.2 Description......................................................................................................................................54
3.2.1 Frame and symbol encoding ................................................................................................ 55
3.2.1.1 Frame encoding............................................................................................................ 56
3.2.1.1.1 Transmission start sequence.................................................................................56
3.2.1.1.2 Frame start sequence............................................................................................56
3.2.1.1.3 Byte start sequence...............................................................................................56
3.2.1.1.4 Frame end sequence.............................................................................................56
3.2.1.1.5 Dynamic trailing sequence ....................................................................................56
3.2.1.1.6 Frame bit stream assembly ...................................................................................57
3.2.1.2 Symbol encoding .......................................................................................................... 58
3.2.1.2.1 Collision avoidance symbol and media access test symbol ..................................58
3.2.1.2.2 Wakeup symbol .....................................................................................................59
3.2.2 Sampling and majority voting ............................................................................................... 61
3.2.3 Bit clock alignment and bit strobing ...................................................................................... 61
3.2.4 Channel idle detection .......................................................................................................... 63
3.2.5 Action point and time reference point ................................................................................... 63
3.2.6 Frame and symbol decoding ................................................................................................ 65
3.2.6.1 Frame decoding............................................................................................................ 66
3.2.6.2 Symbol decoding .......................................................................................................... 67
3.2.6.2.1 Collision avoidance symbol and media access test symbol decoding ..................67
3.2.6.2.2 Wakeup symbol decoding .....................................................................................67
3.2.6.3 Decoding error.............................................................................................................. 68
3.2.7 Signal integrity ...................................................................................................................... 68
3.3 Coding and decoding process ........................................................................................................69
3.3.1 Operating modes .................................................................................................................. 69
3.3.2 Coding and decoding process behavior ............................................................................... 69
3.3.3 Encoding behavior................................................................................................................ 71
3.3.4 Encoding macros.................................................................................................................. 73
3.3.5 Decoding behavior................................................................................................................ 77
3.3.6 Decoding macros.................................................................................................................. 78
3.4 Bit strobing process ........................................................................................................................85
3.4.1 Operating modes .................................................................................................................. 85
3.4.2 Bit strobing process behavior ............................................................................................... 86
3.5 Wakeup pattern decoding process .................................................................................................87
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FlexRay Protocol Specification
Table of Contents
3.5.1 Operating modes .................................................................................................................. 87
3.5.2 Wakeup decoding process behavior .................................................................................... 88
3.5.3 Wakeup decoding macros .................................................................................................... 89
Chapter 4
Frame Format........................................................................................................... 90
4.1 Overview.........................................................................................................................................90
4.2 FlexRay header segment (5 bytes) ................................................................................................90
4.2.1 Reserved bit (1 bit) ............................................................................................................... 90
4.2.2 Payload preamble indicator (1 bit)........................................................................................ 91
4.2.3 Null frame indicator (1 bit) .................................................................................................... 91
4.2.4 Sync frame indicator (1 bit)................................................................................................... 91
4.2.5 Startup frame indicator (1 bit) ............................................................................................... 92
4.2.6 Frame ID (11 bits)................................................................................................................. 92
4.2.7 Payload length (7 bits).......................................................................................................... 93
4.2.8 Header CRC (11 bits) ........................................................................................................... 93
4.2.9 Cycle count (6 bits)............................................................................................................... 94
4.2.10 Formal header definition..................................................................................................... 94
4.3 FlexRay payload segment (0 - 254 bytes)......................................................................................94
4.3.1 NMVector (optional).............................................................................................................. 95
4.3.2 Message ID (optional, 16 bits).............................................................................................. 96
4.4 FlexRay trailer segment..................................................................................................................96
4.5 CRC calculation details ..................................................................................................................97
4.5.1 CRC calculation algorithm .................................................................................................... 97
4.5.2 Header CRC calculation ....................................................................................................... 98
4.5.3 Frame CRC calculation ........................................................................................................ 98
Chapter 5
Media Access Control ........................................................................................... 100
5.1 Principles ......................................................................................................................................100
5.1.1 Communication cycle ......................................................................................................... 100
5.1.2 Communication cycle execution ......................................................................................... 101
5.1.3 Static segment.................................................................................................................... 102
5.1.3.1 Structure of the static segment................................................................................... 102
5.1.3.2 Execution and timing of the static segment ................................................................ 102
5.1.4 Dynamic segment............................................................................................................... 103
5.1.4.1 Structure of the dynamic segment.............................................................................. 103
5.1.4.2 Execution and timing of the dynamic segment ........................................................... 103
5.1.5 Symbol window................................................................................................................... 106
5.1.6 Network idle time ................................................................................................................ 107
5.2 Description....................................................................................................................................107
5.2.1 Operating modes ................................................................................................................ 108
5.2.2 Significant events ............................................................................................................... 109
5.2.2.1 Reception-related events............................................................................................ 109
5.2.2.2 Transmission-related events ...................................................................................... 109
5.2.2.3 Timing-related events ................................................................................................. 110
5.3 Media access control process ......................................................................................................110
5.3.1 Initialization and state MAC:standby .................................................................................. 110
5.3.2 Static segment related states ............................................................................................. 112
5.3.2.1 State machine for the static segment media access control ...................................... 112
5.3.2.2 Transmission conditions and frame assembly in the static segment.......................... 114
5.3.3 Dynamic segment related states ........................................................................................ 116
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FlexRay Protocol Specification
Table of Contents
5.3.3.1 State machine for the dynamic segment media access control ................................. 116
5.3.3.2 Transmission conditions and frame assembly in the dynamic segment..................... 120
5.3.4 Symbol window related states ............................................................................................ 121
5.3.4.1 State machine for the symbol window media access control ..................................... 121
5.3.4.2 Transmission condition in the symbol window............................................................ 122
5.3.5 Network idle time ................................................................................................................ 122
Chapter 6
Frame and Symbol Processing ............................................................................ 124
6.1 Principles ......................................................................................................................................124
6.2 Description....................................................................................................................................124
6.2.1 Operating modes ................................................................................................................ 125
6.2.2 Significant events ............................................................................................................... 126
6.2.2.1 Reception-related events............................................................................................ 126
6.2.2.2 Decoding-related events............................................................................................. 127
6.2.2.3 Timing-related events ................................................................................................. 127
6.2.3 Status data ......................................................................................................................... 128
6.3 Frame and symbol processing process........................................................................................130
6.3.1 Initialization and state FSP:standby ................................................................................... 131
6.3.2 Macro SLOT_SEGMENT_END_A ..................................................................................... 132
6.3.3 State FSP:wait for CE start................................................................................................. 133
6.3.4 State FSP:decoding in progress......................................................................................... 134
6.3.4.1 Frame reception checks during non-TDMA operation................................................ 136
6.3.4.2 Frame reception checks during TDMA operation ....................................................... 137
6.3.4.2.1 Frame reception checks in the static segment ....................................................137
6.3.4.2.2 Frame reception checks in the dynamic segment ...............................................138
6.3.5 State FSP:wait for CHIRP .................................................................................................. 139
6.3.6 State FSP:wait for transmission end .................................................................................. 140
Chapter 7
Wakeup and Startup.............................................................................................. 142
7.1 Cluster wakeup.............................................................................................................................142
7.1.1 Principles ............................................................................................................................ 142
7.1.2 Description.......................................................................................................................... 143
7.1.3 Wakeup support by the communication controller.............................................................. 144
7.1.3.1 Wakeup state diagram................................................................................................ 144
7.1.3.2 The POC:wakeup listen state ..................................................................................... 146
7.1.3.3 The POC:wakeup send state...................................................................................... 147
7.1.3.4 The POC:wakeup detect state.................................................................................... 148
7.1.4 Wakeup application notes .................................................................................................. 148
7.1.4.1 Wakeup initiation by the host...................................................................................... 148
7.1.4.1.1 Single-channel nodes ..........................................................................................149
7.1.4.1.2 Dual-channel nodes.............................................................................................149
7.1.4.1.2.1 Wakeup pattern reception by the bus driver................................................150
7.1.4.1.2.2 Wakeup pattern reception by the communication controller........................151
7.1.4.2 Host reactions to status flags signaled by the communication controller ................... 151
7.1.4.2.1 Frame header reception without coding violation ................................................151
7.1.4.2.2 Wakeup pattern reception ...................................................................................152
7.1.4.2.3 Wakeup pattern transmission ..............................................................................152
7.1.4.2.4 Termination due to unsuccessful wakeup pattern transmission ..........................152
7.1.4.3 Retransmission of wakeup patterns ........................................................................... 152
7.1.4.4 Transition to startup.................................................................................................... 152
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FlexRay Protocol Specification
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7.2 Communication startup and reintegration.....................................................................................153
7.2.1 Principles ............................................................................................................................ 153
7.2.1.1 Definition and properties............................................................................................. 153
7.2.1.2 Principle of operation.................................................................................................. 153
7.2.1.2.1 Startup performed by the coldstart nodes ...........................................................153
7.2.1.2.2 Integration of the non-coldstart nodes .................................................................154
7.2.2 Description.......................................................................................................................... 154
7.2.3 Coldstart inhibit mode......................................................................................................... 155
7.2.4 Startup state diagram ......................................................................................................... 155
7.2.4.1 Path of the node initiating the coldstart (leading coldstart node)................................ 157
7.2.4.2 Path of the integrating coldstart nodes (following coldstart nodes) ............................ 157
7.2.4.3 Path of a non-coldstart node ...................................................................................... 157
7.2.4.4 The POC:coldstart listen state.................................................................................... 159
7.2.4.5 The POC:coldstart collision resolution state............................................................... 160
7.2.4.6 The POC:coldstart consistency check state ............................................................... 161
7.2.4.7 The POC:coldstart gap state ...................................................................................... 162
7.2.4.8 The POC:initialize schedule state............................................................................... 163
7.2.4.9 The POC:integration coldstart check state ................................................................. 164
7.2.4.10 The POC:coldstart join state..................................................................................... 165
7.2.4.11 The POC:integration listen state............................................................................... 166
7.2.4.12 The POC:integration consistency check state.......................................................... 167
Chapter 8
Clock Synchronization.......................................................................................... 169
8.1 Introduction...................................................................................................................................169
8.2 Time representation......................................................................................................................170
8.2.1 Timing hierarchy ................................................................................................................. 170
8.2.2 Global and local time .......................................................................................................... 171
8.2.3 Parameters and variables................................................................................................... 171
8.3 Synchronization process ..............................................................................................................172
8.4 Startup of the clock.......................................................................................................................175
8.4.1 Cold start startup ................................................................................................................ 177
8.4.2 Integration startup............................................................................................................... 177
8.5 Time measurement.......................................................................................................................180
8.5.1 Data structure ..................................................................................................................... 181
8.5.2 Initialization......................................................................................................................... 182
8.5.3 Time measurement storage................................................................................................ 183
8.6 Correction term calculation...........................................................................................................184
8.6.1 Fault-tolerant midpoint algorithm ........................................................................................ 184
8.6.2 Calculation of the offset correction value............................................................................ 185
8.6.3 Calculation of the rate correction value .............................................................................. 187
8.6.4 Value limitations ................................................................................................................. 189
8.6.5 External clock synchronization ........................................................................................... 190
8.7 Clock correction............................................................................................................................190
8.8 Sync frame configuration rules .....................................................................................................193
Chapter 9
Controller Host Interface ...................................................................................... 194
9.1 Principles ......................................................................................................................................194
9.2 Description....................................................................................................................................194
9.3 Interfaces......................................................................................................................................195
9.3.1 Protocol data interface........................................................................................................ 195
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9.3.1.1 Protocol configuration data......................................................................................... 195
9.3.1.1.1 Communication cycle timing-related protocol configuration data ........................195
9.3.1.1.2 Protocol operation-related protocol configuration data........................................196
9.3.1.1.3 Frame-related protocol configuration data...........................................................197
9.3.1.1.4 Symbol-related protocol configuration data .........................................................197
9.3.1.2 Protocol control data................................................................................................... 198
9.3.1.2.1 Control of the protocol operation control .............................................................198
9.3.1.2.2 Control of MTS transmission ...............................................................................198
9.3.1.2.3 Control of external clock synchronization ............................................................198
9.3.1.3 Protocol status data.................................................................................................... 198
9.3.1.3.1 Protocol operation control-related status data.....................................................198
9.3.1.3.2 Startup-related status data ..................................................................................199
9.3.1.3.3 Time-related status data......................................................................................199
9.3.1.3.4 Synchronization frame-related status data ..........................................................199
9.3.1.3.5 Symbol window-related status data.....................................................................200
9.3.1.3.6 NIT-related status data ........................................................................................201
9.3.1.3.7 Aggregated channel status-related status data ...................................................201
9.3.1.3.8 Wakeup-related status data.................................................................................202
9.3.1.3.9 Dynamic segment-related status data .................................................................202
9.3.2 Message data interface ...................................................................................................... 202
9.3.2.1 Message transmission................................................................................................ 202
9.3.2.1.1 Transmission slot assignment .............................................................................202
9.3.2.1.2 Transmit buffer assignment .................................................................................203
9.3.2.1.3 Transmit buffer identification for message retrieval.............................................204
9.3.2.1.4 Transmit buffer-related status data......................................................................204
9.3.2.2 Message reception ..................................................................................................... 205
9.3.2.2.1 Reception slot subscription and receive buffer assignment ................................205
9.3.2.2.2 Receive buffer contents.......................................................................................206
9.3.2.2.2.1 Slot status-related data................................................................................206
9.3.2.2.2.2 Frame contents-related data .......................................................................207
9.3.3 CHI Services....................................................................................................................... 208
9.3.3.1 Macrotick timer service............................................................................................... 208
9.3.3.1.1 Absolute timers....................................................................................................208
9.3.3.1.2 Relative timers.....................................................................................................208
9.3.3.2 Interrupt service.......................................................................................................... 208
9.3.3.3 Message ID filtering service ....................................................................................... 209
9.3.3.4 Network management service .................................................................................... 209
Appendix A
System Parameters ............................................................................................... 210
A.1 Protocol constants........................................................................................................................210
A.1.1 cdCASRxLowMin ................................................................................................................211
A.2 Physical layer constants...............................................................................................................212
A.2.1 cdTxMax..............................................................................................................................212
A.3 Performance Constants ...............................................................................................................213
Appendix B
Configuration Constraints .................................................................................... 214
B.1 General ........................................................................................................................................214
B.2 Global cluster parameters ............................................................................................................214
B.2.1 Protocol relevant .................................................................................................................214
B.2.2 Protocol related ...................................................................................................................216
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