CHAPTER 1: ABOUT THIS MANUAL
1.1. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 2: INSTRUCTION SET REFERENCE
1.2. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 1: BASIC ARCHITECTURE
1.3. OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE DEVELOPER’S MANUAL, VOLUME 3: SYSTEM PROGRAMMING GUIDE
1.4. NOTATIONAL CONVENTIONS
1.4.1. Bit and Byte Order
1.4.2. Reserved Bits and Software Compatibility
1.4.3. Instruction Operands
1.4.4. Hexadecimal and Binary Numbers
1.4.5. Segmented Addressing
1.4.6. Exceptions
1.5. RELATED LITERATURE
CHAPTER 2: INSTRUCTION FORMAT
2.1. GENERAL INSTRUCTION FORMAT
2.2. INSTRUCTION PREFIXES
2.3. OPCODE
2.4. MODR/M AND SIB BYTES
2.5. DISPLACEMENT AND IMMEDIATE BYTES
2.6. ADDRESSING-MODE ENCODING OF MODR/M AND SIB BYTES
CHAPTER 3: INSTRUCTION SET REFERENCE
3.1. INTERPRETING THE INSTRUCTION REFERENCE PAGES
3.1.1. Instruction Format
3.1.1.1. OPCODE COLUMN
3.1.1.2. INSTRUCTION COLUMN
3.1.1.3. DESCRIPTION COLUMN
3.1.1.4. DESCRIPTION
3.1.2. Operation
3.1.3. Flags Affected
3.1.4. FPU Flags Affected
3.1.5. Protected Mode Exceptions
3.1.6. Real-Address Mode Exceptions
3.1.7. Virtual-8086 Mode Exceptions
3.1.8. Floating-Point Exceptions
3.2. INSTRUCTION REFERENCE
APPENDIX A: OPCODE MAP
A.1. KEY TO ABBREVIATIONS
A.1.1. Codes for Addressing Method
A.1.2. Codes for Operand Type
A.1.3. Register Codes
A.2. ONE-BYTE OPCODE INTEGER INSTRUCTIONS
A.3. TWO-BYTE OPCODE INTEGER INSTRUCTIONS
A.4. OPCODE EXTENSIONS FOR ONE- AND TWO-BYTE OPCODES
A.5. ESCAPE OPCODE INSTRUCTIONS
A.5.1. Escape Opcodes with D8 as First Byte
A.5.2. Escape Opcodes with D9 as First Byte
A.5.3. Escape Opcodes with DA as First Byte
A.5.4. Escape Opcodes with DB as First Byte
A.5.5. Escape Opcodes with DC as First Byte
A.5.6. Escape Opcodes with DD as First Byte
A.5.7. Escape Opcodes with DE as First Byte
A.5.8. Escape Opcodes with DF As First Byte
APPENDIX B: INSTRUCTION FORMATS AND ENCODINGS
B.1. MACHINE INSTRUCTION FORMAT
B.1.1. Reg Field (reg)
B.1.2. Encoding of Operand Size Bit (w)
B.1.3. Sign Extend (s) Bit
B.1.4. Segment Register Field (sreg)
B.1.5. Special-Purpose Register (eee) Field
B.1.6. Condition Test Field (tttn)
B.1.7. Direction (d) Bit
B.2. INTEGER INSTRUCTION FORMATS AND ENCODINGS
B.3. MMX™ INSTRUCTION FORMATS AND ENCODINGS
B.3.1. Granularity Field (gg)
B.3.2. MMX™ and General-Purpose Register Fields (mmxreg and reg)
B.3.3. MMX™ Instruction Formats and Encodings Table
B.4. FLOATING-POINT INSTRUCTION FORMATS AND ENCODINGS
INDEX