LPDDR4 Standard.pdf-资料库

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JEDEC STANDARD Low Power Double Data Rate (LPDDR4) JESD209-4A (Revision of JESD209-4, August 2014) NOVEMBER 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. ©JEDEC Solid State Technology Association 2015 Published by 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved

PLEASE! DON’T VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information.

JEDEC Standard No. 209-4A Page 1 LOW POWER DOUBLE DATA RATE (LPDDR) 4 From JEDEC Board Ballot JCB-15-16, formulated under the cognizance of the JC-42.6 Subcommittee on Low Power Memories.) 1 Scope This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16x2channel SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79- 3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR4 standard.

JEDEC Standard No. 209-4A Page 2 2 Package ballout and Pin definition 2.1 Pad Order Top 41 VDD2 42 CKE_A CS_A 43 44 VSS 45 CA1_A 46 CA0_A VDD2 47 48 ODT(ca)_A VSS 49 VDD1 50 VSSQ 51 52 DQ7_A VDDQ 53 54 DQ6_A 55 VSSQ 56 DQ5_A 57 VDDQ 58 DQ4_A 59 VSSQ 60 DMI0_A 61 VDDQ 62 DQS0_c_A 63 DQS0_t_A VSSQ 64 65 DQ3_A VDDQ 66 67 DQ2_A 68 VSSQ 69 DQ1_A 70 VDDQ 71 DQ0_A VSSQ 72 VSS 73 VDD2 74 VDD1 75 VSS 76 VDD2 77 Ch. A Top VDD2 1 VSS 2 VDD1 3 VDD2 4 VSS 5 VSSQ 6 DQ8_A 7 VDDQ 8 DQ9_A 9 VSSQ 10 11 DQ10_A VDDQ 12 13 DQ11_A VSSQ 14 15 DQS1_t_A 16 DQS1_c_A VDDQ 17 18 DMI1_A VSSQ 19 20 DQ12_A VDDQ 21 22 DQ13_A VSSQ 23 24 DQ14_A VDDQ 25 26 DQ15_A VSSQ 27 ZQ 28 VDDQ 29 VDD2 30 VDD1 31 VSS 32 33 CA5_A 34 CA4_A VDD2 35 36 CA3_A 37 CA2_A NOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes. NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the extra pads are grouped with like-named pads. Ch. B Top VDD2 101 VSS 102 VDD1 103 VDD2 104 VSS 105 106 VSSQ 107 DQ8_B 108 VDDQ 109 DQ9_B 110 VSSQ 111 DQ10_B 112 VDDQ 113 DQ11_B 114 VSSQ 115 DQS1_t_B 116 DQS1_c_B 117 VDDQ 118 DMI1_B 119 VSSQ 120 DQ12_B 121 VDDQ 122 DQ13_B 123 VSSQ 124 DQ14_B 125 VDDQ 126 DQ15_B 127 VSSQ 128 RESET_n VDDQ 129 VDD2 130 VDD1 131 132 VSS 133 CA5_B 134 CA4_B 135 VDD2 136 CA3_B 137 CA2_B 141 VDD2 142 CKE_B CS_B 143 144 VSS 145 CA1_B 146 CA0_B 147 VDD2 148 ODT(ca)_B VSS 149 VDD1 150 151 VSSQ 152 DQ7_B 153 VDDQ 154 DQ6_B 155 VSSQ 156 DQ5_B 157 VDDQ 158 DQ4_B 159 VSSQ 160 DMI0_B 161 VDDQ 162 DQS0_c_B 163 DQS0_t_B 164 VSSQ 165 DQ3_B 166 VDDQ 167 DQ2_B 168 VSSQ 169 DQ1_B 170 VDDQ 171 DQ0_B VSSQ 172 173 VSS VDD2 174 VDD1 175 VSS 176 177 VDD2 BoƩom A l e n n a h C C h a n n e l B

2.2 2.2.1 Package Ballout 272-ball 15 mm x 15 mm 0.4 mm pitch, Quad-Channel POP FBGA (top view) Using Variation VFFCDB for MO-273 1 DNU VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 VSS VDD1 CA4_a VDDQ ZQ1_a VDDQ DQ15_a VDD2 DQ13_a VDD2 DMI1_a VDDQ DQS1_c_a VDDQ DQ10_a VSS DQ8_a DQ0_c VDD1 DQ2_c VDDQ DQS0_c_c VDDQ DQ4_c VDD2 DQ5_c VDD2 DQ7_c VDDQ CA0_c VDDQ CS1_c VDD1 VSS VDD2 CA3_a VSS CA5_a VSS ZQ0_a VSS DQ14_a VSS DQ12_a VSS DQS1_t_a VSS DQ11_a VSS DQ9_a VDD2 VSS DQ1_c VSS DQ3_c VSS DQS0_t_c VSS DMI0_c VSS DQ6_c VSS ODTca_c VSS CA1_c VSS CS0_c VDD2 36 DNU VSS A B C D E F G H J K L M N CA2_a CK_c_a VDD2 CK_t_a CKE0_a VSS CKE1_a CS0_a VDD2 CS1_a CA1_a VSS CA0_a ODTca_a VDDQ DQ7_a DQ6_a VSS DQ5_a DQ4_a VDDQ DMI0_a P DQS0_c_a VSS R T U V W Y AA AB DQ3_a DQS0_t_a VDDQ DQ2_a DQ1_a VSS VDD1 DQ0_a DQ0_b VDD2 DQ1_b VSS VDDQ DQ2_b DQ3_b DQS0_t_b AC DQS0_c_b VSS AD AE AF AG AH AJ AK VDDQ DMI0_b DQ5_b DQ4_b DQ6_b VSS VDDQ DQ7_b CA0_b ODTca_b CA1_b VSS VDD2 CS1_b AL CKE1_b CS0_b AM CKE0_b VSS VDD2 CK_t_b CA2_b CK_c_b AN AP AR AT VDD1 VDD2 VDDQ VSS CK_t, CK_c DMI DQ, CA, CS, CKE DNU, NC DQS_t, DQS_c RESET_n, ZQ, ODT ca NOTE 1 15 mm x 15 mm, 0.4 mm ball pitch NOTE 2 272 ball count, 36 rows NOTE 3 op View, A1 in top left corner NOTE 4 ODT ca_[x] balls are wired to ODT(ca)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if present) are disabled in the package. NOTE 5 Package Channel a and Channel c shall be assigned to die Channel A of different DRAM die. NOTE 6 Die pad VSS and VSSQ signals are combined to VSS package balls. CKE0_c CKE1_c CK_t_c VDD2 VSS CK_c_c CA2_c CA3_c CA4_c VDD2 VSS CA5_c ZQ0_c ZQ1_c DQ15_c VDDQ VSS DQ14_c DQ12_c DQ13_c DMI1_c VDDQ VSS DQS1_c_c DQS1_t_c DQ11_c DQ10_c VDDQ VSS DQ9_c DQ8_c VDD1 VDD2 DQ8_d VSS DQ9_d DQ10_d VDDQ DQS1_t_d DQ11_d VSS DQS1_c_d DMI1_d VDDQ DQ12_d DQ13_d VSS DQ14_d DQ15_d VDDQ NC NC VSS CA5_d CA4_d VDD2 CA2_d CA3_d VSS CK_c_d CK_t_d VDD2 CKE0_d CKE1_d VSS DNU VDD2 CA3_b VSS CA5_b VSS RESET_n VSS DQ14_b VSS DMI1_b VSS DQS1_t_b VSS DQ11_b VSS DQ9_b VDD2 VSS DQ1_d VSS DQ3_d VSS DQS0_t_d VSS DQ4_d VSS DQ6_d VSS ODTca_d VSS CA1_d VSS CS0_d VDD2 VSS VDD1 CA4_b VDDQ NC VDDQ DQ15_b VDD2 DQ13_b VDD2 DQ12_b VDDQ DQS1_c_b VDDQ DQ10_b VSS DQ8_b DQ0_d VDD1 DQ2_d VDDQ DQS0_c_d VDDQ DMI0_d VDD2 DQ5_d VDD2 DQ7_d VDDQ CA0_d VDDQ CS1_d VDD1 VSS VSS DNU t J E D E C S a n d a r d N o . 2 0 9 - 4 A P a g e 3

JEDEC Standard No. 209-4A Page 4 2.2.2 200-ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311 1 2 3 4 5 6 7 8 9 DNU DNU VSS VDD2 ZQ0 ZQ1 VDD2 10 VSS 11 12 DNU DNU 0.80 mm Pitch DNU DQ0_A VDDQ DQ7_A VDDQ VDDQ DQ15_A VDDQ DQ8_A DNU VSS DQ1_A DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSS VDDQ VSS DQS0_t_A VSS VDDQ VDDQ VSS DQS1_t_A VSS VDDQ VSS DQ2_A DQS0_c_A DQ5_A VSS VSS DQ13_A DQS1_c_A DQ10_A VSS VDD1 DQ3_A VDDQ DQ4_A VDD2 VDD2 DQ12_A VDDQ DQ11_A VDD1 VSS ODT_CA_ A VSS VDD1 VSS VSS VDD1 VSS ZQ2 VSS VDD2 CA0_A CS1_A CS0_A VDD2 VDD2 CA2_A CA3_A CA4_A VDD2 VSS CA1_A VSS CKE0_A CKE1_A CK_t_A CK_c_A VSS CA5_A VSS VDD2 VSS VDD2 VSS CS2_A CKE2_A VSS VDD2 VSS VDD2 VDD2 VSS VDD2 VSS CS2_B CKE2_B VSS VDD2 VSS VDD2 VSS CA1_B VSS CKE0_B CKE1_B CK_t_B CK_c_B VSS CA5_B VSS VDD2 CA0_B CS1_B CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2 VSS ODT_CA_ B VSS VDD1 VSS VSS VDD1 VSS RESET_N VSS VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1 VSS DQ2_B DQS0_c_B DQ5_B VSS VSS DQ13_B DQS1_c_B DQ10_B VSS A B C D E F G H J K L M N P R T U V h c t i P m m 5 6 . 0 W VDDQ VSS DQS0_t_B VSS VDDQ VDDQ VSS DQS1_t_B VSS VDDQ Y VSS DQ1_B DMI0_B DQ6_B VSS VSS DQ14_B DMI1_B DQ9_B VSS AA DNU DQ0_B VDDQ DQ7_B VDDQ VDDQ DQ15_B VDDQ DQ8_B DNU AB DNU DNU VSS VDD2 VSS VSS VDD2 VSS DNU DNU NOTE 1 0.8 mm pitch (X-axis), 0.65mm pitch (Y-axis), 22 rows. NOTE 2 Top View, A1 in top left corner. NOTE 3 ODT_CA_[x] balls are wired to ODT_CA)_[x] pads of Rank 0 DRAM die. ODT(ca)_[x] pads for other ranks (if present) are disabled in the package. NOTE 4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and 2-rank package those balls are NC. NOTE 5 Die pad VSS and VSSQ signals are combined to VSS package balls.

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