Vivado HLS 指导手册.pdf

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Vivado Design Suite Tutorial: High-Level Synthesis

Revision History

Tutorial Description

Overview

High-Level Synthesis Introduction

C Validation

Interface Synthesis

Arbitrary Precision Types

Design Analysis

Design Optimization

RTL Verification

Using HLS IP in IP Integrator

Using HLS IP in a Zynq Processor Design

Using HLS IP in System Generator for DSP

Software Requirements

Hardware Requirements

Locating the Tutorial Design Files

Preparing the Tutorial Design Files

High-Level Synthesis Introductory Tutorial

Overview

Lab 1

Lab 2

Lab 3

Tutorial Design Description

HLS Lab 1: Creating a High-Level Synthesis Project

Introduction

Step 1: Creating a New Project

Understanding the Graphical User Interface (GUI)

Explorer Pane

Information Pane

Auxiliary Pane

Console Pane

Toolbar Buttons

Perspectives

Step 2: Validate the C Source Code

Step 3: High-Level Synthesis

Step 4: RTL Verification

Step 5: IP Creation

HLS: Lab 2: Using the Tcl Command Interface

Introduction

Step 1: Create a Tcl file

HLS: Lab 3: Using Solutions for Design Optimization

Introduction

Step 1: Creating a New Project

Step 2: Optimize the I/O Interfaces

Step 3: Analyze the Results

Step 4: Optimize for the Highest Throughput (lowest interval)

Conclusion

C Validation

Overview

Tutorial Design Description

Lab 1: C Validation and Debug

Overview

Step 1: Create and Open the Project

Step 2: Review Test Bench and Run C Simulation

Step 3: Run the C Debugger

Lab 2: C Validation with ANSI C Arbitrary Precision Types

Introduction

Step 1: Create and Open the Project

Step 2: Run the C Debugger

Lab 3: C Validation with C++ Arbitrary Precision Types

Overview

Step 1: Create and Open the Project

Step 2: Run the C Debugger

Conclusion

Interface Synthesis

Overview

Tutorial Design Description

About the Labs

Interface Synthesis Lab 1: Block-Level I/O protocols

Overview

Step 1: Create and Open the Project

Step 2: Create and Review the Default Block-Level I/O Protocol

Step 3: Modify the Block-Level I/O protocol

Interface Synthesis Lab 2: Port I/O protocols

Overview

Step 1: Create and Open the Project

Step 2: Specify the I/O Protocol for Ports

Interface Synthesis Lab 3: Implementing Arrays as RTL Interfaces

Introduction

Step 1: Create and Open the Project

Step 2: Synthesize Array Function Arguments to RAM ports

Step 3: Using Dual-port RAM and FIFO interfaces

Step 4: Partitioned RAM and FIFO Array interfaces

Step 5: Fully Partitioned Array interfaces

Interface Synthesis Lab 4: Implementing AXI4 Interfaces

Introduction

Step 1: Create and Open the Project

Step 2: Create an Optimized Design with AXI4 Stream Interfaces

Step 3: Implementing an AXI4-Lite Interfaces

Conclusion

Arbitrary Precision Types

Overview

Tutorial Design Description

Arbitrary Precision: Lab 1

Step 1: Create and Open the Project

Step 2: Review Test Bench and Run C Simulation

Step 3: Synthesize the Design and Review Results

Arbitray Precision: Lab 2

Introduction

Step 1: Create and Simulate the Project

Step 2: Synthesize the Design and Review Results

Conclusion

Design Analysis

Overview

Lab1

Tutorial Design Description

Lab 1: Design Optimization

Step 1: Create and Open the Project

Step 2: Review the source Code and Create the Initial Design

Step 3: Review the performance using the Synthesis Report

Step 4: Review the Performance using the Analysis Perspective

Step 5: Apply Loop Pipelining & Review for Loop Optimization

Step 6: Apply Loop Optimization and Review for Bottlenecks

Step 7: Partition Block RAMs and Analyze Concurrency

Step 8: Partition Block RAMs and Apply Dataflow optimization

Step 9: Optimize the Hierarchy for Dataflow

Conclusion

Design Optimization

Overview

Tutorial Design Description

Lab 1: Optimizing a Matrix Multiplier

Step 1: Create and Open the Project

Step 2: Synthesize and Analyze the Design

Step 3: Pipeline the Product Loop

Step 4: Pipeline the Col Loop

Step 5: Reshape the Arrays

Step 6: Apply FIFO Interfaces

Step 7: Pipeline the Function

Lab 2: C Code Optimized for I/O Accesses

Step 1: Create and Open the Project

Conclusion

RTL Verification

Overview

Lab1

Lab2

Lab3

Tutorial Design Description

Lab 1: RTL Verification and the C test bench

Step 1: Create and Open the Project

Step 2: Perform RTL Verification

Step 3: Modify the C test bench

Lab 2: Viewing Trace Files in Vivado

Step 1: Create an RTL Trace File using Xsim

Step 2: View the RTL Trace File in Vivado

Lab 3: Viewing Trace Files in ModelSim

Step 1: Create an RTL Trace File using ModelSim

Step 2: View the RTL Trace File in ModelSim

Conclusion

Using HLS IP in IP Integrator

Overview

Lab1

Tutorial Design Description

Lab 1: Integrate HLS IP with a Xilinx IP Block

Step 1: Create Vivado HLS IP Blocks

Step 2: Create a Vivado Design Suite Project

Step 3: Add HLS IP to an IP Repository

Step 4: Create a Block Design for RealFFT

Step 5: Verify the Design

Conclusion

Using HLS IP in a Zynq Processor Design

Overview

Lab1

Lab2

Tutorial Design Description

Lab 1: Implement Vivado HLS IP on a Zynq Device

Step 1: Create a Vivado HLS IP Block

Step 2: Create a Vivado Zynq Project

Step 3: Add HLS IP to the IP Catalog

Step 4: Creating an IP Integrator Block Design of the System

Step 5: Implementing the System

Step 6: Developing Software and Running it on the ZYNQ System

Step 7: Modify software to communicate with HLS block

Lab 2: Streaming data between the Zynq CPU and HLS Accelerator Blocks

Step 1: Generate the HLS IP

Step 2: Create a Vivado Design Suite Project

Step 3: Add HLS IP to an IP Repository

Step 4: Create a Top-level Block Design

Step 5: Implementing the System

Step 6: Setup SDK and test the ZYNQ System

Step 7: Modify software to communicate with HLS block

Using HLS IP in System Generator for DSP

Overview

Tutorial Design Description

Lab 1: Package HLS IP for System Generator

Step 1: Create a Vivado HLS IP Block

Step 2: Open the System Generator Project

Conclusion

Vivado Design Suite Tutorial High-Level Synthesis UG871 (v 2014.1) May 6, 2014 This tutorial document has been validated for the following software versions: Vivado Design Suite 2014.1 This tutorial document has been validated for the following software versions: Vivado Design Suite 2014.1 This tutorial document has been validated for the following software versions: Vivado Design Suite 2014.1 This tutorial document has been validated for the following software versions: Vivado Design Suite 2014.1 and 2014.2. and 2014.2. and 2014.2. and 2014.2.

Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications http://www.xilinx.com/warranty.htm#critapps. ©Copyright 2012-2014 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date 05/06/2014 Version 2014.1 Rev ision New Release for Vivado Design Suite 2014.1. Send Feedback

Table of Contents Revision History ................................................................................................................. 2 Chapter 1 Tutorial Description ................................................................6 Overview ............................................................................................................................ 6 Software Requirements...................................................................................................... 7 Hardware Requirements .................................................................................................... 7 Locating the Tutorial Design Files ...................................................................................... 8 Preparing the Tutorial Design Files .................................................................................... 8 Chapter 2 High-Level Synthesis Introductory Tutorial ...........................9 Overview ............................................................................................................................ 9 Tutorial Design Description ............................................................................................... 9 HLS Lab 1: Creating a High-Level Synthesis Project .........................................................10 HLS: Lab 2: Using the Tcl Command Interface ..................................................................26 HLS: Lab 3: Using Solutions for Design Optimization .......................................................30 Chapter 3 C Validation ........................................................................... 42 Overview ...........................................................................................................................42 Tutorial Design Description ..............................................................................................42 Lab 1: C Validation and Debug..........................................................................................43 Lab 2: C Validation with ANSI C Arbitrary Precision Types...............................................51 Lab 3: C Validation with C++ Arbitrary Precision Types ...................................................56 Chapter 4 Interface Synthesis ................................................................ 61 Overview ...........................................................................................................................61 Tutorial Design Description ..............................................................................................61 Interface Synthesis Lab 1: Block-Level I/O protocols........................................................62 Interface Synthesis Lab 2: Port I/O protocols ...................................................................70 Interface Synthesis Lab 3: Implementing Arrays as RTL Interfaces ..................................75 Interface Synthesis Lab 4: Implementing AXI4 Interfaces ................................................90 Chapter 5 Arbitrary Precision Types.................................................... 100 High-Level Synthesis UG871 (v 2014.1) May 6, 2014 www.xilinx.com 3 Send Feedback

Overview ......................................................................................................................... 100 Arbitrary Precision: Lab 1 ................................................................................................ 101 Arbitray Precision: Lab 2 ................................................................................................. 106 Chapter 6 Design Analysis ................................................................... 112 Overview ......................................................................................................................... 112 Tutorial Design Description ............................................................................................ 112 Lab 1: Design Optimization ............................................................................................. 113 Chapter 7 Design Optimization ........................................................... 145 Overview ......................................................................................................................... 145 Tutorial Design Description ............................................................................................ 146 Lab 1: Optimizing a Matrix Multiplier............................................................................. 146 Lab 2: C Code Optimized for I/O Accesses ...................................................................... 165 Conclusion ....................................................................................................................... 167 Chapter 8 RTL Verification ................................................................... 168 Overview ......................................................................................................................... 168 Tutorial Design Description ............................................................................................ 168 Lab 1: RTL Verification and the C test bench .................................................................. 169 Lab 2: Viewing Trace Files in Vivado ............................................................................... 176 Lab 3: Viewing Trace Files in ModelSim .......................................................................... 180 Conclusion ....................................................................................................................... 184 Chapter 9 Using HLS IP in IP Integrator .............................................. 185 Overview ......................................................................................................................... 185 Tutorial Design Description ............................................................................................ 185 Lab 1: Integrate HLS IP with a Xilinx IP Block ................................................................. 186 Conclusion ....................................................................................................................... 210 Chapter 10 Using HLS IP in a Zynq Processor Design ........................ 211 Overview ......................................................................................................................... 211 Tutorial Design Description ............................................................................................ 211 Lab 1: Implement Vivado HLS IP on a Zynq Device ........................................................ 212 Lab 2: Streaming data between the Zynq CPU and HLS Accelerator Blocks................... 236 Chapter 11 Using HLS IP in System Generator for DSP ...................... 259 High-Level Synthesis UG871 (v 2014.1) May 6, 2014 www.xilinx.com 4 Send Feedback

Overview ......................................................................................................................... 259 Tutorial Design Description ............................................................................................ 259 Lab 1: Package HLS IP for System Generator .................................................................. 260 Conclusion ....................................................................................................................... 264 High-Level Synthesis UG871 (v 2014.1) May 6, 2014 www.xilinx.com 5 Send Feedback

Chapter 1 Tutorial Description Overview This Vivado® tutorial is a collection of smaller tutorials that explain and demonstrate all steps in the process of transforming C, C++ and SystemC code to an RTL implementation using High- Level Synthesis. TH: Sample Paste: Using The binding process. The tutorial shows how you create an initial RTL implementation and then you transform it into both a low-area and high- throughput implementation by using optimization directives without changing the C code. High-Level Synthesis Introduction This tutorial introduces Vivado High-Level Synthesis (HLS). You can learn the primary tasks for performing High-Level Synthesis using both the Graphical User Interface (GUI) and Tcl environments. The tutorial shows how you create an initial RTL implementation and then you transform it into both a low-area and high-throughput implementation by using optimization directives without changing the C code. C Validation This tutorial reviews the aspects of a good C test bench and demonstrates the basic operations of the Vivado High-Level Synthesis C debug environment. The tutorial also shows how to debug arbitrary precision data types. Interface Synthesis The interface synthesis tutorial reviews all aspect of creating ports for the RTL design. You can learn how to control block-level I/O port protocols and port I/O protocols, how arrays in the C function can be implemented as multiple ports and types of interface protocol (RAM, FIFO, AXI4 Stream), and how AXI4 bus interfaces are implemented. The tutorial completes with a design example in which the I/O accesses and the logic are optimized together to create an optimal implementation of the design. Arbitrary Precision Types The lab exercises in this tutorial contrast a C design written in native C types with the same design written with Vivado High-Level Synthesis arbitrary precision types, showing how the latter improves the quality of the hardware results without sacrificing accuracy. Design Analysis This tutorial uses a DCT function to explain the features of the interactive design analysis features in Vivado High-Level Synthesis. The initial design takes you through a number of High-Level Synthesis UG871 (v 2014.1) May 6, 2014 www.xilinx.com 6 Send Feedback

Tutorial Description analysis and optimization stages that highlight all the features of the analysis perspective and provide the basis for a design optimization methodology. Design Optimization Using a matrix multiplier example, this tutorial reviews two-design optimization techniques. The first lab explains how a design can be pipelined, contrasting the approach of pipelining the loops versus pipelining the functions. The tutorial shows you how to use the insights learned from analyzing to update the initial C code and create a more optimal implementation of the design. RTL Verification This tutorial shows how you can use the RTL cosimulation feature to verify automatically the RTL created by synthesis. The tutorial demonstrates the importance of the C test bench and shows you how to use the output from RTL verification to view the waveform diagrams in the Vivado and Mentor Graphics ModelSim simulators. Using HLS IP in IP Integrator This tutorial shows how RTL designs created by High-Level Synthesis are packaged as IP, added to the Vivado IP Catalog, and used inside the Vivado Design Suite. Using HLS IP in a Zynq Processor Design In addition to using an HLS IP block in a Zynq®-7000 SoC design, this tutorial shows how the C driver files created by High-Level Synthesis are incorporated into the software on the Zynq Processing System (PS). Using HLS IP in System Generator for DSP This tutorial shows how RTL designs created by High-Level Synthesis can be packaged as IP and used inside System Generator for DSP. Software Requirements This tutorial requires that the Vivado Design Suite 2014.1 release or later is installed. Hardware Requirements Xilinx recommends a minimum of 2 GB of RAM when using the Vivado tools. High-Level Synthesis UG871 (v 2014.1) May 6, 2014 www.xilinx.com 7 Send Feedback

Tutorial Description Locating the Tutorial Design Files As shown in Figure 1, designs for the tutorial exercises are available as a zipped archive on the Xilinx Website, tutorial documentation page. IMPORTANT: All the tutorial examples for Vivado High-Level Synthesis are available for download at: http://secure.xilinx.com/webreg/clickthrough.do?cid=356028&license=RefDesLicen se&filename=ug871-vivado-high-level-sythesis-tutorial.zip Figure 1: High-Level Synthesis Tutorial Design Files Preparing the Tutorial Design Files Extract the zip file contents into any write-accessible location. This tutorial assumes that you have placed the unzipped design files in the location C:\Vivado_HLS_Tutorial. IMPORTANT: If the Vivado_HLS_Tutorial directory is unzipped to a different location, or if it resides on Linux, adjust the pathnames to the location at which you have placed the Vivado_HLS_Tutorial directory. High-Level Synthesis UG871 (v 2014.1) May 6, 2014 www.xilinx.com 8 Send Feedback

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