The Verilog Hardware Description Language, 5th Edition.pdf

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Cover

Contents

Preface

1Verilog A Tutorial Introduction

2 Logic Synthesis

3 Behavioral Modeling

4 Concurrent Processes

5 Module Hierarchy

6 Logic Level Modeling

7 Cycle-Accurate Specification

8 Advanced Timing

9User-Defined Primitives

10 Switch Level Modeling

11 Projects

A Tutorial Questions and Discussion

B Lexical Conventions

C Verilog Operators

DVerilog Gate Types

E Registers, Memories, Integers, and Time

F System Tasks and Functions

Index

The Verilog® Hardware Description Language, Fifth Edition

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The Verilog® Hardware Description Language, Fifth Edition Donald E. Thomas ECE Department Carnegie Mellon University Pittsburgh, PA Philip R. Moorby Co-design Automation, Inc. www.co-design.com Verilog® is a registered trade mark of Cadence Design Systems, Inc.

eBook ISBN: 0-306-47666-5 1-4020-7089-6 Print ISBN: ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©2002 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com

To Sandie, and John and Holland, and Jill.

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Preface From the Old to the New Acknowledgments 1 Verilog – A Tutorial Introduction Getting Started A Structural Description Simulating the binaryToESeg Driver Creating Ports For the Module Creating a Testbench For a Module Behavioral Modeling of Combinational Circuits Procedural Models Rules for Synthesizing Combinational Circuits Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines Rules for Synthesizing Sequential Systems Non-Blocking Assignment ("<=") Module Hierarchy The Counter A Clock for the System Tying the Whole Circuit Together Tying Behavioral and Structural Models Together Summary Exercises 2 Logic Synthesis Overview of Synthesis Register-Transfer Level Systems Disclaimer Combinational Logic Using Gates and Continuous Assign Procedural Statements to Specify Combinational Logic The Basics xv xvii xxi 1 2 2 4 7 8 11 12 13 14 15 18 19 21 21 21 22 25 27 28 35 35 35 36 37 40 40

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