Allwinner_V3s_Datasheet_V1.0.pdf

发布时间：2022-06-02 发布人：admin 分类：说明书资料大小：5.00M 资料格式：pdf 举报版权申诉

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Declaration

Revision History

Table of Contents

Chapter 1 About This Documentation

1.1. Documentation Overview

1.2. Acronyms and abbreviations

Chapter 2 Overview

2.1. Processor Features

2.1.1. CPU Architecture

2.1.2. Memory Subsystem

2.1.2.1. Boot ROM

2.1.2.2. SDRAM

2.1.2.3. SD/MMC Interface

2.1.3. System Peripheral

2.1.3.1. Timer

2.1.3.2. High Speed Timer

2.1.3.3. GIC

2.1.3.4. DMA

2.1.3.5. CCU

2.1.3.6. PWM

2.1.3.7. RTC

2.1.3.8. LRADC

2.1.3.9. Crypto Engine

2.1.4. Display Subsystem

2.1.4.1. Display Engine2.0

2.1.4.2. Display Output

2.1.5. Video Engine

2.1.5.1. Video Decoding

2.1.5.2. Video Encoding

2.1.6. Image Subsystem

2.1.6.1. Image Input

2.1.6.2. ISP

2.1.7. Audio Subsystem

2.1.7.1. Audio codec

2.1.8. External Peripherals

2.1.8.1. USB

2.1.8.2. Ethernet

2.1.8.3. UART

2.1.8.4. SPI

2.1.8.5. TWI

2.1.9. Package

2.2. System Block Diagram

Chapter 3 Pin Description

3.1. Pin Characteristics

3.2. GPIO Multiplex Functions

3.3. Detailed Pin/Signal Description

Chapter 4 System

4.1. Memory Mapping

4.2. Boot System

4.3. CCU

4.3.1. Overview

4.3.2. Functionalities Description

4.3.2.1. System Bus

4.3.2.2. Bus clock tree

4.3.3. Typical Applications

4.3.4. Register List

4.3.5. Register Description

4.3.5.1. PLL_CPU Control Register (Default Value: 0x00001000)

4.3.5.2. PLL_Audio Control Register (Default Value: 0x00035514)

4.3.5.3. PLL_VIDEO Control Register (Default Value: 0x03006207)

4.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)

4.3.5.5. PLL_DDR0 Control Register (Default Value: 0x00001000)

4.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811)

4.3.5.7. PLL_ISP Control Register (Default Value: 0x03006207)

4.3.5.8. PLL_PERIPH1 Control Register (Default Value: 0x00041811)

4.3.5.9. PLL_DDR1 Control Register (Default Value: 0x00001800)

4.3.5.10. CPU/AXI Configuration Register (Default Value: 0x00010000)

4.3.5.11. AHB1/APB1 Configuration Register (Default Value: 0x00001010)

4.3.5.12. APB2 Configuration Register (Default Value: 0x01000000)

4.3.5.13. AHB2 Configuration Register (Default Value: 0x00000000)

4.3.5.14. Bus Clock Gating Register0 (Default Value: 0x00000000)

4.3.5.15. Bus Clock Gating Register1 (Default Value: 0x00000000)

4.3.5.16. Bus Clock Gating Register2 (Default Value: 0x00000000)

4.3.5.17. Bus Clock Gating Register3 (Default Value: 0x00000000)

4.3.5.18. Bus Clock Gating Register4 (Default Value: 0x00000000)

4.3.5.19. SDMMC0 Clock Register (Default Value: 0x00000000)

4.3.5.20. SDMMC1 Clock Register (Default Value: 0x00000000)

4.3.5.21. SDMMC2 Clock Register (Default Value: 0x00000000)

4.3.5.22. CE Clock Register (Default Value: 0x00000000)

4.3.5.23. SPI0 Clock Register (Default Value: 0x00000000)

4.3.5.24. USBPHY Configuration Register (Default Value: 0x00000000)

4.3.5.25. DRAM Configuration Register (Default Value: 0x00000001)

4.3.5.26. PLL_DDR1 Configuration Register (Default Value: 0x00000030)

4.3.5.27. MBUS Reset Register (Default Value: 0x80000000)

4.3.5.28. DRAM Clock Gating Register (Default Value: 0x00000000)

4.3.5.29. DE Clock Gating Register (Default Value: 0x00000000)

4.3.5.30. TCON Clock Register (Default Value: 0x00000000)

4.3.5.31. CSI0 Clock Register (Default Value: 0x00000000)

4.3.5.32. CSI1 Clock Register (Default Value: 0x00000000)

4.3.5.33. VE Clock Register (Default Value: 0x00000000)

4.3.5.34. AC Digital Clock Register (Default Value: 0x00000000)

4.3.5.35. AVS Clock Register (Default Value: 0x00000000)

4.3.5.36. MBUS Clock Register (Default Value: 0x00000000)

4.3.5.37. MIPI_CSI Register (Default Value: 0x00000000)

4.3.5.38. PLL Stable Time Register0 (Default Value: 0x000000FF)

4.3.5.39. PLL Stable Time Register1 (Default Value: 0x000000FF)

4.3.5.40. PLL_CPUX Bias Register (Default Value: 0x08100200)

4.3.5.41. PLL_AUDIO Bias Register (Default Value: 0x10100000)

4.3.5.42. PLL_VIDEO Bias Register (Default Value: 0x10100000)

4.3.5.43. PLL_VE Bias Register (Default Value: 0x10100000)

4.3.5.44. PLL_DDR0 Bias Register (Default Value: 0x81104000)

4.3.5.45. PLL_PERIPH0 Bias Register (Default Value: 0x10100010)

4.3.5.46. PLL_ISP Bias Register (Default Value: 0x10100000)

4.3.5.47. PLL_PERIPH1 Bias Register (Default Value: 0x10100010)

4.3.5.48. PLL_DDR1 Bias Register (Default Value: 0x10010000)

4.3.5.49. PLL_CPU Tuning Register (Default Value: 0x0A101000)

4.3.5.50. PLL_DDR0 Tuning Register (Default Value: 0x14880000)

4.3.5.51. PLL_CPU Pattern Control Register (Default Value: 0x00000000)

4.3.5.52. PLL_AUDIO Pattern Control Register(Default Value: 0x00000000)

4.3.5.53. PLL_VIDEO Pattern Control Register (Default Value: 0x00000000)

4.3.5.54. PLL_VE Pattern Control Register (Default Value: 0x00000000)

4.3.5.55. PLL_DDR0 Pattern Control Register (Default Value: 0x00000000)

4.3.5.56. PLL_ISP Pattern Control Register (Default Value: 0x00000000)

4.3.5.57. PLL_PERIPH1 Pattern Control Register (Default Value: 0x00000000)

4.3.5.58. PLL_DDR1 Pattern Control Register (Default Value: 0x00000000)

4.3.5.59. PLL_DDR1 Pattern Control Register1 (Default Value: 0x00000000)

4.3.5.60. Bus Software Reset Register 0 (Default Value: 0x00000000)

4.3.5.61. Bus Software Reset Register 1 (Default Value: 0x00000000)

4.3.5.62. Bus Software Reset Register 2 (Default Value: 0x00000000)

4.3.5.63. Bus Software Reset Register 3 (Default Value: 0x00000000)

4.3.5.64. Bus Software Reset Register 4 (Default Value: 0x00000000)

4.3.5.65. PS Control Register (Default Value: 0x00000000)

4.3.5.66. PS Counter Register (Default Value: 0x00000000)

4.3.6. Programming Guidelines

4.3.6.1. PLL

4.3.6.2. BUS

4.3.6.3. Clock Switch

4.3.6.4. Gating and reset

4.4. System Control

4.4.1. Overview

4.4.2. System Control Register List

4.4.3. System Control Register Description

4.4.3.1. Version Register (Default Value: 0x00000000)

4.4.3.2. EMAC-EPHY Clock Register (Default Value: 0x00058000)

4.5. Timer

4.5.1. Overview

4.5.2. Block Diagram

4.5.3. Timer Register List

4.5.4. Timer Register Description

4.5.4.1. Timer IRQ Enable Register (Default Value: 0x00000000)

4.5.4.2. Timer IRQ Status Register (Default Value: 0x00000000)

4.5.4.3. Timer 0 Control Register (Default Value: 0x00000004)

4.5.4.4. Timer 0 Interval Value Register

4.5.4.5. Timer 0 Current Value Register

4.5.4.6. Timer 1 Control Register (Default Value: 0x00000004)

4.5.4.7. Timer 1 Interval Value Register

4.5.4.8. Timer 1 Current Value Register

4.5.4.9. Timer 2 Control Register

4.5.4.10. Timer 2 Interval Value Register

4.5.4.11. Timer 2 Current Value Register

4.5.4.12. AVS Counter Control Register (Default Value: 0x00000000)

4.5.4.13. AVS Counter 0 Register (Default Value: 0x00000000)

4.5.4.14. AVS Counter 1 Register (Default Value: 0x00000000)

4.5.4.15. AVS Counter Divisor Register (Default Value: 0x05DB05DB)

4.5.4.16. Watchdog IRQ Enable Register (Default Value: 0x00000000)

4.5.4.17. Watchdog Status Register (Default Value: 0x00000000)

4.5.4.18. Watchdog Control Register (Default Value: 0x00000000)

4.5.4.19. Watchdog Configuration Register (Default Value: 0x00000001)

4.5.4.20. Watchdog Mode Register (Default Value: 0x00000000)

4.5.4.21. 64-bit Counter Control Register (Default Value: 0x00000000)

4.5.4.22. 64-bit Counter Low Register (Default Value: 0x00000000)

4.5.4.23. 64-bit Counter High Register (Default Value: 0x00000000)

4.6. High-speed Timer

4.6.1. Overview

4.6.2. Operation Principle

4.6.2.1. HSTimer clock gating and software reset

4.6.2.2. HSTimer reload bit

4.6.3. HSTimer Register List

4.6.4. HSTimer Register Description

4.6.4.1. HS Timer IRQ Enable Register (Default Value: 0x00000000)

4.6.4.2. HS Timer IRQ Status Register (Default Value: 0x00000000)

4.6.4.3. HS Timer0 Control Register (Default Value: 0x00000000)

4.6.4.4. HS Timer0 Interval Value Lo Register

4.6.4.5. HS Timer0 Interval Value Hi Register

4.6.4.6. HS Timer0 Current Value Lo Register

4.6.4.7. HS Timer0 Current Value Hi Register

4.6.4.8. HS Timer1 Control Register (Default Value: 0x00000000)

4.6.4.9. HS Timer1 Interval Value Lo Register

4.6.4.10. HS Timer1 Interval Value Hi Register

4.6.4.11. HS Timer1 Current Value Lo Register

4.6.4.12. HS Timer1 Current Value Hi Register

4.6.5. Programming Guidelines

4.7. PWM

4.7.1. Overview

4.7.2. Functionalities Description

4.7.3. PWM Register List

4.7.4. PWM Register Description

4.7.4.1. PWM Control Register(Default Value: 0x00000000)

4.7.4.2. PWM Channel 0 Period Register

4.7.4.3. PWM Channel 1 Period Register

4.8. DMA

4.8.1. Overview

4.8.2. Functionalities Description

4.8.2.1. Block Diagram

4.8.2.2. DRQ Type and Corresponding Relation

4.8.2.3. DMA Descriptor

4.8.3. DMA Register List

4.8.4. DMA Register Description

4.8.4.1. DMA IRQ Enable Register0 (Default Value: 0x00000000)

4.8.4.2. DMA IRQ Pending Status Register (Default Value: 0x00000000)

4.8.4.3. DMA Auto Gating Register (Default Value: 0x00000000)

4.8.4.4. DMA Status Register (Default Value: 0x00000000)

4.8.4.5. DMA Channel Enable Register (Default Value: 0x00000000)

4.8.4.6. DMA Channel Pause Register (Default Value: 0x00000000)

4.8.4.7. DMA Channel Descriptor Address Register(Default Value: 0x00000000)

4.8.4.8. DMA Channel Configuration Register (Default Value: 0x00000000)

4.8.4.9. DMA Channel Current Source Address Register (Default Value: 0x00000000)

4.8.4.10. DMA Channel Current Destination Address Register (Default Value: 0x00000000)

4.8.4.11. DMA Channel Byte Counter Left Register (Default Value: 0x00000000)

4.8.4.12. DMA Channel Parameter Register (Default Value: 0x00000000)

4.9. GIC

4.9.1. Interrupt Source

4.10. Crypto Engine

4.10.1. Overview

4.10.2. Block Diagram

4.10.3. Crypto Engine Register List

4.10.4. Crypto Engine Register Description

4.10.4.1. Control Register(Default Value: 0x00000000)

4.10.4.2. Key [n] Register (Default Value: 0x00000000)

4.10.4.3. IV[n] Register(Default Value: 0x00000000)

4.10.4.4. Count [n] Register (Default Value: 0x00000000)

4.10.4.5. FIFO Control/ Status Register (Default Value: 0x60000F0F)

4.10.4.6. Interrupt Control/ Status Register (Default Value: 0x00000000)

4.10.4.7. Message Digest[n] Register (Default Value: 0x00000000)

4.10.4.8. CTS Length Register (Default Value: 0x00000000)

4.10.4.9. RXFIFO Register (Default Value: 0x00000000)

4.10.4.10. TXFIFO Register (Default Value: 0x00000000)

4.10.5. Crypto Engine Clock Requirement

4.11. LRADC

4.11.1. Overview

4.11.2. Clock Source

4.11.3. Operation Principle

4.11.4. LRADC Register List

4.11.5. LRADC Register Description

4.11.5.1. LRADC Control Register (Default Value: 0x01000168)

4.11.5.2. LRADC Interrupt Control Register (Default Value: 0x00000000)

4.11.5.3. LRADC Interrupt Status Register (Default Value: 0x00000000)

4.11.5.4. LRADC Data0 Register (Default Value: 0x00000000)

4.12. RTC

4.12.1. Overview

4.12.2. RTC Register List

4.12.3. RTC Register Description

4.12.3.1. LOSC Control Register (Default Value: 0x00004000)

4.12.3.2. LOSC Auto Swith Status Register (Default Value: 0x00000000)

4.12.3.3. RTC YY-MM-DD Register (Default Value: 0x00000000)

4.12.3.4. RTC HH-MM-SS Register (Default Value: 0x00000000)

4.12.3.5. Alarm 0 Counter Register (Default Value: 0x00000000)

4.12.3.6. Alarm 0 Current Value Register (Default Value: 0x00000000)

4.12.3.7. Alarm 0 Enable Register (Default Value: 0x00000000)

4.12.3.8. Alarm 0 IRQ Enable Register (Default Value: 0x00000000)

4.12.3.9. Alarm 0 IRQ Status Register (Default Value: 0x00000000)

4.12.3.10. Alarm 1 Week HH-MM-SS Register (Default Value: 0x00000000)

4.12.3.11. Alarm 1 Enable Register (Default Value: 0x00000000)

4.12.3.12. Alarm 1 IRQ Enable Register (Default Value: 0x00000000)

4.12.3.13. Alarm 1 IRQ Status Register (Default Value: 0x00000000)

4.12.3.14. Alarm Config Register (Default Value: 0x00000000)

4.12.3.15. LOSC Output Gating Register (Default Value: 0x00000000)

4.12.3.16. LOSC Output Gating Register (Default Value: 0x00000000)

4.12.3.17. VDD RTC Regulation Register (Default Value: 0x00000004)

4.12.3.18. IC Characteristic Register (Default Value: 0x00000000)

4.13. Audio Codec

4.13.1. Overview

4.13.2. Power and Signal Description

4.13.2.1. Analog I/O Pins

4.13.2.2. Filter/Reference

4.13.2.3. Power/Ground

4.13.3. Data Path Diagram

4.13.4. Audio Codec Register List

4.13.5. Audio Codec Register Description

4.13.5.1. 0x000 DAC Digital Part Control Register(Default Value: 0x00000000)

4.13.5.2. 0x004 DAC FIFO Control Register(Default Value: 0x00000F00)

4.13.5.3. 0x008 DAC FIFO Status Register(Default Value: 0x00800088)

4.13.5.4. 0x010 ADC FIFO Control Register(Default Value: 0x00000F00)

4.13.5.5. 0x014 ADC FIFO Status Register(Default Value: 0x00000000)

4.13.5.6. 0x018 ADC RX DATA Register(Default Value: 0x00000000)

4.13.5.7. 0x020 DAC TX DATA Register(Default Value: 0x00000000)

4.13.5.8. 0x040 DAC TX Counter Register(Default Value: 0x00000000)

4.13.5.9. 0x044 ADC RX Counter Register(Default Value: 0x00000000)

4.13.5.10. 0x048 DAC Debug Register(Default Value: 0x00000000)

4.13.5.11. 0x04C ADC Debug Register(Default Value: 0x00000000)

4.13.5.12. 0x050 HMIC Control Register(Default Value: 0x00000000)

4.13.5.13. 0x054 HMIC Data Register(Default Value: 0x00000000)

4.13.5.14. 0x060 DAC DAP Control Register(Default Value: 0x00000000)

4.13.5.15. 0x070 ADC DAP Control Register(Default Value: 0x00000000)

4.13.5.16. 0x074 ADC DAP Left Control Register(Default Value: 0x001F1800)

4.13.5.17. 0x078 ADC DAP Right Control Register(Default Value: 0x001F7000)

4.13.5.18. 0x07CADC DAP Parameter Register(Default Value: 0x2C2C2828)

4.13.5.19. 0x080 ADC DAP Left Average Coef Register(Default Value: 0x00051EB8)

4.13.5.20. 0x084 ADC DAP Left Decay & Attack Time Register(Default Value: 0x0000001F)

4.13.5.21. 0x088 ADC DAP Right Average Coef Register(Default Value: 0x00051EB8)

4.13.5.22. 0x08C ADC DAP Right Decay & Attack Time Register(Default Value: 0x0000001F)

4.13.5.23. 0x090 ADC DAP HPF Coef Register(Default Value: 0x00FFFAC1)

4.13.5.24. 0x094 ADC DAP Left Input Signal Low Average Coef Register(Default Value: 0x00051EB8)

4.13.5.25. 0x098 ADC DAP Right Input Signal Low Average Coef Register(Default Value: 0x00051EB8)

4.13.5.26. 0x09C ADC DAP Optimum Register(Default Value: 0x00000000)

4.13.5.27. 0x100 DAC DRC High HPF Coef Register(Default Value: 0x000000FF)

4.13.5.28. 0x104 DAC DRC Low HPF Coef Register(Default Value: 0x0000FAC1)

4.13.5.29. 0x108 DAC DRC Control Register(Default Value: 0x00000080)

4.13.5.30. 0x10C DAC DRC Left Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

4.13.5.31. 0x110 DAC DRC Left Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

4.13.5.32. 0x114 DAC DRC Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

4.13.5.33. 0x118 DAC DRC Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

4.13.5.34. 0x11C DAC DRC Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)

4.13.5.35. 0x120 DAC DRC Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

4.13.5.36. 0x124 DAC DRC Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF)

4.13.5.37. 0x128 DAC DRC Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

4.13.5.38. 0x12C DAC DRC Left RMS Filter High Coef Register(Default Value: 0x00000001)

4.13.5.39. 0x130 DAC DRC Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)

4.13.5.40. 0x134 DAC DRC Right RMS Filter High Coef Register(Default Value: 0x00000001)

4.13.5.41. 0x138 DAC DRC Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)

4.13.5.42. 0x13C DAC DRC Compressor Theshold High Setting Register(Default Value: 0x000006A4)

4.13.5.43. 0x140 DAC DRC Compressor Slope High Setting Register(Default Value: 0x0000D3C0)

4.13.5.44. 0x144 DAC DRC Compressor Slope High Setting Register(Default Value: 0x00000080)

4.13.5.45. 0x148 DAC DRC Compressor Slope Low Setting Register(Default Value: 0x00000000)

4.13.5.46. 0x14C DAC DRC Compressor High Output at Compressor Threshold Register(Default Value: 0x0000F95B)

4.13.5.47. 0x150 DAC DRC Compressor Low Output at Compressor Threshold Register(Default Value: 0x00002C3F)

4.13.5.48. 0x154 DAC DRC Limiter Theshold High Setting Register(Default Value: 0x000001A9)

4.13.5.49. 0x158 DAC DRC Limiter Theshold Low Setting Register(Default Value: 0x000034F0)

4.13.5.50. 0x15C DAC DRC Limiter Slope High Setting Register(Default Value: 0x00000005)

4.13.5.51. 0x160 DAC DRC Limiter Slope Low Setting Register(Default Value: 0x1EB8)

4.13.5.52. 0x164 DAC DRC Limiter High Output at Limiter Threshold(Default Value: 0x0000FBD8)

4.13.5.53. 0x168 DAC DRC Limiter Low Output at Limiter Threshold(Default Value: 0x0000FBA7)

4.13.5.54. 0x16C DAC DRC Expander Theshold High Setting Register(Default Value: 0x00000BA0)

4.13.5.55. 0x170 DAC DRC Expander Theshold Low Setting Register(Default Value: 0x00007291)

4.13.5.56. 0x174 DAC DRC Expander Slope High Setting Register(Default Value: 0x00000500)

4.13.5.57. 0x178 DAC DRC Expander Slope Low Setting Register(Default Value: 0x00000000)

4.13.5.58. 0x17C DAC DRC Expander High Output at Expander Threshold(Default Value: 0xF45F)

4.13.5.59. 0x180 DAC DRC Expander Low Output at Expander Threshold(Default Value: 0x00008D6E)

4.13.5.60. 0x184 DAC DRC Linear Slope High Setting Register(Default Value: 0x00000100)

4.13.5.61. 0x188 DAC DRC Linear Slope Low Setting Register(Default Value: 0x00000000)

4.13.5.62. 0x18C DAC DRC Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002)

4.13.5.63. 0x190 DAC DRC Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600)

4.13.5.64. 0x194 DAC DRC Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000)

4.13.5.65. 0x198 DAC DRC Smooth filter Gain Low Release Time Coef Register(Default Value: 0x00000F04)

4.13.5.66. 0x19C DAC DRC MAX Gain High Setting Register(Default Value: 0x0000FE56)

4.13.5.67. 0x1A0 DAC DRC MAX Gain Low Setting Register(Default Value: 0x0000CB0F)

4.13.5.68. 0x1A4 DAC DRC MIN Gain High Setting Register(Default Value: 0x0000_F95B)

4.13.5.69. 0x1A8 DAC DRC MIN Gain Low Setting Register(Default Value: 0x00002C3F)

4.13.5.70. 0x1AC DAC DRC Expander Smooth Time High Coef Register(Default Value: 0x00000000)

4.13.5.71. 0x1B0 DAC DRC Expander Smooth Time Low Coef Register(Default Value: 0x0000640C)

4.13.5.72. 0x1B8 DAC DRC HPF Gain High Coef Register(Default Value: 0x00000100)

4.13.5.73. 0x1BC DAC DRC HPF Gain Low Coef Register(Default Value: 0x00000000)

4.13.5.74. 0x200 ADC DRC High HPF Coef Register(Default Value: 0x000000FF)

4.13.5.75. 0x204 ADC DRC Low HPF Coef Register(Default Value: 0x0000FAC1)

4.13.5.76. 0x208 ADC DRC Control Register(Default Value: 0x00000080)

4.13.5.77. 0x20C ADC DRC Left Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

4.13.5.78. 0x210 ADC DRC Left Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

4.13.5.79. 0x214 ADC DRC Right Peak Filter High Attack Time Coef Register(Default Value: 0x0000000B)

4.13.5.80. 0x218 ADC DRC Peak Filter Low Attack Time Coef Register(Default Value: 0x000077BF)

4.13.5.81. 0x21C ADC DRC Left Peak Filter High Release Time Coef Register(Default Value: 0x000000FF)

4.13.5.82. 0x220 ADC DRC Left Peak Filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

4.13.5.83. 0x224 ADC DRC Right Peak filter High Release Time Coef Register(Default Value: 0x000000FF)

4.13.5.84. 0x228 ADC DRC Right Peak filter Low Release Time Coef Register(Default Value: 0x0000E1F8)

4.13.5.85. 0x22C ADC DRC Left RMS Filter High Coef Register(Default Value: 0x00000001)

4.13.5.86. 0x230 ADC DRC Left RMS Filter Low Coef Register(Default Value: 0x00002BAF)

4.13.5.87. 0x234 ADC DRC Right RMS Filter High Coef Register(Default Value: 0x00000001)

4.13.5.88. 0x238 ADC DRC Right RMS Filter Low Coef Register(Default Value: 0x00002BAF)

4.13.5.89. 0x23C ADC DRC Compressor Theshold High Setting Register(Default Value: 0x000006A4)

4.13.5.90. 0x240 ADC DRC Compressor Slope High Setting Register(Default Value: 0x0000D3C0)

4.13.5.91. 0x244 ADC DRC Compressor Slope High Setting Register(Default Value: 0x00000080)

4.13.5.92. 0x248 ADC DRC Compressor Slope Low Setting Register(Default Value: 0x00000000)

4.13.5.93. 0x24C ADC DRC Compressor High Output at Compressor Threshold Register(Default Value: 0x0000F95B)

4.13.5.94. 0x250 ADC DRC Compressor Low Output at Compressor Threshold Register(Default Value: 0x00002C3F)

4.13.5.95. 0x254 ADC DRC Limiter Theshold High Setting Register(Default Value: 0x000001A9)

4.13.5.96. 0x258 ADC DRC Limiter Theshold Low Setting Register(Default Value: 0x000034F0)

4.13.5.97. 0x25C ADC DRC Limiter Slope High Setting Register(Default Value: 0x00000005)

4.13.5.98. 0x260 ADC DRC Limiter Slope Low Setting Register(Default Value: 0x1EB8)

4.13.5.99. 0x264 ADC DRC Limiter High Output at Limiter Threshold(Default Value: 0x0000FBD8)

4.13.5.100. 0x268 ADC DRC Limiter Low Output at Limiter Threshold(Default Value: 0x0000FBA7)

4.13.5.101. 0x26C ADC DRC Expander Theshold High Setting Register(Default Value: 0x00000BA0)

4.13.5.102. 0x270 ADC DRC Expander Theshold Low Setting Register(Default Value: 0x00007291)

4.13.5.103. 0x274 ADC DRC Expander Slope High Setting Register(Default Value: 0x00000500)

4.13.5.104. 0x278 ADC DRC Expander Slope Low Setting Register(Default Value: 0x00000000)

4.13.5.105. 0x27C ADC DRC Expander High Output at Expander Threshold(Default Value: 0xF45F)

4.13.5.106. 0x280 ADC DRC Expander Low Output at Expander Threshold(Default Value: 0x00008D6E)

4.13.5.107. 0x284 ADC DRC Linear Slope High Setting Register(Default Value: 0x00000100)

4.13.5.108. 0x288 ADC DRC Linear Slope Low Setting Register(Default Value: 0x00000000)

4.13.5.109. 0x28C ADC DRC Smooth filter Gain High Attack Time Coef Register(Default Value: 0x00000002)

4.13.5.110. 0x290 ADC DRC Smooth filter Gain Low Attack Time Coef Register(Default Value: 0x00005600)

4.13.5.111. 0x294 ADC DRC Smooth filter Gain High Release Time Coef Register(Default Value: 0x00000000)

4.13.5.112. 0x298 ADC DRC Smooth filter Gain Low Release Time Coef Register(Default Value: 0x00000F04)

4.13.5.113. 0x29C ADC DRC MAX Gain High Setting Register(Default Value: 0x0000FE56)

4.13.5.114. 0x2A0 ADC DRC MAX Gain Low Setting Register(Default Value: 0x0000CB0F)

4.13.5.115. 0x2A4 ADC DRC MIN Gain High Setting Register(Default Value: 0x0000F95B)

4.13.5.116. 0x2A8 ADC DRC MIN Gain Low Setting Register(Default Value: 0x00002C3F)

4.13.5.117. 0x2AC ADC DAP Expander Smooth Time High Coef Register(Default Value: 0x00000000)

4.13.5.118. 0x2B0 ADC DRC Expander Smooth Time Low Coef Register (Default Value: 0x0000640C)

4.13.5.119. 0x2B8 ADC DRC HPF Gain High(Default Value: 0x00000100)

4.13.5.120. 0x2BC ADC DRC HPF Gain Low(Default Value: 0x00000000)

4.13.5.121. AC Parameter Configuration Register(Default Value: 0x10000000)

4.13.5.122. 0x00 Headphone Volume Control(Default Value: 0x00)

4.13.5.123. 0x01 Left Output Mixer Source Select Control Register(Default Value: 0x00)

4.13.5.124. 0x02 Right Output Mixer Source Select Control Register(Default Value: 0x00)

4.13.5.125. 0x03 DAC Analog Enable and PA Source Control Register(Default Value: 0x00)

4.13.5.126. 0x06 MIC1 Gain Control Register(Default Value: 0x33)

4.13.5.127. 0x07 PA Enable and HP Control Register(Default Value: 0x14)

4.13.5.128. 0x0B BIAS and MIC1 boost(Default Value: 0x04)

4.13.5.129. 0x0C Left ADC Mixer Mute Control(Default Value: 0x00)

4.13.5.130. 0x0D Right ADC Mixer Mute Control(Default Value: 0x00)

4.13.5.131. 0x0E PA Anti-pop time Control(Default Value: 0x04)

4.13.5.132. 0x0F ADC Analog Control Register(Default Value: 0x03)

4.13.5.133. 0x10 OPDRV/OPCOM/OPADC Control(Default Value: 0x55)

4.13.5.134. 0x11 OPMIC、OPVR and OPADC Control(Default Value: 0x55)

4.13.5.135. 0x12 ZERO CROSS Control(Default Value: 0x42)

4.13.5.136. 0x13 ADC Function Control(Default Value: 0xD6)

4.13.5.137. 0x14 Bias & DA16 Calibration Control Register(Default Value: 0x00)

4.13.5.138. 0x15 DA16 Calibration Data(Default Value: 0x80)

4.13.5.139. 0x17 Bias Calibration Data(Default Value: 0x20)

4.13.5.140. 0x18 Bias Register Setting Data(Default Value: 0x20)

4.14. Port Controller

4.14.1. Port Controller Register List

4.14.2. Port Controller Register Description

4.14.2.1. PB Configure Register 0 (Default Value: 0x77777777)

4.14.2.2. PB Configure Register 1 (Default Value: 0x00777777)

4.14.2.3. PB Configure Register 2 (Default Value: 0x00000000)

4.14.2.4. PB Configure Register 3 (Default Value: 0x00000000)

4.14.2.5. PB Data Register (Default Value: 0x00000000)

4.14.2.6. PB Multi-Driving Register 0 (Default Value: 0x05555555)

4.14.2.7. PB Multi-Driving Register 1 (Default Value: 0x00000000)

4.14.2.8. PB PULL Register 0 (Default Value: 0x00000000)

4.14.2.9. PB PULL Register 1 (Default Value: 0x00000000)

4.14.2.10. PC Configure Register 0 (Default Value: 0x77777777)

4.14.2.11. PC Configure Register 1 (Default Value: 0x00000777)

4.14.2.12. PC Configure Register 2 (Default Value: 0x00000000)

4.14.2.13. PC Configure Register 3 (Default Value: 0x00000000)

4.14.2.14. PC Data Register (Default Value: 0x00000000)

4.14.2.15. PC Multi-Driving Register 0 (Default Value: 0x00155555)

4.14.2.16. PC Multi-Driving Register 1 (Default Value: 0x00000000)

4.14.2.17. PC PULL Register 0 (Default Value: 0x00000000)

4.14.2.18. PC PULL Register 1 (Default Value: 0x00000000)

4.14.2.19. PE Configure Register 0 (Default Value: 0x77777777)

4.14.2.20. PE Configure Register 1 (Default Value: 0x77777777)

4.14.2.21. PE Configure Register 2 (Default Value: 0x77777777)

4.14.2.22. PE Configure Register 3 (Default Value: 0x00000007)

4.14.2.23. PE Data Register (Default Value: 0x00000000)

4.14.2.24. PE Multi-Driving Register 0 (Default Value: 0x55555555)

4.14.2.25. PE Multi-Driving Register 1 (Default Value: 0x00015555)

4.14.2.26. PE PULL Register 0 (Default Value: 0x00000000)

4.14.2.27. PE PULL Register 1 (Default Value: 0x00000000)

4.14.2.28. PF Configure Register 0 (Default Value: 0x07373733)

4.14.2.29. PF Configure Register 1 (Default Value: 0x00000000)

4.14.2.30. PF Configure Register 2(Default Value: 0x00000000)

4.14.2.31. PF Configure Register 3(Default Value: 0x00000000)

4.14.2.32. PF Data Register (Default Value: 0x00000000)

4.14.2.33. PF Multi-Driving Register 0 (Default Value: 0x00001555)

4.14.2.34. PF Multi-Driving Register 1 (Default Value: 0x00000000)

4.14.2.35. PF PULL Register 0 (Default Value: 0x00000000)

4.14.2.36. PF PULL Register 1 (Default Value: 0x00000000)

4.14.2.37. PG Configure Register 0 (Default Value: 0x77777777)

4.14.2.38. PG Configure Register 1 (Default Value: 0x00777777)

4.14.2.39. PG Configure Register 2 (Default Value: 0x00000000)

4.14.2.40. PG Configure Register 3 (Default Value: 0x00000000)

4.14.2.41. PG Data Register (Default Value: 0x00000000)

4.14.2.42. PG Multi-Driving Register 0 (Default Value: 0x05555555)

4.14.2.43. PG Multi-Driving Register 1 (Default Value: 0x00000000)

4.14.2.44. PG PULL Register 0 (Default Value: 0x00000000)

4.14.2.45. PG PULL Register 1 (Default Value: 0x00000000)

4.14.2.46. PB External Interrupt Configure Register 0 (Default Value: 0x00000000)

4.14.2.47. PB External Interrupt Configure Register 1 (Default Value: 0x00000000)

4.14.2.48. PB External Interrupt Configure Register 2 (Default Value: 0x00000000)

4.14.2.49. PB External Interrupt Configure Register 3 (Default Value: 0x00000000)

4.14.2.50. PB External Interrupt Control Register (Default Value: 0x00000000)

4.14.2.51. PB External Interrupt Status Register (Default Value: 0x00000000)

4.14.2.52. PB External Interrupt Debounce Register (Default Value: 0x00000000)

4.14.2.53. PG External Interrupt Configure Register 0 (Default Value: 0x00000000)

4.14.2.54. PG External Interrupt Configure Register 1 (Default Value: 0x00000000)

4.14.2.55. PG External Interrupt Configure Register 2 (Default Value: 0x00000000)

4.14.2.56. PG External Interrupt Configure Register 3 (Default Value: 0x00000000)

4.14.2.57. PG External Interrupt Control Register (Default Value: 0x00000000)

4.14.2.58. PG External Interrupt Status Register (Default Value: 0x00000000)

4.14.2.59. PG External Interrupt Debounce Register (Default Value: 0x00000000)

Chapter 5 Memory

5.1. SD/MMC

5.1.1. Overview

5.1.2. Block Diagram

5.1.3. SD/MMC Controller Timing Diagram

5.1.4. SD/MMC Controller Special Requirement

5.1.4.1. SD/MMC Pin List

5.1.5. Internal DMA Controller Description

5.1.5.1. IDMAC Descriptor Structure

5.1.5.2. DES0 definition

5.1.5.3. DES1 definition

5.1.5.4. DES2 definition

5.1.5.5. DES3 definition

5.1.6. SD/MMC Register List

5.1.7. SD/MMC Register Description

5.1.7.1. SD Global Control Register(Default Value: 0x00000300)

5.1.7.2. SD Clock Control Register(Default Value: 0x00000000)

5.1.7.3. SD Timeout Register (Default Value: 0xFFFFFF40)

5.1.7.4. SD Bus Width Register (Default Value: 0x00000000)

5.1.7.5. SD Block Size Register (Default Value: 0x00000200)

5.1.7.6. SD Block Count Register (Default Value: 0x00000200)

5.1.7.7. SD Command Register (Default Value: 0x00000000)

5.1.7.8. SD Command Argument Register (Default Value: 0x00000000)

5.1.7.9. SD Response 0 Register (Default Value: 0x00000000)

5.1.7.10. SD Response 1 Register (Default Value: 0x00000000)

5.1.7.11. SD Response 2 Register (Default Value: 0x00000000)

5.1.7.12. SD Response 3 Register (Default Value: 0x00000000)

5.1.7.13. SD Interrupt Mask Register (Default Value: 0x00000000)

5.1.7.14. SD Masked Interrupt Status Register (Default Value: 0x00000000)

5.1.7.15. SD Raw Interrupt Status Register (Default Value: 0x00000000)

5.1.7.16. SD Status Register (Default Value: 0x00000006)

5.1.7.17. SD FIFO Water Level Register (Default Value: 0x000F0000)

5.1.7.18. SD Function Select Register (Default Value: 0x00000000)

5.1.7.19. SD Auto Command 12 Register (Default Value: 0x0000ffff)

5.1.7.20. SD NewTiming Set Register (Default Value: 0x00000001,only used in SDC2)

5.1.7.21. SD Hardware Reset Register (Default Value: 0x00000001)

5.1.7.22. SD DMAC Control Register (Default Value: 0x00000000)

5.1.7.23. SD Descriptor List Base Address Register (Default Value: 0x00000000)

5.1.7.24. SD DMAC Status Register (Default Value: 0x0000_0000)

5.1.7.25. SD DMAC Interrupt Enable Register (Default Value: 0x00000000)

5.1.7.26. Card Threshold Control Register (Default Value: 0x00000000)

5.1.7.27. eMMC4.41 DDR Start Bit Detection Control Register (Default Value: 0x00000000)

5.1.7.28. SD Response CRC Register (Default Value: 0x00000000)

5.1.7.29. SD Data7 CRC Register (Default Value: 0x00000000)

5.1.7.30. SD Data6 CRC Register (Default Value: 0x00000000)

5.1.7.31. SD Data5 CRC Register (Default Value: 0x00000000)

5.1.7.32. SD Data4 CRC Register (Default Value: 0x00000000)

5.1.7.33. SD Data3 CRC Register (Default Value: 0x00000000)

5.1.7.34. SD Data2 CRC Register (Default Value: 0x00000000)

5.1.7.35. SD Data1 CRC Register (Default Value: 0x00000000)

5.1.7.36. SD Data0 CRC Register (Default Value: 0x00000000)

5.1.7.37. SD CRC Status Register (Default Value: 0x00000000)

5.1.7.38. SD FIFO Register (Default Value: 0x00000000)

Chapter 6 Image

6.1. CSI

6.1.1. Overview

6.1.2. Functionalities Description

6.1.2.1. Block Diagram

6.1.2.2. CSI FIFO Distribution

6.1.2.3. Pin Mapping

6.1.2.4. Timing

6.1.2.5. Bit Definition

6.1.3. CSI Register list

6.1.4. CSI Register Description

6.1.4.1. CSI Enable Register (Default Value: 0x00000000)

6.1.4.2. CSI Interface Configuration Register (Default Value: 0x00000000)

6.1.4.3. CSI Capture Register (Default Value: 0x00000000)

6.1.4.4. CSI Synchronization Counter Register (Default Value: 0x00000000)

6.1.4.5. CSI FIFO Threshold Register (Default Value: 0x040f0400)

6.1.4.6. CSI BT656 Header Configuration Register (Default Value: 0x03020100)

6.1.4.7. CSI Pattern Generation Length Register (Default Value: 0x00000000)

6.1.4.8. CSI Pattern Generation Address Register (Default Value: 0x00000000)

6.1.4.9. CSI Version Register (Default Value: 0x00000000)

6.1.4.10. CSI Channel_0 configuration Register (Default Value: 0x00300200)

6.1.4.11. CSI Channel_0 scale Register (Default Value: 0x00000000)

6.1.4.12. CSI Channel_0 FIFO 0 output buffer-A address Register (Default Value: 0x00000000)

6.1.4.13. CSI Channel_0 FIFO 1 output buffer-A address Register (Default Value: 0x00000000)

6.1.4.14. CSI Channel_0 FIFO 2 output buffer-A address Register (Default Value: 0x00000000)

6.1.4.15. CSI Channel_0 status Register (Default Value: 0x00000000)

6.1.4.16. CSI Channel_0 interrupt enable Register (Default Value: 0x00000000)

6.1.4.17. CSI Channel_0 interrupt status Register (Default Value: 0x00000000)

6.1.4.18. CSI Channel_0 filed1 vertical size Register (Default Value: 0x01E00000)

6.1.4.19. CSI Channel_0 horizontal size Register (Default Value: 0x05000000)

6.1.4.20. CSI Channel_0 vertical size Register (Default Value: 0x01E00000)

6.1.4.21. CSI Channel_0 buffer length Register (Default Value: 0x01400280)

6.1.4.22. CSI Channel_0 flip size Register (Default Value: 0x01E00280)

6.1.4.23. CSI Channel_0 frame clock counter Register (Default Value: 0x00000000)

6.1.4.24. CSI Channel_0 accumulated and internal clock counter Register (Default Value: 0x00000000)

6.1.4.25. CSI Channel_0 FIFO Statistic Register (Default Value: 0x00000000)

6.1.4.26. CSI Channel_0 PCLK Statistic Register (Default Value: 0x00007FFF)

6.1.4.27. CCI Control Register (Default Value: 0x00000000)

6.1.4.28. CCI Transmission Configuration Register (Default Value: 0x10000000)

6.1.4.29. CCI Packet Format Register (Default Value: 0x00110001)

6.1.4.30. CCI Bus Control Register (Default Value: 0x00002500)

6.1.4.31. CCI Interrupt Control Register (Default Value: 0x00000000)

6.1.4.32. CCI Line Counter Trigger Control Register (Default Value: 0x00000000)

6.1.4.33. CCI FIFO Acess Register (Default Value: 0x00000000)

6.2. MIPI CSI2

6.2.1. Overview

Chapter 7 Display

7.1. Display Engine 2.0

7.1.1. Overview

7.2. TCON

7.2.1. Overview

7.2.2. Block Diagram

7.2.3. Functionalities Description

7.2.3.1. Panel Interface

7.2.3.2. RGB gamma correction

7.2.3.3. CEU module

7.2.3.4. CMAP module

7.2.4. TCON Module Register List

7.2.5. TCON Module Register Description

7.2.5.1. TCON_GCTL_REG (Default Value: 0x00000000)

7.2.5.2. TCON_GINT0_REG (Default Value: 0x00000000)

7.2.5.3. TCON_GINT1_REG (Default Value: 0x00000000)

7.2.5.4. TCON0_TRM_CTL_REG (Default Value: 0x00000000)

7.2.5.5. TCON0_FRM_SEED_REG (Default Value: 0x00000000)

7.2.5.6. TCON0_FRM_TAB_REG (Default Value: 0x00000000)

7.2.5.7. TCON0_CTL_REG (Default Value: 0x00000000)

7.2.5.8. TCON0_DCLK_REG (Default Value: 0x00000000)

7.2.5.9. TCON0_BASIC0_REG (Default Value: 0x00000000)

7.2.5.10. TCON0_BASIC1_REG (Default Value: 0x00000000)

7.2.5.11. TCON0_BASIC2_REG (Default Value: 0x00000000)

7.2.5.12. TCON0_BASIC3_REG (Default Value: 0x00000000)

7.2.5.13. TCON0_HV_IF_REG (Default Value: 0x00000000)

7.2.5.14. TCON0_CPU_IF_REG (Default Value: 0x00000000)

7.2.5.15. TCON0_CPU_WR_REG (Default Value: 0x00000000)

7.2.5.16. TCON0_CPU_RD0_REG (Default Value: 0x00000000)

7.2.5.17. TCON0_CPU_RD1_REG (Default Value: 0x00000000)

7.2.5.18. TCON0_IO_POL_REG (Default Value: 0x00000000)

7.2.5.19. TCON0_IO_TRI_REG (Default Value: 0x0FFFFFFF)

7.2.5.20. TCON_ECC_FIFO_REG (Default Value: 0x00000000)

7.2.5.21. TCON_DEBUG_REG (Default Value: 0x00000000)

7.2.5.22. TCON_CEU_CTL_REG (Default Value: 0x00000000)

7.2.5.23. TCON_CEU_COEF_MUL_REG (Default Value: 0x00000000)

7.2.5.24. TCON_CEU_COEF_ADD_REG (Default Value: 0x00000000)

7.2.5.25. TCON_CEU_COEF_RANG_REG (Default Value: 0x00000000)

7.2.5.26. TCON0_CPU_TRI0_REG (Default Value: 0x00000000)

7.2.5.27. TCON0_CPU_TRI1_REG (Default Value: 0x00000000)

7.2.5.28. TCON0_CPU_TRI2_REG (Default Value: 0x00200000)

7.2.5.29. TCON0_CPU_TRI3_REG (Default Value: 0x00000000)

7.2.5.30. TCON_CMAP_CTL_REG (Default Value: 0x00000000)

7.2.5.31. TCON_CMAP_ODD0_REG (Default Value: 0x00000000)

7.2.5.32. TCON_CMAP_ODD1_REG (Default Value: 0x00000000)

7.2.5.33. TCON_CMAP_EVEN0_REG (Default Value: 0x00000000)

7.2.5.34. TCON_CMAP_EVEN1_REG (Default Value: 0x00000000)

7.2.5.35. TCON_SAFE_PERIOD_REG (Default Value: 0x00000000)

Chapter 8 Interfaces

8.1. TWI

8.1.1. Overview

8.1.2. Timing Diagram

8.1.3. TWI Controller Special Requirement

8.1.3.1. TWI Pin List

8.1.3.2. TWI Controller Operation

8.1.4. TWI Controller Register List

8.1.5. TWI Controller Register Description

8.1.5.1. TWI Slave Address Register(Default Value: 0x00000000)

8.1.5.2. TWI Extend Address Register(Default Value: 0x00000000)

8.1.5.3. TWI Data Register(Default Value: 0x00000000)

8.1.5.4. TWI Control Register(Default Value: 0x00000000)

8.1.5.5. TWI Status Register(Default Value: 0x000000F8)

8.1.5.6. TWI Clock Register(Default Value: 0x00000000)

8.1.5.7. TWI Soft Reset Register(Default Value: 0x00000000)

8.1.5.8. TWI Enhance Feature Register(Default Value: 0x00000000)

8.1.5.9. TWI Line Control Register(Default Value: 0x0000003A)

8.1.5.10. TWI DVFS Control Register(Default Value: 0x00000000)

8.2. SPI

8.2.1. Overview

8.2.2. SPI Timing Diagram

8.2.3. SPI Special Requirement

8.2.3.1. SPI Pin List

8.2.3.2. SPI Module Clock Source and Frequency

8.2.4. SPI Register List

8.2.5. SPI Register Description

8.2.5.1. SPI Global Control Register(Default Value: 0x00000080)

8.2.5.2. SPI Transfer Control Register(Default Value: 0x00000087)

8.2.5.3. SPI Interrupt Control Register(Default Value: 0x00000000)

8.2.5.4. SPI Interrupt Status Register(Default Value: 0x00000022)

8.2.5.5. SPI FIFO Control Register(Default Value: 0x00400001)

8.2.5.6. SPI FIFO Status Register(Default Value: 0x00000000)

8.2.5.7. SPI Wait Clock Register(Default Value: 0x0000_0000)

8.2.5.8. SPI Clock Control Register(Default Value: 0x00000002)

8.2.5.9. SPI Master Burst Counter Register(Default Value: 0x00000000)

8.2.5.10. SPI Master Transmit Counter Register(Default Value: 0x00000000)

8.2.5.11. SPI Master Burst Control Counter Register(Default Value: 0x00000000)

8.2.5.12. SPI TX Data Register(Default Value: 0x00000000)

8.2.5.13. SPI RX Data Register(Default Value: 0x00000000)

8.3. UART

8.3.1. Overview

8.3.2. UART Timing Diagram

8.3.3. UART Pin List

8.3.4. UART Register List

8.3.5. UART Register Description

8.3.5.1. UART Receiver Buffer Register(Default Value: 0x00000000)

8.3.5.2. UART Transmit Holding Register(Default Value: 0x00000000)

8.3.5.3. UART Divisor Latch Low Register(Default Value: 0x00000000)

8.3.5.4. UART Divisor Latch High Register(Default Value: 0x00000000)

8.3.5.5. UART Interrupt Enable Register(Default Value: 0x00000000)

8.3.5.6. UART Interrupt Identity Register(Default Value: 0x00000000)

8.3.5.7. UART FIFO Control Register(Default Value: 0x00000000)

8.3.5.8. UART Line Control Register(Default Value: 0x00000000)

8.3.5.9. UART Modem Control Register(Default Value: 0x00000000)

8.3.5.10. UART Line Status Register(Default Value: 0x00000060)

8.3.5.11. UART Modem Status Register(Default Value: 0x00000000)

8.3.5.12. UART Scratch Register(Default Value: 0x00000000)

8.3.5.13. UART Status Register(Default Value: 0x00000006)

8.3.5.14. UART Transmit FIFO Level Register(Default Value: 0x00000000)

8.3.5.15. UART Receive FIFO Level Register(Default Value: 0x00000000)

8.3.5.16. UART Halt TX Register(Default Value: 0x00000000)

8.4. USB

8.4.1. USB OTG Controller

8.4.1.1. Block Diagram

8.4.1.2. USB OTG Register List

8.4.1.3. EHCI Register Description

8.4.1.3.1. EHCI Identification Register(Default Value: Implementation Dependent)

8.4.1.3.2. EHCI Host Interface Version Number Register(Default Value: 0x0100)

8.4.1.3.3. EHCI Host Control Structural Parameter Register(Default Value: Implementation Dependent)

8.4.1.3.4. EHCI Host Control Capability Parameter Register(Default Value: Implementation Dependent)

8.4.1.3.5. EHCI Companion Port Route Description (Default Value: UNDEFINED)

8.4.1.3.6. EHCI USB Command Register (Default Value: 0x00080000(0x00080B00 if Asynchronous Schedule Park Capability is a one))

8.4.1.3.7. EHCI USB Status Register (Default Value: 0x00001000)

8.4.1.3.8. EHCI USB Interrupt Enable Register (Default Value: 0x00000000)

8.4.1.3.9. EHCI Frame Index Register (Default Value: 0x00000000)

8.4.1.3.10. EHCI Periodic Frame List Base Address Register (Default Value: Undefined)

8.4.1.3.11. EHCI Current Asynchronous List Address Register (Default Value: Undefined)

8.4.1.3.12. EHCI Configure Flag Register (Default Value: 0x00000000)

8.4.1.3.13. EHCI Port Status and Control Register (Default Value: 0x00002000(w/PPC set to one);0x00003000

8.4.1.4. OHCI Register Description

8.4.1.4.1. HcRevision Register(Default Value: 0x00000010)

8.4.1.4.2. HcControl Register(Default Value: 0x00000000)

8.4.1.4.3. HcCommandStatus Register(Default Value: 0x00000000)

8.4.1.4.4. HcInterruptStatus Register(Default Value: 0x00000000)

8.4.1.4.5. HcInterruptEnable Register(Default Value: 0x00000000)

8.4.1.4.6. HcInterruptDisable Register(Default Value: 0x00000000)

8.4.1.4.7. HcHCCA Register(Default Value: 0x00000000)

8.4.1.4.8. HcPeriodCurrentED Register(Default Value: 0x00000000)

8.4.1.4.9. HcControlHeadED Register(Default Value: 0x00000000)

8.4.1.4.10. HcControlCurrentED Register(Default Value: 0x00000000)

8.4.1.4.11. HcBulkHeadED Register(Default Value: 0x00000000)

8.4.1.4.12. HcBulkCurrentED Register(Default Value: 0x00000000)

8.4.1.4.13. HcDoneHead Register(Default Value: 0x00000000)

8.4.1.4.14. HcFmInterval Register(Default Value: 0x00002EDF)

8.4.1.4.15. HcFmRemaining Register(Default Value: 0x00000000)

8.4.1.4.16. HcFmNumber Register(Default Value: 0x00000000)

8.4.1.4.17. HcPeriodicStart Register(Default Value: 0x00000000)

8.4.1.4.18. HcLSThreshold Register(Default Value: 0x00000628)

8.4.1.4.19. HcRhDescriptorA Register(Default Value: 0x02001201)

8.4.1.4.20. HcRhDescriptorB Register(Default Value: 0x00000000)

8.4.1.4.21. HcRhStatus Register(Default Value: 0x00000000)

8.4.1.4.22. HcRhPortStatus Register(Default Value: 0x00000100)

8.4.1.5. HCI Interface Control and PHY Interface Description

8.4.1.5.1. HCI Interface Control Register(Default Value: 0x10000000)

8.4.1.5.2. HSIC status Register(Default Value: 0x00000000)

8.4.1.5.3. HSIC UTMI PHY TUNE Register(Default Value: 0x23438E4)

8.4.1.5.4. HSIC HSIC PHY CFG(Default Value: 0x00000000)

8.4.1.5.5. HSIC HSIC PHY STATUS(Default Value: 0x00000000)

8.5. EMAC

8.5.1. Overview

8.5.2. Block Diagram

8.5.3. EMAC Core Register List

8.5.4. EMAC Core Register Description

8.5.4.1. Basic Control 0 Register(Default Value: 0x00000000)

8.5.4.2. Basic Control 1 Register(Default Value: 0x08000000)

8.5.4.3. Interrupt Status Register(Default Value: 0x00000000)

8.5.4.4. Interrupt Enable Register(Default Value: 0x00000000)

8.5.4.5. Transmit Control 0 Register(Default Value: 0x00000000)

8.5.4.6. Transmit Control 1 Register(Default Value: 0x00000000)

8.5.4.7. Transmit Flow Control Register(Default Value: 0x00000000)

8.5.4.8. Transmit DMA Descriptor List Address Register(Default Value: 0x00000000)

8.5.4.9. Receive Control 0 Register(Default Value: 0x00000000)

8.5.4.10. Receive Control 1 Register(Default Value: 0x00000000)

8.5.4.11. Receive DMA Descriptor List Address Register(Default Value: 0x00000000)

8.5.4.12. Receive Frame Filter Register(Default Value: 0x00000000)

8.5.4.13. Receive Hash Table 0 Register(Default Value: 0x00000000)

8.5.4.14. Receive Hash Table 1 Register(Default Value: 0x00000000)

8.5.4.15. MII Command Register(Default Value: 0x00000000)

8.5.4.16. MII Data Register(Default Value: 0x00000000)

8.5.4.17. MAC Address 0 High Register(Default Value: 0x0000FFFF)

8.5.4.18. MAC Address 0 Low Register(Default Value: 0xFFFFFFFF)

8.5.4.19. MAC Address x High Register(Default Value: 0x0000FFFF)

8.5.4.20. MAC Address x Low Register(Default Value: 0xFFFFFFFF)

8.5.4.21. Transmit DMA Status Register(Default Value: 0x00000000)

8.5.4.22. Transmit DMA Current Descriptor Register(Default Value: 0x00000000)

8.5.4.23. Transmit DMA Current Buffer Address Register(Default Value: 0x00000000)

8.5.4.24. Receive DMA Status Register(Default Value: 0x00000000)

8.5.4.25. Receive DMA Current Descriptor Register(Default Value: 0x00000000)

8.5.4.26. Receive DMA Current Buffer Address Register(Default Value: 0x00000000)

8.5.4.27. RGMII Status Register(Default Value: 0x00000000)

8.5.5. EMAC RX/TX Descriptor

8.5.5.1. Transmit Descriptor

1st Word of Transmit Descriptor

2nd Word of Transmit Descriptor

3rd Word of Transmit Descriptor

4th Word of Transmit Descriptor

8.5.5.2. Receive Descriptor

1st Word of Receive Descriptor

2nd Word of Receive Descriptor

3rd Word of Receive Descriptor

4th Word of Receive Descriptor

Chapter 9 Electrical Characteristics

9.1. Absolute Maximum Ratings

9.2. Recommended Operating Conditions

9.3. DC Electrical Characteristics

9.4. Oscillator Electrical Characteristics

9.5. Power on and Power off Sequence

Appendix

Pin Map

Package dimension

V3s Declaration This documentation is the original work and copyrighted property of Allwinner Technology Co.,Ltd.(“Allwinner”). Reproduction in whole or in part must obtain the written approval of Allwinner and give clear acknowledgement to the copyright owner. The information furnished by Allwinner is believed to be accurate and reliable. Allwinner reserves the right to make changes in circuit design and/or specifications at any time without notice. Allwinner does not assume any responsibility and liability for its use. Nor for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Allwinner. This documentation neither states nor implies warranty of any kind, including fitness for any particular application. Third party licences may be required to implement the solution/product. Customers shall be solely responsible to obtain all appropriately required third party licences. Allwinner shall not be liable for any licence fee or royalty due in respect of any required third party licence. Allwinner shall have no warranty, indemnity or other obligations with respect to matters covered under any required third party licence. V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 2 confidential

V3s Revision History Version V1.0 Date Nov.17,2014 Description Initial release version V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 3 confidential

V3s Table of Contents Declaration ............................................................................................................................................................................ 2 Revision History..................................................................................................................................................................... 3 Table of Contents .................................................................................................................................................................. 4 Chapter 1 About This Documentation ......................................................................................................................... 36 1.1. Documentation Overview ........................................................................................................................... 36 1.2. Acronyms and abbreviations ....................................................................................................................... 36 Chapter 2 Overview ..................................................................................................................................................... 40 2.1. Processor Features ...................................................................................................................................... 41 2.1.1. CPU Architecture ................................................................................................................................. 41 2.1.2. Memory Subsystem ............................................................................................................................. 41 2.1.2.1. Boot ROM .................................................................................................................................... 41 2.1.2.2. SDRAM ........................................................................................................................................ 41 2.1.2.3. SD/MMC Interface ...................................................................................................................... 41 2.1.3. System Peripheral ................................................................................................................................ 42 2.1.3.1. Timer ........................................................................................................................................... 42 2.1.3.2. High Speed Timer ........................................................................................................................ 42 2.1.3.3. GIC ............................................................................................................................................... 42 2.1.3.4. DMA ............................................................................................................................................ 42 2.1.3.5. CCU .............................................................................................................................................. 42 2.1.3.6. PWM ........................................................................................................................................... 43 2.1.3.7. RTC .............................................................................................................................................. 43 V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 4 confidential

V3s 2.1.3.8. LRADC .......................................................................................................................................... 43 2.1.3.9. Crypto Engine .............................................................................................................................. 43 2.1.4. Display Subsystem ............................................................................................................................... 43 2.1.4.1. Display Engine2.0 ........................................................................................................................ 43 2.1.4.2. Display Output ............................................................................................................................ 44 2.1.5. Video Engine ....................................................................................................................................... 44 2.1.5.1. Video Decoding ........................................................................................................................... 44 2.1.5.2. Video Encoding ........................................................................................................................... 44 2.1.6. Image Subsystem ................................................................................................................................. 44 2.1.6.1. Image Input ................................................................................................................................. 44 2.1.6.2. ISP ................................................................................................................................................ 45 2.1.7. Audio Subsystem ................................................................................................................................. 45 2.1.7.1. Audio codec ................................................................................................................................. 45 2.1.8. External Peripherals ............................................................................................................................ 46 2.1.8.1. USB .............................................................................................................................................. 46 2.1.8.2. Ethernet ...................................................................................................................................... 46 2.1.8.3. UART............................................................................................................................................ 46 2.1.8.4. SPI ................................................................................................................................................ 46 2.1.8.5. TWI .............................................................................................................................................. 47 2.1.9. Package ................................................................................................................................................ 47 2.2. System Block Diagram ................................................................................................................................. 48 Chapter 3 Pin Description ............................................................................................................................................ 49 3.1. Pin Characteristics ....................................................................................................................................... 49 3.2. GPIO Multiplex Functions ............................................................................................................................ 53 V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 5 confidential

V3s 3.3. Detailed Pin/Signal Description ................................................................................................................... 55 Chapter 4 System ......................................................................................................................................................... 58 4.1. Memory Mapping ....................................................................................................................................... 59 4.2. Boot System ................................................................................................................................................ 60 4.3. CCU .............................................................................................................................................................. 61 4.3.1. Overview ............................................................................................................................................. 61 4.3.2. Functionalities Description .................................................................................................................. 62 4.3.2.1. System Bus .................................................................................................................................. 62 4.3.2.2. Bus clock tree .............................................................................................................................. 63 4.3.3. Typical Applications ............................................................................................................................. 63 4.3.4. Register List ......................................................................................................................................... 64 4.3.5. Register Description ............................................................................................................................ 65 4.3.5.1. PLL_CPU Control Register (Default Value: 0x00001000) ............................................................ 65 4.3.5.2. PLL_Audio Control Register (Default Value: 0x00035514) .......................................................... 66 4.3.5.3. PLL_VIDEO Control Register (Default Value: 0x03006207).......................................................... 67 4.3.5.4. PLL_VE Control Register (Default Value: 0x03006207)................................................................ 68 4.3.5.5. PLL_DDR0 Control Register (Default Value: 0x00001000)........................................................... 69 4.3.5.6. PLL_PERIPH0 Control Register (Default Value: 0x00041811) ...................................................... 70 4.3.5.7. PLL_ISP Control Register (Default Value: 0x03006207) ............................................................... 72 4.3.5.8. PLL_PERIPH1 Control Register (Default Value: 0x00041811) ...................................................... 73 4.3.5.9. PLL_DDR1 Control Register (Default Value: 0x00001800)........................................................... 74 4.3.5.10. CPU/AXI Configuration Register (Default Value: 0x00010000).................................................. 75 4.3.5.11. AHB1/APB1 Configuration Register (Default Value: 0x00001010)............................................. 75 4.3.5.12. APB2 Configuration Register (Default Value: 0x01000000) ...................................................... 76 V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 6 confidential

V3s 4.3.5.13. AHB2 Configuration Register (Default Value: 0x00000000) ...................................................... 77 4.3.5.14. Bus Clock Gating Register0 (Default Value: 0x00000000) ......................................................... 77 4.3.5.15. Bus Clock Gating Register1 (Default Value: 0x00000000) ......................................................... 78 4.3.5.16. Bus Clock Gating Register2 (Default Value: 0x00000000) ......................................................... 79 4.3.5.17. Bus Clock Gating Register3 (Default Value: 0x00000000) ......................................................... 79 4.3.5.18. Bus Clock Gating Register4 (Default Value: 0x00000000) ......................................................... 80 4.3.5.19. SDMMC0 Clock Register (Default Value: 0x00000000) ............................................................. 80 4.3.5.20. SDMMC1 Clock Register (Default Value: 0x00000000) ............................................................. 81 4.3.5.21. SDMMC2 Clock Register (Default Value: 0x00000000) ............................................................. 82 4.3.5.22. CE Clock Register (Default Value: 0x00000000) ........................................................................ 83 4.3.5.23. SPI0 Clock Register (Default Value: 0x00000000) ..................................................................... 84 4.3.5.24. USBPHY Configuration Register (Default Value: 0x00000000) .................................................. 84 4.3.5.25. DRAM Configuration Register (Default Value: 0x00000001) ..................................................... 85 4.3.5.26. PLL_DDR1 Configuration Register (Default Value: 0x00000030) .............................................. 85 4.3.5.27. MBUS Reset Register (Default Value: 0x80000000) .................................................................. 86 4.3.5.28. DRAM Clock Gating Register (Default Value: 0x00000000)....................................................... 86 4.3.5.29. DE Clock Gating Register (Default Value: 0x00000000) ............................................................ 87 4.3.5.30. TCON Clock Register (Default Value: 0x00000000) ................................................................... 87 4.3.5.31. CSI0 Clock Register (Default Value: 0x00000000) ..................................................................... 88 4.3.5.32. CSI1 Clock Register (Default Value: 0x00000000) ..................................................................... 88 4.3.5.33. VE Clock Register (Default Value: 0x00000000) ........................................................................ 89 4.3.5.34. AC Digital Clock Register (Default Value: 0x00000000) ............................................................. 90 4.3.5.35. AVS Clock Register (Default Value: 0x00000000) ...................................................................... 90 4.3.5.36. MBUS Clock Register (Default Value: 0x00000000) .................................................................. 90 V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 7 confidential

V3s 4.3.5.37. MIPI_CSI Register (Default Value: 0x00000000) ....................................................................... 91 4.3.5.38. PLL Stable Time Register0 (Default Value: 0x000000FF) ........................................................... 91 4.3.5.39. PLL Stable Time Register1 (Default Value: 0x000000FF) ........................................................... 91 4.3.5.40. PLL_CPUX Bias Register (Default Value: 0x08100200) .............................................................. 92 4.3.5.41. PLL_AUDIO Bias Register (Default Value: 0x10100000) ............................................................ 92 4.3.5.42. PLL_VIDEO Bias Register (Default Value: 0x10100000) ............................................................. 93 4.3.5.43. PLL_VE Bias Register (Default Value: 0x10100000) ................................................................... 93 4.3.5.44. PLL_DDR0 Bias Register (Default Value: 0x81104000) .............................................................. 93 4.3.5.45. PLL_PERIPH0 Bias Register (Default Value: 0x10100010) ......................................................... 94 4.3.5.46. PLL_ISP Bias Register (Default Value: 0x10100000) .................................................................. 94 4.3.5.47. PLL_PERIPH1 Bias Register (Default Value: 0x10100010) ......................................................... 95 4.3.5.48. PLL_DDR1 Bias Register (Default Value: 0x10010000) .............................................................. 95 4.3.5.49. PLL_CPU Tuning Register (Default Value: 0x0A101000) ............................................................ 95 4.3.5.50. PLL_DDR0 Tuning Register (Default Value: 0x14880000) .......................................................... 96 4.3.5.51. PLL_CPU Pattern Control Register (Default Value: 0x00000000) .............................................. 97 4.3.5.52. PLL_AUDIO Pattern Control Register(Default Value: 0x00000000) ........................................... 97 4.3.5.53. PLL_VIDEO Pattern Control Register (Default Value: 0x00000000) ........................................... 98 4.3.5.54. PLL_VE Pattern Control Register (Default Value: 0x00000000) ................................................. 98 4.3.5.55. PLL_DDR0 Pattern Control Register (Default Value: 0x00000000) ............................................ 99 4.3.5.56. PLL_ISP Pattern Control Register (Default Value: 0x00000000) ................................................ 99 4.3.5.57. PLL_PERIPH1 Pattern Control Register (Default Value: 0x00000000) ..................................... 100 4.3.5.58. PLL_DDR1 Pattern Control Register (Default Value: 0x00000000) .......................................... 100 4.3.5.59. PLL_DDR1 Pattern Control Register1 (Default Value: 0x00000000) ........................................ 101 4.3.5.60. Bus Software Reset Register 0 (Default Value: 0x00000000) .................................................. 101 V3s Datasheet(Revision 1.0) Copyright© 2014 Allwinner Technology Co.,Ltd. All Rights Reserved. Page 8 confidential

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