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PCIe M.2 specification.pdf
PCI Express M.2
Specification
Revision 0.7, Version 1.0
November 27, 2012
Revision History
Initial Draft
The spec is structurally and content complete with a limited number of
known TBD parameters/items
Date
May 16, 2012
August 1, 2012
Revision Version History
0.3
0.5
0.7
1.0
The spec is structurally and content complete with a limited number of
known TBD parameters/items.
Text edit and new template.
November 17, 2012
PCI-SIG® disclaims all warranties and liability for the use of this document and the information contained herein
and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a
commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of this specification.
Questions regarding the PCI Code and ID Assignment Specification or membership in PCI-SIG may be
forwarded to:
Membership Services
www.pcisig.com
E-mail: administration@pcisig.com
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503-644-6708
Fax:
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techsupp@pcisig.com
DISCLAIMER
This PCI Code and ID Assignment Specification is provided “as is” with no warranties whatsoever, including
any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise
arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of
proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted herein.
PCI Express M.2 Specification
Table of Contents
1.
Introduction to M.2 Electro-Mechanical Specifications ................................ 17
1.1. Targeted Application ......................................................................................................18
1.2. Specification References ...............................................................................................19
2.
Mechanical Specification ................................................................................. 20
2.1. Overview .......................................................................................................................20
2.2. Card Type Naming Convention .....................................................................................22
2.3. Card Specifications........................................................................................................25
2.3.1. Card Form Factors Intended for Connectivity Socket 1 .......................................................... 26
2.3.1.1. Type 2230 Specification .................................................................................................... 26
2.3.1.2. Type 1630 Specification .................................................................................................... 29
2.3.1.3. Type 3030 Specification .................................................................................................... 31
2.3.2. Card Form Factor Intended for WWAN Socket 2 .................................................................... 32
2.3.2.1. Type 3042 Specification .................................................................................................... 32
2.3.3. Card Form Factor for SSD Socket 2 ....................................................................................... 33
2.3.3.1. Type 2230 Specification .................................................................................................... 33
2.3.4. Card Form Factors for SSD Socket 2 and 3 ............................................................................ 34
2.3.4.1. Type 2242 Specification .................................................................................................... 34
2.3.4.2. Type 2260 Specification .................................................................................................... 35
2.3.4.3. Type 2280 Specification .................................................................................................... 36
2.3.4.4. Type 22110 Specification .................................................................................................. 37
2.3.5. Card PCB Details .................................................................................................................... 38
2.3.5.1. Mechanical Outline of Card-Edge ..................................................................................... 38
2.3.5.2. Module Keying .................................................................................................................. 40
2.3.6. Soldered-down Form Factors .................................................................................................. 44
2.3.6.1. Type 2226 Specification .................................................................................................... 44
2.3.6.2. Type 1216 Specification .................................................................................................... 46
2.3.6.3. Type 3026 Specification .................................................................................................... 47
2.3.7. RF Connectors......................................................................................................................... 49
2.3.7.1. Socket 1 & 2 RF Connector Pin-Out ................................................................................. 53
2.4. System Connector Specifications ..................................................................................55
2.4.1. Connector Pin count ................................................................................................................ 56
2.4.2. Contact Pitch ........................................................................................................................... 56
2.4.3. System Connector Parametric Specifications ......................................................................... 56
2.4.4. Additional Environmental Requirements ................................................................................. 58
2.4.5. Card Insertion .......................................................................................................................... 58
2.4.6. Point of Contact Guideline ....................................................................................................... 58
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PCI Express M.2 Specification
2.4.7. Top Side Connection ............................................................................................................... 59
2.4.7.1. Top Side Connector Physical Dimensions ........................................................................ 59
2.4.7.2. Top Side Connection Total System Length ...................................................................... 61
2.4.7.3. Top Side Connection Stack-up ......................................................................................... 62
2.4.7.3.1. Single Sided Module (Using H2.3 Connector) ............................................... 62
2.4.7.3.2. Single Sided Module (Using H2.5 Connector) ............................................... 63
2.4.7.3.3. Double Sided Module (Using H2.8, H3.2 and H4.2 Connector) .................... 64
2.4.7.4. Top Side Connector Layout Pattern.................................................................................. 66
2.4.8. Mid Line Connection (Using M1.8 Connector) ........................................................................ 67
2.4.8.1. Mid Line Connector Physical Dimensions......................................................................... 67
2.4.8.2. Mid Line Connection Total System Length ....................................................................... 68
2.4.8.3. Mid Line Connection Stack-up .......................................................................................... 69
2.4.8.3.1. Single-sided Module ...................................................................................... 69
2.4.8.3.2. Double-sided Module ..................................................................................... 70
2.4.8.4. Mid Line Connector Layout Pattern .................................................................................. 72
2.4.9. Connector Key Dimension ....................................................................................................... 73
2.4.9.1. Host Connector Keying ..................................................................................................... 73
2.5. Module Stand-off ...........................................................................................................76
2.5.1. Recommended Main Board Hole ............................................................................................ 76
2.5.2. Electrical Ground Path ............................................................................................................. 76
2.5.3. Thermal Ground Path .............................................................................................................. 76
2.5.4. Stand-Off Guidelines ............................................................................................................... 79
2.5.4.1. Stand-Off Guidelines Option 1 .......................................................................................... 79
2.5.4.2. Stand-Off Guidelines Option 2 .......................................................................................... 79
2.5.5. Screw Selection Guideline ....................................................................................................... 81
2.5.5.1. Option 1, Wafer-Head Style M3 Screw ............................................................................. 81
2.5.5.2. Option 2, M3 Screw with Tapered Shaft ........................................................................... 82
2.5.5.3. Option 3, Wafer-Head Style M2 Screw ............................................................................. 82
2.5.5.4. Option 4, Flat-Head Style M3 Screw ................................................................................. 83
2.6. Thermal Guidelines for the M.2......................................................................................83
2.6.1. Objective .................................................................................................................................. 83
2.6.2.
Introduction .............................................................................................................................. 84
2.6.2.1. Thermal Design Power Definition ..................................................................................... 84
2.6.2.2. Skin Temperature Definition ............................................................................................. 84
2.6.2.3. Unpowered M.2 Module Temperature .............................................................................. 85
2.6.2.4. System Skin Temperature—Fan-based System .............................................................. 85
2.6.3. System Skin Temperature—Fanless System .......................................................................... 86
2.6.4. Examples ................................................................................................................................. 86
3.
Electrical Specifications .................................................................................. 87
3.1. Connectivity Socket 1 System Interface Signals ............................................................87
3.1.1. Supplemental NFC Signals ..................................................................................................... 90
3.1.2. Power Sources and Grounds .................................................................................................. 90
3.1.3. PCI Express Interface .............................................................................................................. 90
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3.1.4. PCI Express Auxiliary Signals ................................................................................................. 91
3.1.4.1. Reference Clock ................................................................................................................ 91
3.1.4.2. CLKREQ# Signal .............................................................................................................. 92
3.1.4.2.1. Power-up Requirements ................................................................................ 93
3.1.4.2.2. Dynamic Clock Control .................................................................................. 94
3.1.4.3. Clock Request Support Reporting and Enabling .............................................................. 95
3.1.4.4. PERST# Signal ................................................................................................................. 95
3.1.4.5. WAKE# Signal ................................................................................................................... 95
3.1.5. USB Interface .......................................................................................................................... 96
3.1.6. Display Port Interface .............................................................................................................. 96
3.1.6.1. HPD ................................................................................................................................... 96
3.1.6.2. MLDIR ............................................................................................................................... 96
3.1.7. SDIO Interface ......................................................................................................................... 97
3.1.8. UART Interface ........................................................................................................................ 99
3.1.8.1. UART Wakeup .................................................................................................................. 99
3.1.9. PCM/I2S Interface ................................................................................................................. 102
3.1.10. I2C Interface .......................................................................................................................... 103
3.1.10.1. ALERT# Signal ................................................................................................................ 103
3.1.10.2. I2C Data Signal ............................................................................................................... 103
3.1.10.3. I2C Clock Signal .............................................................................................................. 103
3.1.11. NFC Supplemental UIM Interface ......................................................................................... 103
3.1.11.1. UIM Power In .................................................................................................................. 103
3.1.11.2. UIM Power Out ................................................................................................................ 104
3.1.11.3. UIM SWP ........................................................................................................................ 104
3.1.12. Communication Specific Signals ........................................................................................... 104
3.1.12.1. Suspend Clock ................................................................................................................ 104
3.1.12.2. Status Indicators ............................................................................................................. 104
3.1.12.3. W_DISABLE# Signal....................................................................................................... 106
3.1.12.4. Coexistence Signals........................................................................................................ 107
3.1.13. Reserved Pins ....................................................................................................................... 107
3.1.14. Socket 1 Connector Pin-out Definitions ................................................................................. 107
3.1.15. Socket 1 Based Soldered-down Module Pinouts .................................................................. 111
3.2. WWAN/SSD/Other Socket 2 System Interface Signals ................................................ 114
3.2.1. Power Sources and Grounds ................................................................................................ 117
3.2.2. PCI Express Interface ............................................................................................................ 117
3.2.3. USB Interface ........................................................................................................................ 117
3.2.4. HSIC Interface ....................................................................................................................... 117
3.2.5. SSIC Interface ....................................................................................................................... 117
3.2.6. USB3.0 Interface ................................................................................................................... 118
3.2.7. SATA Interface ...................................................................................................................... 118
3.2.8. User Identity Module (UIM) Interface .................................................................................... 118
3.2.8.1. UIM_PWR ....................................................................................................................... 118
3.2.8.2. UIM_RESET .................................................................................................................... 118
3.2.8.3. UIM_CLK ......................................................................................................................... 119
3.2.8.4. UIM_DATA ...................................................................................................................... 119
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3.2.8.5. SIM_DET ......................................................................................................................... 119
3.2.9. Communication-specific Signals............................................................................................ 120
3.2.9.1. Suspend Clock ................................................................................................................ 120
3.2.9.2. Status Indicators ............................................................................................................. 120
3.2.9.3. W_DISABLE# Signals ..................................................................................................... 120
3.2.9.4. Coexistence Signals........................................................................................................ 120
3.2.10. Supplemental Communication Specific Signals .................................................................... 121
3.2.10.1. Full Card Power Off......................................................................................................... 121
3.2.10.1.1. Example of Power On/Off Sequence ......................................................... 121
3.2.10.1.2. Example of Tablet Power On/Off Sequence .............................................. 121
3.2.10.1.3. Example of Very-thin Notebooks Power On/Off Sequence ....................... 122
3.2.10.2. RESET# .......................................................................................................................... 122
3.2.10.3. General Purpose Input Output Pins ................................................................................ 123
3.2.10.3.1. GNSS Signals ............................................................................................ 123
3.2.10.3.2. Audio Signals ............................................................................................. 124
3.2.10.3.3. Second UIM Signals .................................................................................. 124
3.2.10.3.4.
IPC[0..8] Signals ........................................................................................ 124
3.2.10.3.5. DPR Signal................................................................................................. 124
3.2.10.3.6. WAKE_ON_WWAN Signal ........................................................................ 125
3.2.10.4. Antenna Control .............................................................................................................. 125
3.2.11. SSD Specific Signals ............................................................................................................. 125
3.2.11.1. DEVSLP .......................................................................................................................... 125
3.2.11.2. DAS/DSS# ...................................................................................................................... 125
3.2.11.3. Reserved for MFG Clock and Data ................................................................................. 125
3.2.12. Configuration Pins ................................................................................................................. 126
3.2.12.1. Socket 2 Connector Pin-out Definitions .......................................................................... 127
3.3. SSD Socket 3 System Interface Signals ...................................................................... 132
3.3.1. Power and Grounds ............................................................................................................... 133
3.3.2. PCI Express Interface ............................................................................................................ 133
3.3.3. SATA Interface ...................................................................................................................... 133
3.3.4. SSD Specific Signals ............................................................................................................. 133
3.3.4.1. SUSCLK .......................................................................................................................... 133
3.3.4.2. PEDET ............................................................................................................................ 133
3.3.4.3. DEVSLP .......................................................................................................................... 133
3.3.4.4. DAS/DSS# ...................................................................................................................... 134
3.3.4.5. MFG Clock & Data .......................................................................................................... 134
3.3.4.6. Socket 3 Connector Pin-out Definitions .......................................................................... 134
4.
Electrical Requirements ................................................................................. 136
4.1. 3.3 V Logic Signal Requirements ................................................................................. 136
4.1.1. 1.8 V Logic Signal Requirements .......................................................................................... 137
4.1.2. Power ..................................................................................................................................... 137
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5.
Platform Socket Pin-Out and Key Definitions .............................................. 140
5.1. Connectivity Socket; Socket 1 ..................................................................................... 141
5.1.1. Socket 1-DP (Mechanical Key A) On Platform ...................................................................... 142
5.1.2. Socket 1-SD (Mechanical Key E) On Platform ...................................................................... 144
5.1.3. Dual Module key Module: Supports Socket 1-SD and Socket 1-DP ..................................... 146
5.2. WWAN+GNSS/SSD/Other Socket; Socket 2 ............................................................... 146
5.2.1. Socket 2 – Configuration Pin Definitions ............................................................................... 146
5.2.2. Socket 2 Pin-Out (Mechanical Key B) On Platform ............................................................... 148
5.3. SSD Socket; Socket 3 (Mechanical Key M) ................................................................. 150
5.4. Soldered Down Pinout Definitions ............................................................................... 151
6.
Annex .............................................................................................................. 154
6.1. Glossary ...................................................................................................................... 154
6.2. M.2 Signal Directions ................................................................................................... 155
6.3. Signal Integrity Guideline ............................................................................................. 156
6.3.1. Suggested Signal Integrity PCB Layout ................................................................................ 157
6.4. VSWR Test Set-up Method for RF Connector Receptacles ......................................... 158
6.5. Thermal Guideline Annex ............................................................................................ 158
6.5.1. Assumptions .......................................................................................................................... 158
6.5.1.1. Die Thermal Dissipation Overview .................................................................................. 158
6.5.1.2. Component Overview...................................................................................................... 160
6.5.2. Generic System Environment Categories (Assumptions) ..................................................... 161
6.5.2.1. Module Slot Definitions by System ................................................................................. 162
6.5.2.1.1. Systems with Fans ....................................................................................... 162
6.5.2.1.2. Systems without Fans .................................................................................. 162
6.5.3. Assessing Thermal Design Power Capability ........................................................................ 163
6.5.3.1. Use Cases ....................................................................................................................... 163
6.5.3.2. Extended Use Cases ...................................................................................................... 163
6.5.3.3. Unpowered Module ......................................................................................................... 163
6.5.3.4. Use Case Flexibility......................................................................................................... 163
6.5.4. Module Placement Advice ..................................................................................................... 164
6.5.5. Skin Temperature Sensitivity to Module Power ..................................................................... 164
6.5.6. General Applicability .............................................................................................................. 164
6.5.7. Generic assumptions for module arrangement ..................................................................... 164
6.5.8. Examples ............................................................................................................................... 165
6.5.8.1. Notebook Category ......................................................................................................... 165
6.5.8.1.1. Generic Motherboard Assumptions ............................................................. 166
6.5.8.1.2. System Layout Assumptions........................................................................ 166
6.5.8.1.3. Local Skin Temperature ............................................................................... 167
6.5.8.1.4. Thermal Design Power Response – Notebook Category ............................ 168
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6.5.8.2. Thin Platform Notebook with Fan Category .................................................................... 170
6.5.8.2.1. Generic motherboard assumptions .............................................................. 171
6.5.8.2.2. System Layout Assumptions........................................................................ 172
6.5.8.2.3. Module Placement Advice – Thin Platform Notebook ................................. 172
6.5.8.2.4. Local Skin Temperature ............................................................................... 173
6.5.8.2.5. Thermal design Power Response – Thin Platform Notebook with Fan
Category 174
6.5.8.3. Tablet without Fan Category ........................................................................................... 176
6.5.8.3.1. Generic Motherboard Assumptions ............................................................. 177
6.5.8.3.2. System Layout Assumptions........................................................................ 178
6.5.8.3.3. Local Skin Temperature ............................................................................... 178
6.5.8.3.4. Thermal Design Power Response—Tablet Category .................................. 180
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