Xilinx ISE 中调用 FFT IP Core 的源程序 module myfft( clk, xn_re, xn_im, start, fwd_inv, fwd_inv_we, xk_re, xk_im, xn_index, xk_index, rfd, busy,dv, edone, done ); input clk; input [15:0] xn_re; input [15:0] xn_im; input start; input fwd_inv; input fwd_inv_we; output [20:0] xk_re; output [20:0] xk_im; output [3:0] xn_index; output [3:0] xk_index; output rfd; output busy; output dv; 

output edone; output done; fft fft( .clk(clk), .xn_re(xn_re), .xn_im(xn_im), .start(start), .fwd_inv(fwd_inv), .fwd_inv_we(fwd_inv_we), .xk_re(xk_re), .xk_im(xk_im), .xn_index(xn_index), .xk_index(xk_index), .rfd(rfd), .busy(busy), .dv(dv), .edone(edone), .done(done) ); endmodule ②在工程中添加HDL测试文件并命名，进行功能测试。 module tb_myfft; // Inputs reg fwd_inv_we; reg start; reg fwd_inv; reg clk; reg [15:0] xn_re; 

reg [15:0] xn_im; // Outputs wire rfd; wire dv; wire done; wire busy; wire edone; wire [20:0] xk_im; wire [3:0] xn_index; wire [20:0] xk_re; wire [3:0] xk_index; // Instantiate the Unit Under Test (UUT) myfft uut ( .fwd_inv_we(fwd_inv_we), .rfd(rfd), .start(start), .fwd_inv(fwd_inv), .dv(dv), .done(done), .clk(clk), .busy(busy), .edone(edone), .xn_re(xn_re), .xk_im(xk_im), .xn_index(xn_index), .xk_re(xk_re), .xn_im(xn_im), .xk_index(xk_index))； initial begin // Initialize Inputs fwd_inv_we = 0; 

start = 0; fwd_inv = 0; clk = 0; xn_re = 0; xn_im = 0; // Wait 100 ns for global reset to finish; #100； // Add stimulus here fwd_inv_we = 1; fwd_inv = 1; start = 1; end always #5 clk=!clk; always@(posedge clk) begin xn_re = xn_re+1 ; xn_im = xn_im+1 ; end endmodule