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AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual.pdf
Table of Contents
Preface
1 Introduction
1.1 AM335x Family
1.1.1 Device Features
1.1.2 Device Identification
1.1.3 Feature Identification
2 Memory Map
2.1 ARM Cortex-A8 Memory Map
2.2 ARM Cortex-M3 Memory Map
3 ARM MPU Subsystem
3.1 ARM Cortex-A8 MPU Subsystem
3.1.1 Features
3.1.2 MPU Subsystem Integration
3.1.3 MPU Subsystem Clock and Reset Distribution
3.1.3.1 Clock Distribution
3.1.3.2 Reset Distribution
3.1.4 ARM Subchip
3.1.4.1 ARM Overview
3.1.4.2 ARM Description
3.1.4.2.1 ARM® Cortex™-A8 Instruction, Data, and Private Peripheral Port
3.1.4.2.2 ARM Core Supported Features
3.1.5 Interrupt Controller
3.1.6 Power Management
3.1.6.1 Power Domains
3.1.6.2 Power States
3.1.6.3 Power Modes
3.1.7 ARM Programming Model
3.1.7.1 Clock Control
3.1.7.2 MPU Power Mode Transitions
3.1.7.2.1 Basic Power-On Reset
3.1.7.2.2 MPU Into Standby Mode
3.1.7.2.3 MPU Out Of Standby Mode
3.1.7.2.4 MPU Power On From a Powered-Off State
3.1.7.3 NEON Power Mode Transition
4 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
4.1 Introduction
5 Graphics Accelerator (SGX)
5.1 Introduction
5.1.1 POWERVR SGX Main Features
5.1.2 SGX 3D Features
5.1.3 Universal Scalable Shader Engine (USSE) – Key Features
5.1.4 Unsupported Features
5.2 Integration
5.2.1 SGX530 Connectivity Attributes
5.2.2 SGX530 Clock and Reset Management
5.2.3 SGX530 Pin List
5.3 Functional Description
5.3.1 SGX Block Diagram
5.3.2 SGX Elements Description
6 Interrupts
6.1 Functional Description
6.1.1 Interrupt Processing
6.1.1.1 Input Selection
6.1.1.2 Masking
6.1.1.3 Individual Masking
6.1.1.4 Priority Masking
6.1.1.5 Priority Sorting
6.1.2 Register Protection
6.1.3 Module Power Saving
6.1.4 Error Han˜dling
6.1.5 Interrupt Handling
6.2 Basic Programming Model
6.2.1 Initialization Sequence
6.2.2 INTC Processing Sequence
6.2.3 INTC Preemptive Processing Sequence
6.2.4 Interrupt Preemption
6.2.5 ARM A8 INTC Spurious Interrupt Handling
6.3 ARM Cortex-A8 Interrupts
6.4 ARM Cortex-M3 Interrupts
6.5 PWM Events
6.6 Interrupt Controller Registers
6.6.1 INTC Registers
6.6.1.1 INTC_REVISION Register (offset = 0h) [reset = 50h]
6.6.1.2 INTC_SYSCONFIG Register (offset = 10h) [reset = 0h]
6.6.1.3 INTC_SYSSTATUS Register (offset = 14h) [reset = 0h]
6.6.1.4 INTC_SIR_IRQ Register (offset = 40h) [reset = FFFFFF80h]
6.6.1.5 INTC_SIR_FIQ Register (offset = 44h) [reset = FFFFFF80h]
6.6.1.6 INTC_CONTROL Register (offset = 48h) [reset = 0h]
6.6.1.7 INTC_PROTECTION Register (offset = 4Ch) [reset = 0h]
6.6.1.8 INTC_IDLE Register (offset = 50h) [reset = 0h]
6.6.1.9 INTC_IRQ_PRIORITY Register (offset = 60h) [reset = FFFFFFC0h]
6.6.1.10 INTC_FIQ_PRIORITY Register (offset = 64h) [reset = FFFFFFC0h]
6.6.1.11 INTC_THRESHOLD Register (offset = 68h) [reset = FFh]
6.6.1.12 INTC_ITR0 Register (offset = 80h) [reset = 0h]
6.6.1.13 INTC_MIR0 Register (offset = 84h) [reset = FFFFFFFFh]
6.6.1.14 INTC_MIR_CLEAR0 Register (offset = 88h) [reset = 0h]
6.6.1.15 INTC_MIR_SET0 Register (offset = 8Ch) [reset = 0h]
6.6.1.16 INTC_ISR_SET0 Register (offset = 90h) [reset = 0h]
6.6.1.17 INTC_ISR_CLEAR0 Register (offset = 94h) [reset = 0h]
6.6.1.18 INTC_PENDING_IRQ0 Register (offset = 98h) [reset = 0h]
6.6.1.19 INTC_PENDING_FIQ0 Register (offset = 9Ch) [reset = 0h]
6.6.1.20 INTC_ITR1 Register (offset = A0h) [reset = 0h]
6.6.1.21 INTC_MIR1 Register (offset = A4h) [reset = FFFFFFFFh]
6.6.1.22 INTC_MIR_CLEAR1 Register (offset = A8h) [reset = 0h]
6.6.1.23 INTC_MIR_SET1 Register (offset = ACh) [reset = 0h]
6.6.1.24 INTC_ISR_SET1 Register (offset = B0h) [reset = 0h]
6.6.1.25 INTC_ISR_CLEAR1 Register (offset = B4h) [reset = 0h]
6.6.1.26 INTC_PENDING_IRQ1 Register (offset = B8h) [reset = 0h]
6.6.1.27 INTC_PENDING_FIQ1 Register (offset = BCh) [reset = 0h]
6.6.1.28 INTC_ITR2 Register (offset = C0h) [reset = 0h]
6.6.1.29 INTC_MIR2 Register (offset = C4h) [reset = FFFFFFFFh]
6.6.1.30 INTC_MIR_CLEAR2 Register (offset = C8h) [reset = 0h]
6.6.1.31 INTC_MIR_SET2 Register (offset = CCh) [reset = 0h]
6.6.1.32 INTC_ISR_SET2 Register (offset = D0h) [reset = 0h]
6.6.1.33 INTC_ISR_CLEAR2 Register (offset = D4h) [reset = 0h]
6.6.1.34 INTC_PENDING_IRQ2 Register (offset = D8h) [reset = 0h]
6.6.1.35 INTC_PENDING_FIQ2 Register (offset = DCh) [reset = 0h]
6.6.1.36 INTC_ITR3 Register (offset = E0h) [reset = 0h]
6.6.1.37 INTC_MIR3 Register (offset = E4h) [reset = FFFFFFFFh]
6.6.1.38 INTC_MIR_CLEAR3 Register (offset = E8h) [reset = 0h]
6.6.1.39 INTC_MIR_SET3 Register (offset = ECh) [reset = 0h]
6.6.1.40 INTC_ISR_SET3 Register (offset = F0h) [reset = 0h]
6.6.1.41 INTC_ISR_CLEAR3 Register (offset = F4h) [reset = 0h]
6.6.1.42 INTC_PENDING_IRQ3 Register (offset = F8h) [reset = 0h]
6.6.1.43 INTC_PENDING_FIQ3 Register (offset = FCh) [reset = 0h]
6.6.1.44 INTC_ILR0 Register (offset = 100h) [reset = 0h]
6.6.1.45 INTC_ILR1 Register (offset = 104h) [reset = 0h]
6.6.1.46 INTC_ILR2 Register (offset = 108h) [reset = 0h]
6.6.1.47 INTC_ILR3 Register (offset = 10Ch) [reset = 0h]
6.6.1.48 INTC_ILR4 Register (offset = 110h) [reset = 0h]
6.6.1.49 INTC_ILR5 Register (offset = 114h) [reset = 0h]
6.6.1.50 INTC_ILR6 Register (offset = 118h) [reset = 0h]
6.6.1.51 INTC_ILR7 Register (offset = 11Ch) [reset = 0h]
6.6.1.52 INTC_ILR8 Register (offset = 120h) [reset = 0h]
6.6.1.53 INTC_ILR9 Register (offset = 124h) [reset = 0h]
6.6.1.54 INTC_ILR10 Register (offset = 128h) [reset = 0h]
6.6.1.55 INTC_ILR11 Register (offset = 12Ch) [reset = 0h]
6.6.1.56 INTC_ILR12 Register (offset = 130h) [reset = 0h]
6.6.1.57 INTC_ILR13 Register (offset = 134h) [reset = 0h]
6.6.1.58 INTC_ILR14 Register (offset = 138h) [reset = 0h]
6.6.1.59 INTC_ILR15 Register (offset = 13Ch) [reset = 0h]
6.6.1.60 INTC_ILR16 Register (offset = 140h) [reset = 0h]
6.6.1.61 INTC_ILR17 Register (offset = 144h) [reset = 0h]
6.6.1.62 INTC_ILR18 Register (offset = 148h) [reset = 0h]
6.6.1.63 INTC_ILR19 Register (offset = 14Ch) [reset = 0h]
6.6.1.64 INTC_ILR20 Register (offset = 150h) [reset = 0h]
6.6.1.65 INTC_ILR21 Register (offset = 154h) [reset = 0h]
6.6.1.66 INTC_ILR22 Register (offset = 158h) [reset = 0h]
6.6.1.67 INTC_ILR23 Register (offset = 15Ch) [reset = 0h]
6.6.1.68 INTC_ILR24 Register (offset = 160h) [reset = 0h]
6.6.1.69 INTC_ILR25 Register (offset = 164h) [reset = 0h]
6.6.1.70 INTC_ILR26 Register (offset = 168h) [reset = 0h]
6.6.1.71 INTC_ILR27 Register (offset = 16Ch) [reset = 0h]
6.6.1.72 INTC_ILR28 Register (offset = 170h) [reset = 0h]
6.6.1.73 INTC_ILR29 Register (offset = 174h) [reset = 0h]
6.6.1.74 INTC_ILR30 Register (offset = 178h) [reset = 0h]
6.6.1.75 INTC_ILR31 Register (offset = 17Ch) [reset = 0h]
6.6.1.76 INTC_ILR32 Register (offset = 180h) [reset = 0h]
6.6.1.77 INTC_ILR33 Register (offset = 184h) [reset = 0h]
6.6.1.78 INTC_ILR34 Register (offset = 188h) [reset = 0h]
6.6.1.79 INTC_ILR35 Register (offset = 18Ch) [reset = 0h]
6.6.1.80 INTC_ILR36 Register (offset = 190h) [reset = 0h]
6.6.1.81 INTC_ILR37 Register (offset = 194h) [reset = 0h]
6.6.1.82 INTC_ILR38 Register (offset = 198h) [reset = 0h]
6.6.1.83 INTC_ILR39 Register (offset = 19Ch) [reset = 0h]
6.6.1.84 INTC_ILR40 Register (offset = 1A0h) [reset = 0h]
6.6.1.85 INTC_ILR41 Register (offset = 1A4h) [reset = 0h]
6.6.1.86 INTC_ILR42 Register (offset = 1A8h) [reset = 0h]
6.6.1.87 INTC_ILR43 Register (offset = 1ACh) [reset = 0h]
6.6.1.88 INTC_ILR44 Register (offset = 1B0h) [reset = 0h]
6.6.1.89 INTC_ILR45 Register (offset = 1B4h) [reset = 0h]
6.6.1.90 INTC_ILR46 Register (offset = 1B8h) [reset = 0h]
6.6.1.91 INTC_ILR47 Register (offset = 1BCh) [reset = 0h]
6.6.1.92 INTC_ILR48 Register (offset = 1C0h) [reset = 0h]
6.6.1.93 INTC_ILR49 Register (offset = 1C4h) [reset = 0h]
6.6.1.94 INTC_ILR50 Register (offset = 1C8h) [reset = 0h]
6.6.1.95 INTC_ILR51 Register (offset = 1CCh) [reset = 0h]
6.6.1.96 INTC_ILR52 Register (offset = 1D0h) [reset = 0h]
6.6.1.97 INTC_ILR53 Register (offset = 1D4h) [reset = 0h]
6.6.1.98 INTC_ILR54 Register (offset = 1D8h) [reset = 0h]
6.6.1.99 INTC_ILR55 Register (offset = 1DCh) [reset = 0h]
6.6.1.100 INTC_ILR56 Register (offset = 1E0h) [reset = 0h]
6.6.1.101 INTC_ILR57 Register (offset = 1E4h) [reset = 0h]
6.6.1.102 INTC_ILR58 Register (offset = 1E8h) [reset = 0h]
6.6.1.103 INTC_ILR59 Register (offset = 1ECh) [reset = 0h]
6.6.1.104 INTC_ILR60 Register (offset = 1F0h) [reset = 0h]
6.6.1.105 INTC_ILR61 Register (offset = 1F4h) [reset = 0h]
6.6.1.106 INTC_ILR62 Register (offset = 1F8h) [reset = 0h]
6.6.1.107 INTC_ILR63 Register (offset = 1FCh) [reset = 0h]
6.6.1.108 INTC_ILR64 Register (offset = 200h) [reset = 0h]
6.6.1.109 INTC_ILR65 Register (offset = 204h) [reset = 0h]
6.6.1.110 INTC_ILR66 Register (offset = 208h) [reset = 0h]
6.6.1.111 INTC_ILR67 Register (offset = 20Ch) [reset = 0h]
6.6.1.112 INTC_ILR68 Register (offset = 210h) [reset = 0h]
6.6.1.113 INTC_ILR69 Register (offset = 214h) [reset = 0h]
6.6.1.114 INTC_ILR70 Register (offset = 218h) [reset = 0h]
6.6.1.115 INTC_ILR71 Register (offset = 21Ch) [reset = 0h]
6.6.1.116 INTC_ILR72 Register (offset = 220h) [reset = 0h]
6.6.1.117 INTC_ILR73 Register (offset = 224h) [reset = 0h]
6.6.1.118 INTC_ILR74 Register (offset = 228h) [reset = 0h]
6.6.1.119 INTC_ILR75 Register (offset = 22Ch) [reset = 0h]
6.6.1.120 INTC_ILR76 Register (offset = 230h) [reset = 0h]
6.6.1.121 INTC_ILR77 Register (offset = 234h) [reset = 0h]
6.6.1.122 INTC_ILR78 Register (offset = 238h) [reset = 0h]
6.6.1.123 INTC_ILR79 Register (offset = 23Ch) [reset = 0h]
6.6.1.124 INTC_ILR80 Register (offset = 240h) [reset = 0h]
6.6.1.125 INTC_ILR81 Register (offset = 244h) [reset = 0h]
6.6.1.126 INTC_ILR82 Register (offset = 248h) [reset = 0h]
6.6.1.127 INTC_ILR83 Register (offset = 24Ch) [reset = 0h]
6.6.1.128 INTC_ILR84 Register (offset = 250h) [reset = 0h]
6.6.1.129 INTC_ILR85 Register (offset = 254h) [reset = 0h]
6.6.1.130 INTC_ILR86 Register (offset = 258h) [reset = 0h]
6.6.1.131 INTC_ILR87 Register (offset = 25Ch) [reset = 0h]
6.6.1.132 INTC_ILR88 Register (offset = 260h) [reset = 0h]
6.6.1.133 INTC_ILR89 Register (offset = 264h) [reset = 0h]
6.6.1.134 INTC_ILR90 Register (offset = 268h) [reset = 0h]
6.6.1.135 INTC_ILR91 Register (offset = 26Ch) [reset = 0h]
6.6.1.136 INTC_ILR92 Register (offset = 270h) [reset = 0h]
6.6.1.137 INTC_ILR93 Register (offset = 274h) [reset = 0h]
6.6.1.138 INTC_ILR94 Register (offset = 278h) [reset = 0h]
6.6.1.139 INTC_ILR95 Register (offset = 27Ch) [reset = 0h]
6.6.1.140 INTC_ILR96 Register (offset = 280h) [reset = 0h]
6.6.1.141 INTC_ILR97 Register (offset = 284h) [reset = 0h]
6.6.1.142 INTC_ILR98 Register (offset = 288h) [reset = 0h]
6.6.1.143 INTC_ILR99 Register (offset = 28Ch) [reset = 0h]
6.6.1.144 INTC_ILR100 Register (offset = 290h) [reset = 0h]
6.6.1.145 INTC_ILR101 Register (offset = 294h) [reset = 0h]
6.6.1.146 INTC_ILR102 Register (offset = 298h) [reset = 0h]
6.6.1.147 INTC_ILR103 Register (offset = 29Ch) [reset = 0h]
6.6.1.148 INTC_ILR104 Register (offset = 2A0h) [reset = 0h]
6.6.1.149 INTC_ILR105 Register (offset = 2A4h) [reset = 0h]
6.6.1.150 INTC_ILR106 Register (offset = 2A8h) [reset = 0h]
6.6.1.151 INTC_ILR107 Register (offset = 2ACh) [reset = 0h]
6.6.1.152 INTC_ILR108 Register (offset = 2B0h) [reset = 0h]
6.6.1.153 INTC_ILR109 Register (offset = 2B4h) [reset = 0h]
6.6.1.154 INTC_ILR110 Register (offset = 2B8h) [reset = 0h]
6.6.1.155 INTC_ILR111 Register (offset = 2BCh) [reset = 0h]
6.6.1.156 INTC_ILR112 Register (offset = 2C0h) [reset = 0h]
6.6.1.157 INTC_ILR113 Register (offset = 2C4h) [reset = 0h]
6.6.1.158 INTC_ILR114 Register (offset = 2C8h) [reset = 0h]
6.6.1.159 INTC_ILR115 Register (offset = 2CCh) [reset = 0h]
6.6.1.160 INTC_ILR116 Register (offset = 2D0h) [reset = 0h]
6.6.1.161 INTC_ILR117 Register (offset = 2D4h) [reset = 0h]
6.6.1.162 INTC_ILR118 Register (offset = 2D8h) [reset = 0h]
6.6.1.163 INTC_ILR119 Register (offset = 2DCh) [reset = 0h]
6.6.1.164 INTC_ILR120 Register (offset = 2E0h) [reset = 0h]
6.6.1.165 INTC_ILR121 Register (offset = 2E4h) [reset = 0h]
6.6.1.166 INTC_ILR122 Register (offset = 2E8h) [reset = 0h]
6.6.1.167 INTC_ILR123 Register (offset = 2ECh) [reset = 0h]
6.6.1.168 INTC_ILR124 Register (offset = 2F0h) [reset = 0h]
6.6.1.169 INTC_ILR125 Register (offset = 2F4h) [reset = 0h]
6.6.1.170 INTC_ILR126 Register (offset = 2F8h) [reset = 0h]
6.6.1.171 INTC_ILR127 Register (offset = 2FCh) [reset = 0h]
7 Memory Subsystem
7.1 GPMC
7.1.1 Introduction
7.1.1.1 GPMC Features
7.1.1.2 Block Diagram
7.1.1.3 Unsupported GPMC Features
7.1.2 Integration
7.1.2.1 GPMC Connectivity Attributes
7.1.2.2 GPMC Clock and Reset Management
7.1.2.3 GPMC Signal List
7.1.3 Functional Description
7.1.3.1 GPMC Signals
7.1.3.2 GPMC Modes
7.1.3.3 GPMC Functional Description
7.1.3.3.1 GPMC Clock Configuration
7.1.3.3.2 GPMC Software Reset
7.1.3.3.3 GPMC Power Management
7.1.3.3.4 GPMC Interrupt Requests
7.1.3.3.5 GPMC DMA Requests
7.1.3.3.6 L3 Slow Interconnect Interface
7.1.3.3.7 GPMC Address and Data Bus
7.1.3.3.8 Address Decoder and Chip-Select Configuration
7.1.3.3.9 Timing Setting
7.1.3.3.10 NOR Access Description
7.1.3.3.11 pSRAM Access Specificities
7.1.3.3.12 NAND Access Description
7.1.3.4 GPMC High-Level Programming Model Overview
7.1.3.5 GPMC Initialization
7.1.3.6 GPMC Configuration in NOR Mode
7.1.3.7 GPMC Configuration in NAND Mode
7.1.3.8 Set Memory Access
7.1.3.9 GPMC Timing Parameters
7.1.3.9.1 GPMC Timing Parameters Formulas
7.1.4 Use Cases
7.1.4.1 How to Set GPMC Timing Parameters for Typical Accesses
7.1.4.1.1 External Memory Attached to the GPMC Module
7.1.4.1.2 Typical GPMC Setup
7.1.4.1.3 GPMC Configuration for Synchronous Burst Read Access
7.1.4.1.4 GPMC Configuration for Asynchronous Read Access
7.1.4.1.5 GPMC Configuration for Asynchronous Single Write Access
7.1.4.2 How to Choose a Suitable Memory to Use With the GPMC
7.1.4.2.1 Supported Memories or Devices
7.1.4.2.2 NAND Interface Protocol
7.1.4.2.3 NOR Interface Protocol
7.1.4.2.4 Other Technologies
7.1.4.2.5 Supported Protocols
7.1.4.2.6 GPMC Features and Settings
7.1.5 Registers
7.1.5.1 GPMC_REVISION
7.1.5.2 GPMC_SYSCONFIG
7.1.5.3 GPMC_SYSSTATUS
7.1.5.4 GPMC_IRQSTATUS
7.1.5.5 GPMC_IRQENABLE
7.1.5.6 GPMC_TIMEOUT_CONTROL
7.1.5.7 GPMC_ERR_ADDRESS
7.1.5.8 GPMC_ERR_TYPE
7.1.5.9 GPMC_CONFIG
7.1.5.10 GPMC_STATUS
7.1.5.11 GPMC_CONFIG1_i
7.1.5.12 GPMC_CONFIG2_i
7.1.5.13 GPMC_CONFIG3_i
7.1.5.14 GPMC_CONFIG4_i
7.1.5.15 GPMC_CONFIG5_i
7.1.5.16 GPMC_CONFIG6_i
7.1.5.17 GPMC_CONFIG7_i
7.1.5.18 GPMC_NAND_COMMAND_i
7.1.5.19 GPMC_NAND_ADDRESS_i
7.1.5.20 GPMC_NAND_DATA_i
7.1.5.21 GPMC_PREFETCH_CONFIG1
7.1.5.22 GPMC_PREFETCH_CONFIG2
7.1.5.23 GPMC_PREFETCH_CONTROL
7.1.5.24 GPMC_PREFETCH_STATUS
7.1.5.25 GPMC_ECC_CONFIG
7.1.5.26 GPMC_ECC_CONTROL
7.1.5.27 GPMC_ECC_SIZE_CONFIG
7.1.5.28 GPMC_ECCj_RESULT
7.1.5.29 GPMC_BCH_RESULT0_i
7.1.5.30 GPMC_BCH_RESULT1_i
7.1.5.31 GPMC_BCH_RESULT2_i
7.1.5.32 GPMC_BCH_RESULT3_i
7.1.5.33 GPMC_BCH_SWDATA
7.1.5.34 GPMC_BCH_RESULT4_i
7.1.5.35 GPMC_BCH_RESULT5_i
7.1.5.36 GPMC_BCH_RESULT6_i
7.2 OCMC-RAM
7.2.1 Introduction
7.2.1.1 OCMC RAM Features
7.2.1.2 Unsupported OCMC RAM Features
7.2.2 Integration
7.2.2.1 OCMC RAM Connectivity Attributes
7.2.2.2 OCMC RAM Clock and Reset Management
7.2.2.3 OCMC RAM Pin List
7.3 EMIF
7.3.1 Introduction
7.3.1.1 Features
7.3.1.2 Unsupported EMIF Features
7.3.2 Integration
7.3.2.1 EMIF Connectivity Attributes
7.3.2.2 EMIF Clock Management
7.3.2.3 EMIF Pin List
7.3.3 Functional Description
7.3.3.1 Signal Descriptions
7.3.3.2 Clock Control
7.3.3.3 DDR2/3/mDDR Memory Controller Subsytem Overview
7.3.3.3.1 DDR2/3/mDDR Memory Controller Interface
7.3.3.3.2 Data Macro
7.3.3.3.3 Command Macro
7.3.3.3.4 VTP Controller Macro
7.3.3.3.5 DQS-Gate IOs
7.3.3.4 Address Mapping
7.3.3.4.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0
7.3.3.4.2 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 0
7.3.3.4.3 Address Mapping when REG_IBANK_POS=2 and REG_EBANK_POS = 0
7.3.3.4.4 Address Mapping when REG_IBANK_POS= 3 and REG_EBANK_POS = 0
7.3.3.4.5 Address Mapping when REG_IBANK_POS = 0 and REG_EBANK_POS = 1
7.3.3.4.6 Address Mapping when REG_IBANK_POS = 1 and REG_EBANK_POS = 1
7.3.3.4.7 Address Mapping when REG_IBANK_POS = 2 and REG_EBANK_POS = 1
7.3.3.4.8 Address Mapping when REG_IBANK_POS = 3 and REG_EBANK_POS = 1
7.3.3.5 Performance Management
7.3.3.5.1 Command Ordering and Scheduling
7.3.3.5.2 Command Starvation
7.3.3.5.3 Possible Race Condition
7.3.3.5.4 Class of Service (COS)
7.3.3.5.5 Refresh Scheduling
7.3.3.6 DDR3 Read-Write Leveling
7.3.3.7 PRCM Sequence for DDR2/3/mDDR Memory controller
7.3.3.8 Interrupt Support
7.3.3.9 EDMA Event Support
7.3.3.10 Emulation Considerations
7.3.3.11 Power Management
7.3.3.11.1 Clock Stop Mode
7.3.3.11.2 Self-Refresh Mode
7.3.3.11.3 Power Down Mode
7.3.3.11.4 Deep Power-Down Mode
7.3.3.11.5 Save and Restore Mode
7.3.3.11.6 EMIF PHY Clock Gating
7.3.4 Use Cases
7.3.5 EMIF4D Registers
7.3.5.1 EMIF_MOD_ID_REV Register (offset = 0h) [reset = 40440C03h]
7.3.5.2 STATUS Register (offset = 4h) [reset = 0h]
7.3.5.3 SDRAM_CONFIG Register (offset = 8h) [reset = 0h]
7.3.5.4 SDRAM_CONFIG_2 Register (offset = Ch) [reset = 0h]
7.3.5.5 SDRAM_REF_CTRL Register (offset = 10h) [reset = 0h]
7.3.5.6 SDRAM_REF_CTRL_SHDW Register (offset = 14h) [reset = 0h]
7.3.5.7 SDRAM_TIM_1 Register (offset = 18h) [reset = 0h]
7.3.5.8 SDRAM_TIM_1_SHDW Register (offset = 1Ch) [reset = 0h]
7.3.5.9 SDRAM_TIM_2 Register (offset = 20h) [reset = 0h]
7.3.5.10 SDRAM_TIM_2_SHDW Register (offset = 24h) [reset = 0h]
7.3.5.11 SDRAM_TIM_3 Register (offset = 28h) [reset = 0h]
7.3.5.12 SDRAM_TIM_3_SHDW Register (offset = 2Ch) [reset = 0h]
7.3.5.13 PWR_MGMT_CTRL Register (offset = 38h) [reset = 0h]
7.3.5.14 PWR_MGMT_CTRL_SHDW Register (offset = 3Ch) [reset = 0h]
7.3.5.15 PERF_CNT_1 Register (offset = 80h) [reset = 0h]
7.3.5.16 PERF_CNT_2 Register (offset = 84h) [reset = 0h]
7.3.5.17 PERF_CNT_CFG Register (offset = 88h) [reset = 10000h]
7.3.5.18 PERF_CNT_SEL Register (offset = 8Ch) [reset = 0h]
7.3.5.19 PERF_CNT_TIM Register (offset = 90h) [reset = 0h]
7.3.5.20 READ_IDLE_CTRL Register (offset = 98h) [reset = 50000h]
7.3.5.21 READ_IDLE_CTRL_SHDW Register (offset = 9Ch) [reset = 50000h]
7.3.5.22 IRQSTATUS_RAW_SYS Register (offset = A4h) [reset = 0h]
7.3.5.23 IRQSTATUS_SYS Register (offset = ACh) [reset = 0h]
7.3.5.24 IRQENABLE_SET_SYS Register (offset = B4h) [reset = 0h]
7.3.5.25 IRQENABLE_CLR_SYS Register (offset = BCh) [reset = 0h]
7.3.5.26 ZQ_CONFIG Register (offset = C8h) [reset = 0h]
7.3.5.27 RDWR_LVL_RMP_WIN Register (offset = D4h) [reset = 0h]
7.3.5.28 RDWR_LVL_RMP_CTRL Register (offset = D8h) [reset = 0h]
7.3.5.29 RDWR_LVL_CTRL Register (offset = DCh) [reset = 0h]
7.3.5.30 DDR_PHY_CTRL_1 Register (offset = E4h) [reset = 0h]
7.3.5.31 DDR_PHY_CTRL_1_SHDW Register (offset = E8h) [reset = 0h]
7.3.5.32 PRI_COS_MAP Register (offset = 100h) [reset = 0h]
7.3.5.33 CONNID_COS_1_MAP Register (offset = 104h) [reset = 0h]
7.3.5.34 CONNID_COS_2_MAP Register (offset = 108h) [reset = 0h]
7.3.5.35 RD_WR_EXEC_THRSH Register (offset = 120h) [reset = 0h]
7.3.6 DDR2/3/mDDR PHY Registers
7.3.6.1 DDR PHY Command 0/1/2 Address/Command Slave Ratio Register (CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0)
7.3.6.2 DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register( CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0)
7.3.6.3 DDR PHY Command 0/1/2 Invert Clockout Selection Register( CMD0/1/2_REG_PHY_INVERT_CLKOUT_0)
7.3.6.4 DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register (DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)
7.3.6.5 DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register (DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0)
7.3.6.6 DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register ( DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0)
7.3.6.7 DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register (DATA0/1_REG_PHY_WRLVL_INIT_MODE_0)
7.3.6.8 DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register (DATA0_REG_PHY_GATELVL_INIT_RATIO_0)
7.3.6.9 DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register (DATA0/1_REG_PHY_GATELVL_INIT_MODE_0)
7.3.6.10 DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register (DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0)
7.3.6.11 DDR PHY Data Macro 0/1 Write Data Slave Ratio Register (DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0)
7.3.6.12 DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
7.4 ELM
7.4.1 Introduction
7.4.1.1 ELM Features
7.4.1.2 Unsupported ELM Features
7.4.2 Integration
7.4.2.1 ELM Connectivity Attributes
7.4.2.2 ELM Clock and Reset Management
7.4.2.3 ELM Pin List
7.4.3 Functional Description
7.4.3.1 ELM Software Reset
7.4.3.2 ELM Power Management
7.4.3.3 ELM Interrupt Requests
7.4.3.4 Processing Initialization
7.4.3.5 Processing Sequence
7.4.3.6 Processing Completion
7.4.4 Basic Programming Model
7.4.4.1 ELM Low Level Programming Model
7.4.4.1.1 Processing Initialization
7.4.4.1.2 Read Results
7.4.4.2 Use Case: ELM Used in Continuous Mode
7.4.4.3 Use Case: ELM Used in Page Mode
7.4.5 ELM Registers
7.4.5.1 ELM Revision Register (ELM_REVISION)
7.4.5.2 ELM System Configuration Register (ELM_SYSCONFIG)
7.4.5.3 ELM System Status Register (ELM_SYSSTATUS)
7.4.5.4 ELM Interrupt Status Register (ELM_IRQSTATUS)
7.4.5.5 ELM Interrupt Enable Register (ELM_IRQENABLE)
7.4.5.6 ELM Location Configuration Register (ELM_LOCATION_CONFIG)
7.4.5.7 ELM Page Definition Register (ELM_PAGE_CTRL)
7.4.5.8 ELM_SYNDROME_FRAGMENT_0_i Register
7.4.5.9 ELM_SYNDROME_FRAGMENT_1_i Register
7.4.5.10 ELM_SYNDROME_FRAGMENT_2_i Register
7.4.5.11 ELM_SYNDROME_FRAGMENT_3_i Register
7.4.5.12 ELM_SYNDROME_FRAGMENT_4_i Register
7.4.5.13 ELM_SYNDROME_FRAGMENT_5_i Register
7.4.5.14 ELM_SYNDROME_FRAGMENT_6_i Register
7.4.5.15 ELM_LOCATION_STATUS_i Register
7.4.5.16 ELM_ERROR_LOCATION_0-15_i Registers
8 Power, Reset, and Clock Management (PRCM)
8.1 Power, Reset, and Clock Management
8.1.1 Introduction
8.1.2 Device Power-Management Architecture Building Blocks
8.1.3 Clock Management
8.1.3.1 Module Interface and Functional Clocks
8.1.3.2 Module-Level Clock Management
8.1.3.2.1 Master Standby Protocol
8.1.3.2.2 Slave Idle Protocol
8.1.3.3 Clock Domain
8.1.3.3.1 Clock Domain-Level Clock Management
8.1.4 Power Management
8.1.4.1 Power Domain
8.1.4.2 Power Domain Management
8.1.4.2.1 Power-Management Techniques
8.1.4.3 Power Modes
8.1.4.3.1 Active
8.1.4.3.2 Standby
8.1.4.3.3 Deepsleep0
8.1.4.3.4 Deepsleep1
8.1.4.3.5 Deepsleep2
8.1.4.3.6 RTC-Only
8.1.4.4 Main Oscillator Control During Deep Sleep
8.1.4.5 Wakeup Sources/Events
8.1.4.6 Functional Sequencing for Power Management with Cortex M3
8.1.4.6.1 Periodic Idling of Cortex A8 MPU
8.1.4.6.2 Sleep Sequencing
8.1.4.6.3 Wakeup Sequencing
8.1.5 PRCM Module Overview
8.1.5.1 Interface Descriptions
8.1.5.1.1 OCP Interfaces
8.1.5.1.2 OCP Slave Interfaces
8.1.5.1.3 Power Control Interface
8.1.5.1.4 Device Control Interface
8.1.5.1.5 Clocks Interface
8.1.5.1.6 Resets Interface
8.1.5.1.7 Modules Power Management Control Interface
8.1.5.1.8 Initiator Modules Interface
8.1.5.1.9 Targets Modules Interface
8.1.6 Clock Generation and Management
8.1.6.1 Terminology
8.1.6.2 Clock Structure
8.1.6.3 ADPLLS
8.1.6.3.1 Clock Functions
8.1.6.4 ADPLLLJ (Low Jitter DPLL)
8.1.6.4.1 Clock Functions
8.1.6.5 M2 and N2 Change On-the-Fly
8.1.6.6 Core PLL Description
8.1.6.6.1 Core PLL Configuration
8.1.6.7 Peripheral PLL Description
8.1.6.7.1 Configuring the Peripheral PLL
8.1.6.8 MPU PLL Description
8.1.6.8.1 Configuring the MPU PLL
8.1.6.9 Display PLL Description
8.1.6.9.1 Configuring the Display PLL
8.1.6.10 DDR PLL Description
8.1.6.10.1 Configuring the DDR PLL
8.1.6.11 CLKOUT Signals
8.1.6.12 Timer Clock Structure
8.1.7 Reset Management
8.1.7.1 Overview
8.1.7.2 Reset Concepts and Definitions
8.1.7.3 Global Power On Reset (Cold Reset)
8.1.7.3.1 Power On Reset (PORz)
8.1.7.3.2 PORz Sequence
8.1.7.3.3 Bad Device Reset
8.1.7.3.4 Global Cold Software Reset (GLOBAL_COLD_SW_RST)
8.1.7.4 Global Warm Reset
8.1.7.4.1 External Warm Reset
8.1.7.4.2 Watchdog Timer
8.1.7.4.3 Global Warm Software Reset (GLOBAL_SW_WARM_RST)
8.1.7.4.4 Test Reset (TRSTz)
8.1.7.5 Reset Characteristics
8.1.7.6 EMAC Switch Reset Isolation
8.1.7.7 Reset Priority
8.1.7.8 Trace Functionality Across Reset
8.1.7.9 RTC PORz
8.1.8 Power-Up/Down Sequence
8.1.9 IO State
8.1.10 Voltage and Power Domains
8.1.10.1 Voltage Domains
8.1.10.2 Power Domains
8.1.11 Device Modules and Power Management Attributes List
8.1.11.1 Power Domain Power Down Sequence
8.1.11.2 Power Domain Power-Up Sequence
8.1.12 Clock Module Registers
8.1.12.1 CM_PER Registers
8.1.12.1.1 CM_PER_L4LS_CLKSTCTRL Register (offset = 0h) [reset = C0102h]
8.1.12.1.2 CM_PER_L3S_CLKSTCTRL Register (offset = 4h) [reset = Ah]
8.1.12.1.3 CM_PER_L3_CLKSTCTRL Register (offset = Ch) [reset = 12h]
8.1.12.1.4 CM_PER_CPGMAC0_CLKCTRL Register (offset = 14h) [reset = 70000h]
8.1.12.1.5 CM_PER_LCDC_CLKCTRL Register (offset = 18h) [reset = 70000h]
8.1.12.1.6 CM_PER_USB0_CLKCTRL Register (offset = 1Ch) [reset = 70000h]
8.1.12.1.7 CM_PER_TPTC0_CLKCTRL Register (offset = 24h) [reset = 70000h]
8.1.12.1.8 CM_PER_EMIF_CLKCTRL Register (offset = 28h) [reset = 30000h]
8.1.12.1.9 CM_PER_OCMCRAM_CLKCTRL Register (offset = 2Ch) [reset = 30000h]
8.1.12.1.10 CM_PER_GPMC_CLKCTRL Register (offset = 30h) [reset = 30002h]
8.1.12.1.11 CM_PER_MCASP0_CLKCTRL Register (offset = 34h) [reset = 30000h]
8.1.12.1.12 CM_PER_UART5_CLKCTRL Register (offset = 38h) [reset = 30000h]
8.1.12.1.13 CM_PER_MMC0_CLKCTRL Register (offset = 3Ch) [reset = 30000h]
8.1.12.1.14 CM_PER_ELM_CLKCTRL Register (offset = 40h) [reset = 30000h]
8.1.12.1.15 CM_PER_I2C2_CLKCTRL Register (offset = 44h) [reset = 30000h]
8.1.12.1.16 CM_PER_I2C1_CLKCTRL Register (offset = 48h) [reset = 30000h]
8.1.12.1.17 CM_PER_SPI0_CLKCTRL Register (offset = 4Ch) [reset = 30000h]
8.1.12.1.18 CM_PER_SPI1_CLKCTRL Register (offset = 50h) [reset = 30000h]
8.1.12.1.19 CM_PER_L4LS_CLKCTRL Register (offset = 60h) [reset = 2h]
8.1.12.1.20 CM_PER_L4FW_CLKCTRL Register (offset = 64h) [reset = 2h]
8.1.12.1.21 CM_PER_MCASP1_CLKCTRL Register (offset = 68h) [reset = 30000h]
8.1.12.1.22 CM_PER_UART1_CLKCTRL Register (offset = 6Ch) [reset = 30000h]
8.1.12.1.23 CM_PER_UART2_CLKCTRL Register (offset = 70h) [reset = 30000h]
8.1.12.1.24 CM_PER_UART3_CLKCTRL Register (offset = 74h) [reset = 30000h]
8.1.12.1.25 CM_PER_UART4_CLKCTRL Register (offset = 78h) [reset = 30000h]
8.1.12.1.26 CM_PER_TIMER7_CLKCTRL Register (offset = 7Ch) [reset = 30000h]
8.1.12.1.27 CM_PER_TIMER2_CLKCTRL Register (offset = 80h) [reset = 30000h]
8.1.12.1.28 CM_PER_TIMER3_CLKCTRL Register (offset = 84h) [reset = 30000h]
8.1.12.1.29 CM_PER_TIMER4_CLKCTRL Register (offset = 88h) [reset = 30000h]
8.1.12.1.30 CM_PER_GPIO1_CLKCTRL Register (offset = ACh) [reset = 30000h]
8.1.12.1.31 CM_PER_GPIO2_CLKCTRL Register (offset = B0h) [reset = 30000h]
8.1.12.1.32 CM_PER_GPIO3_CLKCTRL Register (offset = B4h) [reset = 30000h]
8.1.12.1.33 CM_PER_TPCC_CLKCTRL Register (offset = BCh) [reset = 30000h]
8.1.12.1.34 CM_PER_DCAN0_CLKCTRL Register (offset = C0h) [reset = 30000h]
8.1.12.1.35 CM_PER_DCAN1_CLKCTRL Register (offset = C4h) [reset = 30000h]
8.1.12.1.36 CM_PER_EPWMSS1_CLKCTRL Register (offset = CCh) [reset = 30000h]
8.1.12.1.37 CM_PER_EPWMSS0_CLKCTRL Register (offset = D4h) [reset = 30000h]
8.1.12.1.38 CM_PER_EPWMSS2_CLKCTRL Register (offset = D8h) [reset = 30000h]
8.1.12.1.39 CM_PER_L3_INSTR_CLKCTRL Register (offset = DCh) [reset = 2h]
8.1.12.1.40 CM_PER_L3_CLKCTRL Register (offset = E0h) [reset = 2h]
8.1.12.1.41 CM_PER_IEEE5000_CLKCTRL Register (offset = E4h) [reset = 70002h]
8.1.12.1.42 CM_PER_PRU_ICSS_CLKCTRL Register (offset = E8h) [reset = 70000h]
8.1.12.1.43 CM_PER_TIMER5_CLKCTRL Register (offset = ECh) [reset = 30000h]
8.1.12.1.44 CM_PER_TIMER6_CLKCTRL Register (offset = F0h) [reset = 30000h]
8.1.12.1.45 CM_PER_MMC1_CLKCTRL Register (offset = F4h) [reset = 30000h]
8.1.12.1.46 CM_PER_MMC2_CLKCTRL Register (offset = F8h) [reset = 30000h]
8.1.12.1.47 CM_PER_TPTC1_CLKCTRL Register (offset = FCh) [reset = 70000h]
8.1.12.1.48 CM_PER_TPTC2_CLKCTRL Register (offset = 100h) [reset = 70000h]
8.1.12.1.49 CM_PER_SPINLOCK_CLKCTRL Register (offset = 10Ch) [reset = 30000h]
8.1.12.1.50 CM_PER_MAILBOX0_CLKCTRL Register (offset = 110h) [reset = 30000h]
8.1.12.1.51 CM_PER_L4HS_CLKSTCTRL Register (offset = 11Ch) [reset = 7Ah]
8.1.12.1.52 CM_PER_L4HS_CLKCTRL Register (offset = 120h) [reset = 2h]
8.1.12.1.53 CM_PER_OCPWP_L3_CLKSTCTRL Register (offset = 12Ch) [reset = 2h]
8.1.12.1.54 CM_PER_OCPWP_CLKCTRL Register (offset = 130h) [reset = 70002h]
8.1.12.1.55 CM_PER_PRU_ICSS_CLKSTCTRL Register (offset = 140h) [reset = 2h]
8.1.12.1.56 CM_PER_CPSW_CLKSTCTRL Register (offset = 144h) [reset = 2h]
8.1.12.1.57 CM_PER_LCDC_CLKSTCTRL Register (offset = 148h) [reset = 2h]
8.1.12.1.58 CM_PER_CLKDIV32K_CLKCTRL Register (offset = 14Ch) [reset = 30000h]
8.1.12.1.59 CM_PER_CLK_24MHZ_CLKSTCTRL Register (offset = 150h) [reset = 2h]
8.1.12.2 CM_WKUP Registers
8.1.12.2.1 CM_WKUP_CLKSTCTRL Register (offset = 0h) [reset = 6h]
8.1.12.2.2 CM_WKUP_CONTROL_CLKCTRL Register (offset = 4h) [reset = 30000h]
8.1.12.2.3 CM_WKUP_GPIO0_CLKCTRL Register (offset = 8h) [reset = 30000h]
8.1.12.2.4 CM_WKUP_L4WKUP_CLKCTRL Register (offset = Ch) [reset = 2h]
8.1.12.2.5 CM_WKUP_TIMER0_CLKCTRL Register (offset = 10h) [reset = 30002h]
8.1.12.2.6 CM_WKUP_DEBUGSS_CLKCTRL Register (offset = 14h) [reset = 52580002h]
8.1.12.2.7 CM_L3_AON_CLKSTCTRL Register (offset = 18h) [reset = 1Ah]
8.1.12.2.8 CM_AUTOIDLE_DPLL_MPU Register (offset = 1Ch) [reset = 0h]
8.1.12.2.9 CM_IDLEST_DPLL_MPU Register (offset = 20h) [reset = 0h]
8.1.12.2.10 CM_SSC_DELTAMSTEP_DPLL_MPU Register (offset = 24h) [reset = 0h]
8.1.12.2.11 CM_SSC_MODFREQDIV_DPLL_MPU Register (offset = 28h) [reset = 0h]
8.1.12.2.12 CM_CLKSEL_DPLL_MPU Register (offset = 2Ch) [reset = 0h]
8.1.12.2.13 CM_AUTOIDLE_DPLL_DDR Register (offset = 30h) [reset = 0h]
8.1.12.2.14 CM_IDLEST_DPLL_DDR Register (offset = 34h) [reset = 0h]
8.1.12.2.15 CM_SSC_DELTAMSTEP_DPLL_DDR Register (offset = 38h) [reset = 0h]
8.1.12.2.16 CM_SSC_MODFREQDIV_DPLL_DDR Register (offset = 3Ch) [reset = 0h]
8.1.12.2.17 CM_CLKSEL_DPLL_DDR Register (offset = 40h) [reset = 0h]
8.1.12.2.18 CM_AUTOIDLE_DPLL_DISP Register (offset = 44h) [reset = 0h]
8.1.12.2.19 CM_IDLEST_DPLL_DISP Register (offset = 48h) [reset = 0h]
8.1.12.2.20 CM_SSC_DELTAMSTEP_DPLL_DISP Register (offset = 4Ch) [reset = 0h]
8.1.12.2.21 CM_SSC_MODFREQDIV_DPLL_DISP Register (offset = 50h) [reset = 0h]
8.1.12.2.22 CM_CLKSEL_DPLL_DISP Register (offset = 54h) [reset = 0h]
8.1.12.2.23 CM_AUTOIDLE_DPLL_CORE Register (offset = 58h) [reset = 0h]
8.1.12.2.24 CM_IDLEST_DPLL_CORE Register (offset = 5Ch) [reset = 0h]
8.1.12.2.25 CM_SSC_DELTAMSTEP_DPLL_CORE Register (offset = 60h) [reset = 0h]
8.1.12.2.26 CM_SSC_MODFREQDIV_DPLL_CORE Register (offset = 64h) [reset = 0h]
8.1.12.2.27 CM_CLKSEL_DPLL_CORE Register (offset = 68h) [reset = 0h]
8.1.12.2.28 CM_AUTOIDLE_DPLL_PER Register (offset = 6Ch) [reset = 0h]
8.1.12.2.29 CM_IDLEST_DPLL_PER Register (offset = 70h) [reset = 0h]
8.1.12.2.30 CM_SSC_DELTAMSTEP_DPLL_PER Register (offset = 74h) [reset = 0h]
8.1.12.2.31 CM_SSC_MODFREQDIV_DPLL_PER Register (offset = 78h) [reset = 0h]
8.1.12.2.32 CM_CLKDCOLDO_DPLL_PER Register (offset = 7Ch) [reset = 0h]
8.1.12.2.33 CM_DIV_M4_DPLL_CORE Register (offset = 80h) [reset = 4h]
8.1.12.2.34 CM_DIV_M5_DPLL_CORE Register (offset = 84h) [reset = 4h]
8.1.12.2.35 CM_CLKMODE_DPLL_MPU Register (offset = 88h) [reset = 4h]
8.1.12.2.36 CM_CLKMODE_DPLL_PER Register (offset = 8Ch) [reset = 4h]
8.1.12.2.37 CM_CLKMODE_DPLL_CORE Register (offset = 90h) [reset = 4h]
8.1.12.2.38 CM_CLKMODE_DPLL_DDR Register (offset = 94h) [reset = 4h]
8.1.12.2.39 CM_CLKMODE_DPLL_DISP Register (offset = 98h) [reset = 4h]
8.1.12.2.40 CM_CLKSEL_DPLL_PERIPH Register (offset = 9Ch) [reset = 0h]
8.1.12.2.41 CM_DIV_M2_DPLL_DDR Register (offset = A0h) [reset = 1h]
8.1.12.2.42 CM_DIV_M2_DPLL_DISP Register (offset = A4h) [reset = 1h]
8.1.12.2.43 CM_DIV_M2_DPLL_MPU Register (offset = A8h) [reset = 1h]
8.1.12.2.44 CM_DIV_M2_DPLL_PER Register (offset = ACh) [reset = 1h]
8.1.12.2.45 CM_WKUP_WKUP_M3_CLKCTRL Register (offset = B0h) [reset = 2h]
8.1.12.2.46 CM_WKUP_UART0_CLKCTRL Register (offset = B4h) [reset = 30000h]
8.1.12.2.47 CM_WKUP_I2C0_CLKCTRL Register (offset = B8h) [reset = 30000h]
8.1.12.2.48 CM_WKUP_ADC_TSC_CLKCTRL Register (offset = BCh) [reset = 30000h]
8.1.12.2.49 CM_WKUP_SMARTREFLEX0_CLKCTRL Register (offset = C0h) [reset = 30000h]
8.1.12.2.50 CM_WKUP_TIMER1_CLKCTRL Register (offset = C4h) [reset = 30000h]
8.1.12.2.51 CM_WKUP_SMARTREFLEX1_CLKCTRL Register (offset = C8h) [reset = 30000h]
8.1.12.2.52 CM_L4_WKUP_AON_CLKSTCTRL Register (offset = CCh) [reset = 6h]
8.1.12.2.53 CM_WKUP_WDT1_CLKCTRL Register (offset = D4h) [reset = 30002h]
8.1.12.2.54 CM_DIV_M6_DPLL_CORE Register (offset = D8h) [reset = 4h]
8.1.12.3 CM_DPLL Registers
8.1.12.3.1 CLKSEL_TIMER7_CLK Register (offset = 4h) [reset = 1h]
8.1.12.3.2 CLKSEL_TIMER2_CLK Register (offset = 8h) [reset = 1h]
8.1.12.3.3 CLKSEL_TIMER3_CLK Register (offset = Ch) [reset = 1h]
8.1.12.3.4 CLKSEL_TIMER4_CLK Register (offset = 10h) [reset = 1h]
8.1.12.3.5 CM_MAC_CLKSEL Register (offset = 14h) [reset = 4h]
8.1.12.3.6 CLKSEL_TIMER5_CLK Register (offset = 18h) [reset = 1h]
8.1.12.3.7 CLKSEL_TIMER6_CLK Register (offset = 1Ch) [reset = 1h]
8.1.12.3.8 CM_CPTS_RFT_CLKSEL Register (offset = 20h) [reset = 0h]
8.1.12.3.9 CLKSEL_TIMER1MS_CLK Register (offset = 28h) [reset = 0h]
8.1.12.3.10 CLKSEL_GFX_FCLK Register (offset = 2Ch) [reset = 0h]
8.1.12.3.11 CLKSEL_PRU_ICSS_OCP_CLK Register (offset = 30h) [reset = 0h]
8.1.12.3.12 CLKSEL_LCDC_PIXEL_CLK Register (offset = 34h) [reset = 0h]
8.1.12.3.13 CLKSEL_WDT1_CLK Register (offset = 38h) [reset = 1h]
8.1.12.3.14 CLKSEL_GPIO0_DBCLK Register (offset = 3Ch) [reset = 0h]
8.1.12.4 CM_MPU Registers
8.1.12.4.1 CM_MPU_CLKSTCTRL Register (offset = 0h) [reset = 6h]
8.1.12.4.2 CM_MPU_MPU_CLKCTRL Register (offset = 4h) [reset = 2h]
8.1.12.5 CM_DEVICE Registers
8.1.12.5.1 CM_CLKOUT_CTRL Register (offset = 0h) [reset = 0h]
8.1.12.6 CM_RTC Registers
8.1.12.6.1 CM_RTC_RTC_CLKCTRL Register (offset = 0h) [reset = 30002h]
8.1.12.6.2 CM_RTC_CLKSTCTRL Register (offset = 4h) [reset = 102h]
8.1.12.7 CM_GFX Registers
8.1.12.7.1 CM_GFX_L3_CLKSTCTRL Register (offset = 0h) [reset = 2h]
8.1.12.7.2 CM_GFX_GFX_CLKCTRL Register (offset = 4h) [reset = 70000h]
8.1.12.7.3 CM_GFX_L4LS_GFX_CLKSTCTRL Register (offset = Ch) [reset = 102h]
8.1.12.7.4 CM_GFX_MMUCFG_CLKCTRL Register (offset = 10h) [reset = 30000h]
8.1.12.7.5 CM_GFX_MMUDATA_CLKCTRL Register (offset = 14h) [reset = 30000h]
8.1.12.8 CM_CEFUSE Registers
8.1.12.8.1 CM_CEFUSE_CLKSTCTRL Register (offset = 0h) [reset = 2h]
8.1.12.8.2 CM_CEFUSE_CEFUSE_CLKCTRL Register (offset = 20h) [reset = 30000h]
8.1.13 Power Management Registers
8.1.13.1 PRM_IRQ Registers
8.1.13.1.1 REVISION_PRM Register (offset = 0h) [reset = 0h]
8.1.13.1.2 PRM_IRQSTATUS_MPU Register (offset = 4h) [reset = 0h]
8.1.13.1.3 PRM_IRQENABLE_MPU Register (offset = 8h) [reset = 0h]
8.1.13.1.4 PRM_IRQSTATUS_M3 Register (offset = Ch) [reset = 0h]
8.1.13.1.5 PRM_IRQENABLE_M3 Register (offset = 10h) [reset = 0h]
8.1.13.2 PRM_PER Registers
8.1.13.2.1 RM_PER_RSTCTRL Register (offset = 0h) [reset = 2h]
8.1.13.2.2 PM_PER_PWRSTST Register (offset = 8h) [reset = 1E60007h]
8.1.13.2.3 PM_PER_PWRSTCTRL Register (offset = Ch) [reset = EE0000EBh]
8.1.13.3 PRM_WKUP Registers
8.1.13.3.1 RM_WKUP_RSTCTRL Register (offset = 0h) [reset = 8h]
8.1.13.3.2 PM_WKUP_PWRSTCTRL Register (offset = 4h) [reset = 8h]
8.1.13.3.3 PM_WKUP_PWRSTST Register (offset = 8h) [reset = 60004h]
8.1.13.3.4 RM_WKUP_RSTST Register (offset = Ch) [reset = 0h]
8.1.13.4 PRM_MPU Registers
8.1.13.4.1 PM_MPU_PWRSTCTRL Register (offset = 0h) [reset = 1FF0007h]
8.1.13.4.2 PM_MPU_PWRSTST Register (offset = 4h) [reset = 157h]
8.1.13.4.3 RM_MPU_RSTST Register (offset = 8h) [reset = 0h]
8.1.13.5 PRM_DEVICE Registers
8.1.13.5.1 PRM_RSTCTRL Register (offset = 0h) [reset = 0h]
8.1.13.5.2 PRM_RSTTIME Register (offset = 4h) [reset = 1006h]
8.1.13.5.3 PRM_RSTST Register (offset = 8h) [reset = 1h]
8.1.13.5.4 PRM_SRAM_COUNT Register (offset = Ch) [reset = 78000017h]
8.1.13.5.5 PRM_LDO_SRAM_CORE_SETUP Register (offset = 10h) [reset = 0h]
8.1.13.5.6 PRM_LDO_SRAM_CORE_CTRL Register (offset = 14h) [reset = 0h]
8.1.13.5.7 PRM_LDO_SRAM_MPU_SETUP Register (offset = 18h) [reset = 0h]
8.1.13.5.8 PRM_LDO_SRAM_MPU_CTRL Register (offset = 1Ch) [reset = 0h]
8.1.13.6 PRM_RTC Registers
8.1.13.6.1 PM_RTC_PWRSTCTRL Register (offset = 0h) [reset = 4h]
8.1.13.6.2 PM_RTC_PWRSTST Register (offset = 4h) [reset = 4h]
8.1.13.7 PRM_GFX Registers
8.1.13.7.1 PM_GFX_PWRSTCTRL Register (offset = 0h) [reset = 60044h]
8.1.13.7.2 RM_GFX_RSTCTRL Register (offset = 4h) [reset = 1h]
8.1.13.7.3 PM_GFX_PWRSTST Register (offset = 10h) [reset = 17h]
8.1.13.7.4 RM_GFX_RSTST Register (offset = 14h) [reset = 0h]
8.1.13.8 PRM_CEFUSE Registers
8.1.13.8.1 PM_CEFUSE_PWRSTCTRL Register (offset = 0h) [reset = 0h]
8.1.13.8.2 PM_CEFUSE_PWRSTST Register (offset = 4h) [reset = 7h]
9 Control Module
9.1 Introduction
9.2 Functional Description
9.2.1 Control Module Initialization
9.2.2 Pad Control Registers
9.2.2.1 Mode Selection
9.2.2.2 Pull Selection
9.2.3 EDMA Event Multiplexing
9.2.4 Device Control and Status
9.2.4.1 Control and Boot Status
9.2.4.2 Interprocessor Communication
9.2.4.3 Initiator Priority Control
9.2.4.3.1 Initiator Priority Control for Interconnect
9.2.4.3.2 Initiator Priority at EMIF
9.2.4.4 Peripheral Control and Status
9.2.4.4.1 USB Control and Status
9.2.4.4.2 USB Charger Detect
9.2.4.4.3 Ethernet MII Mode Selection
9.2.4.4.4 Ethernet Module Reset Isolation Control
9.2.4.4.5 Timer/eCAP Event Capture Control
9.2.4.4.6 ADC Capture Control
9.2.5 DDR PHY
9.2.5.1 DDR PHY to IO Pin Mapping
9.3 CONTROL_MODULE Registers
9.3.1 control_revision Register (offset = 0h) [reset = 0h]
9.3.2 device_id Register (offset = 600h) [reset = 0x]
9.3.3 control_hwinfo Register (offset = 4h) [reset = 0h]
9.3.4 control_sysconfig Register (offset = 10h) [reset = 0h]
9.3.5 control_status Register (offset = 40h) [reset = 0h]
9.3.6 cortex_vbbldo_ctrl Register (offset = 41Ch) [reset = 0h]
9.3.7 core_sldo_ctrl Register (offset = 428h) [reset = 0h]
9.3.8 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h]
9.3.9 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h]
9.3.10 bandgap_ctrl Register (offset = 448h) [reset = 0h]
9.3.11 bandgap_trim Register (offset = 44Ch) [reset = 0h]
9.3.12 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h]
9.3.13 mosc_ctrl Register (offset = 468h) [reset = 0h]
9.3.14 rcosc_ctrl Register (offset = 46Ch) [reset = 0h]
9.3.15 deepsleep_ctrl Register (offset = 470h) [reset = 0h]
9.3.16 dev_feature Register (offset = 604h) [reset = 0h]
9.3.17 init_priority_0 Register (offset = 608h) [reset = 0h]
9.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h]
9.3.19 mmu_cfg Register (offset = 610h) [reset = 0h]
9.3.20 tptc_cfg Register (offset = 614h) [reset = 0h]
9.3.21 usb_ctrl0 Register (offset = 620h) [reset = 0h]
9.3.22 usb_sts0 Register (offset = 624h) [reset = 0h]
9.3.23 usb_ctrl1 Register (offset = 628h) [reset = 0h]
9.3.24 usb_sts1 Register (offset = 62Ch) [reset = 0h]
9.3.25 mac_id0_lo Register (offset = 630h) [reset = 0h]
9.3.26 mac_id0_hi Register (offset = 634h) [reset = 0h]
9.3.27 mac_id1_lo Register (offset = 638h) [reset = 0h]
9.3.28 mac_id1_hi Register (offset = 63Ch) [reset = 0h]
9.3.29 dcan_raminit Register (offset = 644h) [reset = 0h]
9.3.30 usb_wkup_ctrl Register (offset = 648h) [reset = 0h]
9.3.31 gmii_sel Register (offset = 650h) [reset = 0h]
9.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h]
9.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h]
9.3.34 mreqprio_1 Register (offset = 674h) [reset = 0h]
9.3.35 hw_event_sel_grp1 Register (offset = 690h) [reset = 0h]
9.3.36 hw_event_sel_grp2 Register (offset = 694h) [reset = 0h]
9.3.37 hw_event_sel_grp3 Register (offset = 698h) [reset = 0h]
9.3.38 hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h]
9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h]
9.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h]
9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h]
9.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h]
9.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h]
9.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h]
9.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h]
9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h]
9.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h]
9.3.48 bb_scale Register (offset = 7D0h) [reset = 0h]
9.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h]
9.3.50 conf__ Register (offset = 800h)
9.3.51 cqdetect_status Register (offset = E00h) [reset = 0h]
9.3.52 ddr_io_ctrl Register (offset = E04h) [reset = 0h]
9.3.53 vtp_ctrl Register (offset = E0Ch) [reset = 0h]
9.3.54 vref_ctrl Register (offset = E14h) [reset = 0h]
9.3.55 tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h]
9.3.56 tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h]
9.3.57 tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h]
9.3.58 tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h]
9.3.59 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h]
9.3.60 tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h]
9.3.61 tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h]
9.3.62 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h]
9.3.63 tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h]
9.3.64 tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h]
9.3.65 tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h]
9.3.66 tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h]
9.3.67 tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h]
9.3.68 tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h]
9.3.69 tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h]
9.3.70 tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h]
9.3.71 timer_evt_capt Register (offset = FD0h) [reset = 0h]
9.3.72 ecap_evt_capt Register (offset = FD4h) [reset = 0h]
9.3.73 adc_evt_capt Register (offset = FD8h) [reset = 0h]
9.3.74 reset_iso Register (offset = 1000h) [reset = 0h]
9.3.75 ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h]
9.3.76 sma2 Register (offset = 1320h) [reset = 0h]
9.3.77 m3_txev_eoi Register (offset = 1324h) [reset = 0h]
9.3.78 ipc_msg_reg0 Register (offset = 1328h) [reset = 0h]
9.3.79 ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h]
9.3.80 ipc_msg_reg2 Register (offset = 1330h) [reset = 0h]
9.3.81 ipc_msg_reg3 Register (offset = 1334h) [reset = 0h]
9.3.82 ipc_msg_reg4 Register (offset = 1338h) [reset = 0h]
9.3.83 ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h]
9.3.84 ipc_msg_reg6 Register (offset = 1340h) [reset = 0h]
9.3.85 ipc_msg_reg7 Register (offset = 1344h) [reset = 0h]
9.3.86 ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h]
9.3.87 ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h]
9.3.88 ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h]
9.3.89 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h]
9.3.90 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h]
10 Interconnects
10.1 Introduction
10.1.1 Terminology
10.1.2 L3 Interconnect
10.1.2.1 L3 Topology
10.1.2.2 L3 Port Mapping
10.1.2.3 Interconnect Requirements
10.1.2.4 ConnID Assignment
10.1.3 L4 Interconnect
11 Enhanced Direct Memory Access (EDMA)
11.1 Introduction
11.1.1 EDMA3 Controller Block Diagram
11.1.2 Third-Party Channel Controller (TPCC) Overview
11.1.2.1 TPCC Features
11.1.2.2 Unsupported TPCC Features
11.1.3 Third-Party Transfer Controller (TPTC) Overview
11.1.3.1 TPTC Features
11.1.3.2 Unsupported TPTC Features
11.2 Integration
11.2.1 Third-Party Channel Controller (TPCC) Integration
11.2.1.1 TPCC Connectivity Attributes
11.2.1.2 TPCC Clock and Reset Management
11.2.1.3 TPCC Pin List
11.2.2 Third-Party Transfer Controller (TPTC) Integration
11.2.2.1 TPTC Connectivity Attributes
11.2.2.2 TPTC Clock and Reset Management
11.2.2.3 TPTC Pin List
11.3 Functional Description
11.3.1 Functional Overview
11.3.1.1 EDMA3 Channel Controller (EDMA3CC)
11.3.1.2 EDMA3 Transfer Controller (EDMA3TC)
11.3.2 Types of EDMA3 Transfers
11.3.2.1 A-Synchronized Transfers
11.3.2.2 AB-Synchronized Transfers
11.3.3 Parameter RAM (PaRAM)
11.3.3.1 PaRAM
11.3.3.2 EDMA3 Channel PaRAM Set Entry Fields
11.3.3.2.1 Channel Options Parameter (OPT)
11.3.3.2.2 Channel Source Address (SRC)
11.3.3.2.3 Channel Destination Address (DST)
11.3.3.2.4 Count for 1st Dimension (ACNT)
11.3.3.2.5 Count for 2nd Dimension (BCNT)
11.3.3.2.6 Count for 3rd Dimension (CCNT)
11.3.3.2.7 BCNT Reload (BCNTRLD)
11.3.3.2.8 Source B Index (SRCBIDX)
11.3.3.2.9 Destination B Index (DSTBIDX)
11.3.3.2.10 Source C Index (SRCCIDX)
11.3.3.2.11 Destination C Index (DSTCIDX)
11.3.3.2.12 Link Address (LINK)
11.3.3.3 Null PaRAM Set
11.3.3.4 Dummy PaRAM Set
11.3.3.5 Dummy Versus Null Transfer Comparison
11.3.3.6 Parameter Set Updates
11.3.3.7 Linking Transfers
11.3.3.8 Constant Addressing Mode Transfers/Alignment Issues
11.3.3.9 Element Size
11.3.4 Initiating a DMA Transfer
11.3.4.1 DMA Channel
11.3.4.1.1 Event-Triggered Transfer Request
11.3.4.1.2 Manually Triggered Transfer Request
11.3.4.1.3 Chain-Triggered Transfer Request
11.3.4.2 QDMA Channels
11.3.4.2.1 Auto-triggered and Link-Triggered Transfer Request
11.3.4.3 Comparison Between DMA and QDMA Channels
11.3.5 Completion of a DMA Transfer
11.3.5.1 Normal Completion
11.3.5.2 Early Completion
11.3.5.3 Dummy or Null Completion
11.3.6 Event, Channel, and PaRAM Mapping
11.3.6.1 DMA Channel to PaRAM Mapping
11.3.6.2 QDMA Channel to PaRAM Mapping
11.3.7 EDMA3 Channel Controller Regions
11.3.7.1 Region Overview
11.3.7.2 Channel Controller Regions
11.3.7.3 Region Interrupts
11.3.8 Chaining EDMA3 Channels
11.3.9 EDMA3 Interrupts
11.3.9.1 Transfer Completion Interrupts
11.3.9.1.1 Enabling Transfer Completion Interrupts
11.3.9.1.2 Clearing Transfer Completion Interrupts
11.3.9.2 EDMA3 Interrupt Servicing
11.3.9.3 Interrupt Evaluation Operations
11.3.9.4 Error Interrupts
11.3.10 Memory Protection
11.3.10.1 Active Memory Protection
11.3.10.2 Proxy Memory Protection
11.3.11 Event Queue(s)
11.3.11.1 DMA/QDMA Channel to Event Queue Mapping
11.3.11.2 Queue RAM Debug Visibility
11.3.11.3 Queue Resource Tracking
11.3.11.4 Performance Considerations
11.3.12 EDMA3 Transfer Controller (EDMA3TC)
11.3.12.1 Architecture Details
11.3.12.1.1 Command Fragmentation
11.3.12.1.2 TR Pipelining
11.3.12.1.3 Performance Tuning
11.3.12.2 Memory Protection
11.3.12.3 Error Generation
11.3.12.4 Debug Features
11.3.12.4.1 Destination FIFO Register Pointer
11.3.12.5 EDMA3TC Configuration
11.3.13 Event Dataflow
11.3.14 EDMA3 Prioritization
11.3.14.1 Channel Priority
11.3.14.2 Trigger Source Priority
11.3.14.3 Dequeue Priority
11.3.14.4 System (Transfer Controller) Priority
11.3.15 EDMA3 Operating Frequency (Clock Control)
11.3.16 Reset Considerations
11.3.17 Power Management
11.3.18 Emulation Considerations
11.3.19 EDMA Transfer Examples
11.3.19.1 Block Move Example
11.3.19.2 Subframe Extraction Example
11.3.19.3 Data Sorting Example
11.3.19.4 Peripheral Servicing Example
11.3.19.4.1 Non-bursting Peripherals
11.3.19.4.2 Bursting Peripherals
11.3.19.4.3 Continuous Operation
11.3.19.4.4 Ping-Pong Buffering
11.3.19.4.5 Transfer Chaining Examples
11.3.20 EDMA Events
11.4 EDMA3 Registers
11.4.1 EDMA3 Channel Controller Registers
11.4.1.1 Global Registers
11.4.1.1.1 Peripheral Identification Register (PID)
11.4.1.1.2 EDMA3CC Configuration Register (CCCFG)
11.4.1.1.3 EDMA3CC System Configuration Register (SYSCONFIG)
11.4.1.1.4 DMA Channel Map n Registers (DCHMAPn)
11.4.1.1.5 QDMA Channel Map n Registers (QCHMAPn)
11.4.1.1.6 DMA Channel Queue n Number Registers (DMAQNUMn)
11.4.1.1.7 QDMA Channel Queue Number Register (QDMAQNUM)
11.4.1.1.8 Queue Priority Register (QUEPRI)
11.4.1.2 Error Registers
11.4.1.2.1 Event Missed Registers (EMR/EMRH)
11.4.1.2.2 Event Missed Clear Registers (EMCR/EMCRH)
11.4.1.2.3 QDMA Event Missed Register (QEMR)
11.4.1.2.4 QDMA Event Missed Clear Register (QEMCR)
11.4.1.2.5 EDMA3CC Error Register (CCERR)
11.4.1.2.6 EDMA3CC Error Clear Register (CCERRCLR)
11.4.1.2.7 Error Evaluation Register (EEVAL)
11.4.1.3 Region Access Enable Registers
11.4.1.3.1 DMA Region Access Enable for Region m (DRAEm)
11.4.1.3.2 QDMA Region Access Enable Registers (QRAEm)
11.4.1.4 Status/Debug Visibility Registers
11.4.1.4.1 Event Queue Entry Registers (QxEy)
11.4.1.4.2 Queue Status Registers (QSTATn)
11.4.1.4.3 Queue Watermark Threshold A Register (QWMTHRA)
11.4.1.4.4 EDMA3CC Status Register (CCSTAT)
11.4.1.5 Memory Protection Address Space
11.4.1.5.1 Memory Protection Fault Address Register (MPFAR)
11.4.1.5.2 Memory Protection Fault Status Register (MPFSR)
11.4.1.5.3 Memory Protection Fault Command Register (MPFCR)
11.4.1.5.4 Memory Protection Page Attribute Register (MPPAn)
11.4.1.6 DMA Channel Registers
11.4.1.6.1 Event Registers (ER, ERH)
11.4.1.6.2 Event Clear Registers (ECR, ECRH)
11.4.1.6.3 Event Set Registers (ESR, ESRH)
11.4.1.6.4 Chained Event Registers (CER, CERH)
11.4.1.6.5 Event Enable Registers (EER, EERH)
11.4.1.6.6 Event Enable Clear Register (EECR, EECRH)
11.4.1.6.7 Event Enable Set Registers (EESR, EESRH)
11.4.1.6.8 Secondary Event Registers (SER, SERH)
11.4.1.6.9 Secondary Event Clear Registers (SECR, SECRH)
11.4.1.7 Interrupt Registers
11.4.1.7.1 Interrupt Enable Registers (IER, IERH)
11.4.1.7.2 Interrupt Enable Clear Register (IECR, IECRH)
11.4.1.7.3 Interrupt Enable Set Registers (IESR, IESRH)
11.4.1.7.4 Interrupt Pending Register (IPR, IPRH)
11.4.1.7.5 Interrupt Clear Registers (ICR, ICRH)
11.4.1.7.6 Interrupt Evaluate Register (IEVAL)
11.4.1.8 QDMA Registers
11.4.1.8.1 QDMA Event Register (QER)
11.4.1.8.2 QDMA Event Enable Register (QEER)
11.4.1.8.3 QDMA Event Enable Clear Register (QEECR)
11.4.1.8.4 QDMA Event Enable Set Register (QEESR)
11.4.1.8.5 QDMA Secondary Event Register (QSER)
11.4.1.8.6 QDMA Secondary Event Clear Register (QSECR)
11.4.2 EDMA3 Transfer Controller Registers
11.4.2.1 Peripheral Identification Register (PID)
11.4.2.2 EDMA3TC Configuration Register (TCCFG)
11.4.2.3 EDMA3TC Channel Status Register (TCSTAT)
11.4.2.4 Error Registers
11.4.2.4.1 Error Register (ERRSTAT)
11.4.2.4.2 Error Enable Register (ERREN)
11.4.2.4.3 Error Clear Register (ERRCLR)
11.4.2.4.4 Error Details Register (ERRDET)
11.4.2.4.5 Error Interrupt Command Register (ERRCMD)
11.4.2.5 Read Rate Register (RDRATE)
11.4.2.6 EDMA3TC Channel Registers
11.4.2.6.1 Source Active Options Register (SAOPT)
11.4.2.6.2 Source Active Source Address Register (SASRC)
11.4.2.6.3 Source Active Count Register (SACNT)
11.4.2.6.4 Source Active Destination Address Register (SADST)
11.4.2.6.5 Source Active Source B-Dimension Index Register (SABIDX)
11.4.2.6.6 Source Active Memory Protection Proxy Register (SAMPPRXY)
11.4.2.6.7 Source Active Count Reload Register (SACNTRLD)
11.4.2.6.8 Source Active Source Address B-Reference Register (SASRCBREF)
11.4.2.6.9 Source Active Destination Address B-Reference Register (SADSTBREF)
11.4.2.6.10 Destination FIFO Options Register (DFOPTn)
11.4.2.6.11 Destination FIFO Source Address Register (DFSRCn)
11.4.2.6.12 Destination FIFO Count Register (DFCNTn)
11.4.2.6.13 Destination FIFO Destination Address Register (DFDSTn)
11.4.2.6.14 Destination FIFO B-Index Register (DFBIDXn)
11.4.2.6.15 Destination FIFO Memory Protection Proxy Register (DFMPPRXYn)
11.4.2.6.16 Destination FIFO Count Reload Register (DFCNTRLDn)
11.4.2.6.17 Destination FIFO Source Address B-Reference Register (DFSRCBREFn)
11.4.2.6.18 Destination FIFO Destination Address B-Reference (DFDSTBREFn)
11.5 Appendix A
11.5.1 Debug Checklist
11.5.2 Miscellaneous Programming/Debug Tips
11.5.3 Setting Up a Transfer
12 Touchscreen Controller
12.1 Introduction
12.1.1 TSC_ADC Features
12.1.2 Unsupported TSC_ADC_SS Features
12.2 Integration
12.2.1 TSC_ADC Connectivity Attributes
12.2.2 TSC_ADC Clock and Reset Management
12.2.3 TSC_ADC Pin List
12.3 Functional Description
12.3.1 HW Synchronized or SW Channels
12.3.2 Open Delay and Sample Delay
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16)
12.3.4 One-Shot (Single) or Continuous Mode
12.3.5 Interrupts
12.3.6 DMA Requests
12.3.7 Analog Front End (AFE) Functional Block Diagram
12.4 Operational Modes
12.4.1 PenCtrl and PenIRQ
12.5 Touchscreen Controller Registers
12.5.1 TSC_ADC_SS Registers
12.5.1.1 REVISION Register (offset = 0h) [reset = 47300001h]
12.5.1.2 SYSCONFIG Register (offset = 10h) [reset = 0h]
12.5.1.3 IRQSTATUS_RAW Register (offset = 24h) [reset = 0h]
12.5.1.4 IRQSTATUS Register (offset = 28h) [reset = 0h]
12.5.1.5 IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
12.5.1.6 IRQENABLE_CLR Register (offset = 30h) [reset = 0h]
12.5.1.7 IRQWAKEUP Register (offset = 34h) [reset = 0h]
12.5.1.8 DMAENABLE_SET Register (offset = 38h) [reset = 0h]
12.5.1.9 DMAENABLE_CLR Register (offset = 3Ch) [reset = 0h]
12.5.1.10 CTRL Register (offset = 40h) [reset = 0h]
12.5.1.11 ADCSTAT Register (offset = 44h) [reset = 10h]
12.5.1.12 ADCRANGE Register (offset = 48h) [reset = 0h]
12.5.1.13 ADC_CLKDIV Register (offset = 4Ch) [reset = 0h]
12.5.1.14 ADC_MISC Register (offset = 50h) [reset = 0h]
12.5.1.15 STEPENABLE Register (offset = 54h) [reset = 0h]
12.5.1.16 IDLECONFIG Register (offset = 58h) [reset = 0h]
12.5.1.17 TS_CHARGE_STEPCONFIG Register (offset = 5Ch) [reset = 0h]
12.5.1.18 TS_CHARGE_DELAY Register (offset = 60h) [reset = 1h]
12.5.1.19 STEPCONFIG1 Register (offset = 64h) [reset = 0h]
12.5.1.20 STEPDELAY1 Register (offset = 68h) [reset = 0h]
12.5.1.21 STEPCONFIG2 Register (offset = 6Ch) [reset = 0h]
12.5.1.22 STEPDELAY2 Register (offset = 70h) [reset = 0h]
12.5.1.23 STEPCONFIG3 Register (offset = 74h) [reset = 0h]
12.5.1.24 STEPDELAY3 Register (offset = 78h) [reset = 0h]
12.5.1.25 STEPCONFIG4 Register (offset = 7Ch) [reset = 0h]
12.5.1.26 STEPDELAY4 Register (offset = 80h) [reset = 0h]
12.5.1.27 STEPCONFIG5 Register (offset = 84h) [reset = 0h]
12.5.1.28 STEPDELAY5 Register (offset = 88h) [reset = 0h]
12.5.1.29 STEPCONFIG6 Register (offset = 8Ch) [reset = 0h]
12.5.1.30 STEPDELAY6 Register (offset = 90h) [reset = 0h]
12.5.1.31 STEPCONFIG7 Register (offset = 94h) [reset = 0h]
12.5.1.32 STEPDELAY7 Register (offset = 98h) [reset = 0h]
12.5.1.33 STEPCONFIG8 Register (offset = 9Ch) [reset = 0h]
12.5.1.34 STEPDELAY8 Register (offset = A0h) [reset = 0h]
12.5.1.35 STEPCONFIG9 Register (offset = A4h) [reset = 0h]
12.5.1.36 STEPDELAY9 Register (offset = A8h) [reset = 0h]
12.5.1.37 STEPCONFIG10 Register (offset = ACh) [reset = 0h]
12.5.1.38 STEPDELAY10 Register (offset = B0h) [reset = 0h]
12.5.1.39 STEPCONFIG11 Register (offset = B4h) [reset = 0h]
12.5.1.40 STEPDELAY11 Register (offset = B8h) [reset = 0h]
12.5.1.41 STEPCONFIG12 Register (offset = BCh) [reset = 0h]
12.5.1.42 STEPDELAY12 Register (offset = C0h) [reset = 0h]
12.5.1.43 STEPCONFIG13 Register (offset = C4h) [reset = 0h]
12.5.1.44 STEPDELAY13 Register (offset = C8h) [reset = 0h]
12.5.1.45 STEPCONFIG14 Register (offset = CCh) [reset = 0h]
12.5.1.46 STEPDELAY14 Register (offset = D0h) [reset = 0h]
12.5.1.47 STEPCONFIG15 Register (offset = D4h) [reset = 0h]
12.5.1.48 STEPDELAY15 Register (offset = D8h) [reset = 0h]
12.5.1.49 STEPCONFIG16 Register (offset = DCh) [reset = 0h]
12.5.1.50 STEPDELAY16 Register (offset = E0h) [reset = 0h]
12.5.1.51 FIFO0COUNT Register (offset = E4h) [reset = 0h]
12.5.1.52 FIFO0THRESHOLD Register (offset = E8h) [reset = 0h]
12.5.1.53 DMA0REQ Register (offset = ECh) [reset = 0h]
12.5.1.54 FIFO1COUNT Register (offset = F0h) [reset = 0h]
12.5.1.55 FIFO1THRESHOLD Register (offset = F4h) [reset = 0h]
12.5.1.56 DMA1REQ Register (offset = F8h) [reset = 0h]
12.5.1.57 FIFO0DATA Register (offset = 100h) [reset = 0h]
12.5.1.58 FIFO1DATA Register (offset = 200h) [reset = 0h]
13 LCD Controller
13.1 Introduction
13.1.1 Purpose of the Peripheral
13.1.2 Features
13.2 Integration
13.2.1 LCD Controller Connectivity Attributes
13.2.2 LCD Controller Clock and Reset Management
13.2.3 LCD Controller Pin List
13.3 Functional Description
13.3.1 Clocking
13.3.1.1 Pixel Clock (LCD_PCLK)
13.3.1.2 Horizontal Clock (LCD_HSYNC)
13.3.1.3 Vertical Clock (LCD_VSYNC)
13.3.1.4 LCD_AC_BIAS_EN
13.3.2 LCD External I/O Signals
13.3.3 DMA Engine
13.3.3.1 Interrupts
13.3.3.1.1 LIDD Mode
13.3.3.1.2 Raster Mode
13.3.3.1.3 Interrupt Handling
13.3.4 LIDD Controller
13.3.5 Raster Controller
13.3.5.1 Logical Data Path
13.3.5.2 Frame Buffer
13.3.5.3 Palette
13.3.5.4 Gray-Scaler/Serializer
13.3.5.4.1 Passive (STN) Mode
13.3.5.4.2 Active (TFT) Mode
13.3.5.4.3 Summary of Color Depth
13.3.5.5 Output Format
13.3.5.5.1 Passive (STN) Mode
13.3.5.5.2 Active (TFT) Mode
13.3.5.6 Subpicture Feature
13.3.6 Interrupt Conditions
13.3.6.1 Highlander 0.8 Interrupts
13.3.6.1.1 Highlander Interrupt Basics
13.3.6.1.2 Raw Status Register
13.3.6.1.3 Masked Status Register
13.3.6.1.4 Interrupt Enable Set Register
13.3.6.1.5 Interrupt Enable Clear Register
13.3.6.1.6 End of Interrupt Register
13.3.6.2 Interrupt Sources
13.3.6.2.1 Overview of Interrupt Sources
13.3.7 DMA
13.3.8 Power Management
13.4 Programming Model
13.4.1 LCD Character Displays
13.4.1.1 Configuration Registers, Setup, and Settings
13.4.1.1.1 Configuration Registers
13.4.1.1.2 Defining Panel Commands and Panel Data
13.4.1.2 CPU Initiated Data Bus Transactions
13.4.1.2.1 Initiating Data Bus Transactions
13.4.1.3 DMA Initiated Data Bus Transactions for LIDD
13.4.1.3.1 DMA Overview for MPU Bus Output
13.4.1.3.2 MCU/LIDD DMA Setup: Example Pseudo Code
13.4.1.4 Passive Matrix
13.4.1.4.1 Monochrome Bitrate Awareness
13.4.2 Active Matrix Displays
13.4.2.1 Interfacing to Dual LVDS Transmitters
13.4.3 System Interaction
13.4.3.1 DMA End of Frame Interrupts
13.4.4 Palette Lookup
13.4.5 Test Logic
13.4.6 Disable and Software Reset Sequence
13.4.7 Precedence Order for Determining Frame Buffer Type
13.5 LCD Registers
13.5.1 PID Register (offset = 0h) [reset = 0h]
13.5.2 CTRL Register (offset = 4h) [reset = 0h]
13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h]
13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h]
13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h]
13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h]
13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h]
13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h]
13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h]
13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h]
13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h]
13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h]
13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h]
13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h]
13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h]
13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h]
13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h]
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h]
13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h]
13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h]
13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h]
13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h]
13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h]
13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h]
13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h]
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h]
13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h]
14 Ethernet Subsystem
14.1 Introduction
14.1.1 Features
14.1.2 Unsupported Features
14.2 Integration
14.2.1 Ethernet Switch Connectivity Attributes
14.2.2 Ethernet Switch Clock and Reset Management
14.2.3 Ethernet Switch Pin List
14.2.4 Ethernet Switch RMII Clocking Details
14.2.5 GMII Interface Signal Connections and Descriptions
14.2.5.1 GMII Interface Signal Descriptions in GIG (1000Mbps) Mode
14.2.5.2
14.2.6 RMII Signal Connections and Descriptions
14.2.7 RGMII Signal Connections and Descriptions
14.3 Functional Description
14.3.1 CPSW_3G Subsystem
14.3.1.1 Interrupt Pacing
14.3.1.2 Reset Isolation
14.3.1.2.1 Modes of Operation
14.3.1.3 Interrupts
14.3.1.3.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
14.3.1.3.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
14.3.1.3.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
14.3.1.3.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
14.3.1.4 Embedded Memories
14.3.2 CPSW_3G
14.3.2.1 Media Independent Interface (GMII)
14.3.2.2 IEEE 1588v2 Clock Synchronization Support
14.3.2.2.1 IEEE 1588v2 Receive Packet Operation
14.3.2.2.2 IEEE 1588v2 Transmit Packet Operation
14.3.2.3 Device Level Ring (DLR) Support
14.3.2.4 CPDMA RX and TX Interfaces
14.3.2.4.1 CPPI Buffer Descriptors
14.3.2.4.2 Receive DMA Interface
14.3.2.4.3 Transmit DMA Interface
14.3.2.4.4 Transmit Rate Limiting
14.3.2.4.5 Command IDLE
14.3.2.5 VLAN Aware Mode
14.3.2.6 VLAN Unaware Mode
14.3.2.7 Address Lookup Engine (ALE)
14.3.2.7.1 Address Table Entry
14.3.2.7.2 Packet Forwarding Processes
14.3.2.7.3 Learning/Updating/Touching Processes
14.3.2.8 Packet Priority Handling
14.3.2.9 FIFO Memory Control
14.3.2.10 FIFO Transmit Queue Control
14.3.2.10.1 Normal Priority Mode
14.3.2.10.2 Dual Mac Mode
14.3.2.10.3 Rate Limit Mode
14.3.2.11 Packet Padding
14.3.2.12 Flow Control
14.3.2.12.1 CPPI Port Flow Control
14.3.2.12.2 Ethernet Port Flow Control
14.3.2.13 Packet Drop Interface
14.3.2.14 Short Gap
14.3.2.15 Switch Latency
14.3.2.16 Emulation Control
14.3.2.17 Software IDLE
14.3.2.18 Software Reset
14.3.2.19 FIFO Loopback
14.3.2.20 CPSW_3G Network Statistics
14.3.2.20.1 Rx-only Statistics Descriptions
14.3.2.20.2 Tx-only Statistics Descriptions
14.3.2.20.3 Rx- and Tx-Shared Statistics Descriptions
14.3.3 Ethernet Mac Sliver (CPGMAC_SL)
14.3.3.1 GMII/MII Media Independent Interface
14.3.3.1.1 Data Reception
14.3.3.1.2 Data Transmission
14.3.3.2 Frame Classification
14.3.4 Command IDLE
14.3.5 RMII Interface
14.3.5.1 RMII Receive (RX)
14.3.5.2 RMII Transmit (TX)
14.3.6 RGMII Interface
14.3.6.1 RGMII Receive (RX)
14.3.6.2 In-Band Mode of Operation
14.3.6.3 Forced Mode of Operation
14.3.6.4 RGMII Transmit (TX)
14.3.7 Common Platform Time Sync (CPTS)
14.3.7.1 Architecture
14.3.7.2 Time Sync Overview
14.3.7.2.1 Time Sync Initialization
14.3.7.2.2 Time Stamp Value
14.3.7.2.3 Event FIFO
14.3.7.2.4 Time Sync Events
14.3.7.3 Interrupt Handling
14.3.8 MDIO
14.3.8.1 MII Management Interface Frame Formats
14.3.8.2 Functional Description
14.4 Software Operation
14.4.1 Transmit Operation
14.4.2 Receive Operation
14.4.3 Initializing the MDIO Module
14.4.4 Writing Data to a PHY Register
14.4.5 Reading Data from a PHY Register
14.4.6 Initialization and Configuration of CPSW
14.5 Ethernet Subsystem Registers
14.5.1 CPSW_ALE Registers
14.5.1.1 IDVER Register (offset = 0h) [reset = 290104h]
14.5.1.2 CONTROL Register (offset = 8h) [reset = 0h]
14.5.1.3 PRESCALE Register (offset = 10h) [reset = 0h]
14.5.1.4 UNKNOWN_VLAN Register (offset = 18h) [reset = 0h]
14.5.1.5 TBLCTL Register (offset = 20h) [reset = 0h]
14.5.1.6 TBLW2 Register (offset = 34h) [reset = 0h]
14.5.1.7 TBLW1 Register (offset = 38h) [reset = 0h]
14.5.1.8 TBLW0 Register (offset = 3Ch) [reset = 0h]
14.5.1.9 PORTCTL0 Register (offset = 40h) [reset = 0h]
14.5.1.10 PORTCTL1 Register (offset = 44h) [reset = 0h]
14.5.1.11 PORTCTL2 Register (offset = 48h) [reset = 0h]
14.5.1.12 PORTCTL3 Register (offset = 4Ch) [reset = 0h]
14.5.1.13 PORTCTL4 Register (offset = 50h) [reset = 0h]
14.5.1.14 PORTCTL5 Register (offset = 54h) [reset = 0h]
14.5.2 CPSW_CPDMA Registers
14.5.2.1 TX_IDVER Register (offset = 0h) [reset = 180108h]
14.5.2.2 TX_CONTROL Register (offset = 4h) [reset = 0h]
14.5.2.3 TX_TEARDOWN Register (offset = 8h) [reset = 0h]
14.5.2.4 RX_IDVER Register (offset = 10h) [reset = C0107h]
14.5.2.5 RX_CONTROL Register (offset = 14h) [reset = 0h]
14.5.2.6 RX_TEARDOWN Register (offset = 18h) [reset = 0h]
14.5.2.7 CPDMA_SOFT_RESET Register (offset = 1Ch) [reset = 0h]
14.5.2.8 DMACONTROL Register (offset = 20h) [reset = 0h]
14.5.2.9 DMASTATUS Register (offset = 24h) [reset = 0h]
14.5.2.10 RX_BUFFER_OFFSET Register (offset = 28h) [reset = 0h]
14.5.2.11 EMCONTROL Register (offset = 2Ch) [reset = 0h]
14.5.2.12 TX_PRI0_RATE Register (offset = 30h) [reset = 0h]
14.5.2.13 TX_PRI1_RATE Register (offset = 34h) [reset = 0h]
14.5.2.14 TX_PRI2_RATE Register (offset = 38h) [reset = 0h]
14.5.2.15 TX_PRI3_RATE Register (offset = 3Ch) [reset = 0h]
14.5.2.16 TX_PRI4_RATE Register (offset = 40h) [reset = 0h]
14.5.2.17 TX_PRI5_RATE Register (offset = 44h) [reset = 0h]
14.5.2.18 TX_PRI6_RATE Register (offset = 48h) [reset = 0h]
14.5.2.19 TX_PRI7_RATE Register (offset = 4Ch) [reset = 0h]
14.5.2.20 TX_INTSTAT_RAW Register (offset = 80h) [reset = 0h]
14.5.2.21 TX_INTSTAT_MASKED Register (offset = 84h) [reset = 0h]
14.5.2.22 TX_INTMASK_SET Register (offset = 88h) [reset = 0h]
14.5.2.23 TX_INTMASK_CLEAR Register (offset = 8Ch) [reset = 0h]
14.5.2.24 CPDMA_IN_VECTOR Register (offset = 90h) [reset = 0h]
14.5.2.25 CPDMA_EOI_VECTOR Register (offset = 94h) [reset = 0h]
14.5.2.26 RX_INTSTAT_RAW Register (offset = A0h) [reset = 0h]
14.5.2.27 RX_INTSTAT_MASKED Register (offset = A4h) [reset = 0h]
14.5.2.28 RX_INTMASK_SET Register (offset = A8h) [reset = 0h]
14.5.2.29 RX_INTMASK_CLEAR Register (offset = ACh) [reset = 0h]
14.5.2.30 DMA_INTSTAT_RAW Register (offset = B0h) [reset = 0h]
14.5.2.31 DMA_INTSTAT_MASKED Register (offset = B4h) [reset = 0h]
14.5.2.32 DMA_INTMASK_SET Register (offset = B8h) [reset = 0h]
14.5.2.33 DMA_INTMASK_CLEAR Register (offset = BCh) [reset = 0h]
14.5.2.34 RX0_PENDTHRESH Register (offset = C0h) [reset = 0h]
14.5.2.35 RX1_PENDTHRESH Register (offset = C4h) [reset = 0h]
14.5.2.36 RX2_PENDTHRESH Register (offset = C8h) [reset = 0h]
14.5.2.37 RX3_PENDTHRESH Register (offset = CCh) [reset = 0h]
14.5.2.38 RX4_PENDTHRESH Register (offset = D0h) [reset = 0h]
14.5.2.39 RX5_PENDTHRESH Register (offset = D4h) [reset = 0h]
14.5.2.40 RX6_PENDTHRESH Register (offset = D8h) [reset = 0h]
14.5.2.41 RX7_PENDTHRESH Register (offset = DCh) [reset = 0h]
14.5.2.42 RX0_FREEBUFFER Register (offset = E0h) [reset = 0h]
14.5.2.43 RX1_FREEBUFFER Register (offset = E4h) [reset = 0h]
14.5.2.44 RX2_FREEBUFFER Register (offset = E8h) [reset = 0h]
14.5.2.45 RX3_FREEBUFFER Register (offset = ECh) [reset = 0h]
14.5.2.46 RX4_FREEBUFFER Register (offset = F0h) [reset = 0h]
14.5.2.47 RX5_FREEBUFFER Register (offset = F4h) [reset = 0h]
14.5.2.48 RX6_FREEBUFFER Register (offset = F8h) [reset = 0h]
14.5.2.49 RX7_FREEBUFFER Register (offset = FCh) [reset = 0h]
14.5.3 CPSW_CPTS Registers
14.5.3.1 CPTS_IDVER Register (offset = 0h) [reset = 4E8A0101h]
14.5.3.2 CPTS_CONTROL Register (offset = 4h) [reset = 0h]
14.5.3.3 CPTS_TS_PUSH Register (offset = Ch) [reset = 0h]
14.5.3.4 CPTS_TS_LOAD_VAL Register (offset = 10h) [reset = 0h]
14.5.3.5 CPTS_TS_LOAD_EN Register (offset = 14h) [reset = 0h]
14.5.3.6 CPTS_INTSTAT_RAW Register (offset = 20h) [reset = 0h]
14.5.3.7 CPTS_INTSTAT_MASKED Register (offset = 24h) [reset = 0h]
14.5.3.8 CPTS_INT_ENABLE Register (offset = 28h) [reset = 0h]
14.5.3.9 CPTS_EVENT_POP Register (offset = 30h) [reset = 0h]
14.5.3.10 CPTS_EVENT_LOW Register (offset = 34h) [reset = 0h]
14.5.3.11 CPTS_EVENT_HIGH Register (offset = 38h) [reset = 0h]
14.5.4 CPSW_STATS Registers
14.5.5 CPDMA_STATERAM Registers
14.5.5.1 TX0_HDP Register (offset = A00h) [reset = 0h]
14.5.5.2 TX1_HDP Register (offset = A04h) [reset = 0h]
14.5.5.3 TX2_HDP Register (offset = A08h) [reset = 0h]
14.5.5.4 TX3_HDP Register (offset = A0Ch) [reset = 0h]
14.5.5.5 TX4_HDP Register (offset = A10h) [reset = 0h]
14.5.5.6 TX5_HDP Register (offset = A14h) [reset = 0h]
14.5.5.7 TX6_HDP Register (offset = A18h) [reset = 0h]
14.5.5.8 TX7_HDP Register (offset = A1Ch) [reset = 0h]
14.5.5.9 RX0_HDP Register (offset = A20h) [reset = 0h]
14.5.5.10 RX1_HDP Register (offset = A24h) [reset = 0h]
14.5.5.11 RX2_HDP Register (offset = A28h) [reset = 0h]
14.5.5.12 RX3_HDP Register (offset = A2Ch) [reset = 0h]
14.5.5.13 RX4_HDP Register (offset = A30h) [reset = 0h]
14.5.5.14 RX5_HDP Register (offset = A34h) [reset = 0h]
14.5.5.15 RX6_HDP Register (offset = A38h) [reset = 0h]
14.5.5.16 RX7_HDP Register (offset = A3Ch) [reset = 0h]
14.5.5.17 TX0_CP Register (offset = A40h) [reset = 0h]
14.5.5.18 TX1_CP Register (offset = A44h) [reset = 0h]
14.5.5.19 TX2_CP Register (offset = A48h) [reset = 0h]
14.5.5.20 TX3_CP Register (offset = A4Ch) [reset = 0h]
14.5.5.21 TX4_CP Register (offset = A50h) [reset = 0h]
14.5.5.22 TX5_CP Register (offset = A54h) [reset = 0h]
14.5.5.23 TX6_CP Register (offset = A58h) [reset = 0h]
14.5.5.24 TX7_CP Register (offset = A5Ch) [reset = 0h]
14.5.5.25 RX0_CP Register (offset = A60h) [reset = 0h]
14.5.5.26 RX1_CP Register (offset = A64h) [reset = 0h]
14.5.5.27 RX2_CP Register (offset = A68h) [reset = 0h]
14.5.5.28 RX3_CP Register (offset = A6Ch) [reset = 0h]
14.5.5.29 RX4_CP Register (offset = A70h) [reset = 0h]
14.5.5.30 RX5_CP Register (offset = A74h) [reset = 0h]
14.5.5.31 RX6_CP Register (offset = A78h) [reset = 0h]
14.5.5.32 RX7_CP Register (offset = A7Ch) [reset = 0h]
14.5.6 CPSW_PORT Registers
14.5.6.1 P0_CONTROL Register (offset = 0h) [reset = 0h]
14.5.6.2 P0_MAX_BLKS Register (offset = 8h) [reset = 104h]
14.5.6.3 P0_BLK_CNT Register (offset = Ch) [reset = 41h]
14.5.6.4 P0_TX_IN_CTL Register (offset = 10h) [reset = 40C0h]
14.5.6.5 P0_PORT_VLAN Register (offset = 14h) [reset = 0h]
14.5.6.6 P0_TX_PRI_MAP Register (offset = 18h) [reset = 33221001h]
14.5.6.7 P0_CPDMA_TX_PRI_MAP Register (offset = 1Ch) [reset = 76543210h]
14.5.6.8 P0_CPDMA_RX_CH_MAP Register (offset = 20h) [reset = 0h]
14.5.6.9 P0_RX_DSCP_PRI_MAP0 Register (offset = 30h) [reset = 0h]
14.5.6.10 P0_RX_DSCP_PRI_MAP1 Register (offset = 34h) [reset = 0h]
14.5.6.11 P0_RX_DSCP_PRI_MAP2 Register (offset = 38h) [reset = 0h]
14.5.6.12 P0_RX_DSCP_PRI_MAP3 Register (offset = 3Ch) [reset = 0h]
14.5.6.13 P0_RX_DSCP_PRI_MAP4 Register (offset = 40h) [reset = 0h]
14.5.6.14 P0_RX_DSCP_PRI_MAP5 Register (offset = 44h) [reset = 0h]
14.5.6.15 P0_RX_DSCP_PRI_MAP6 Register (offset = 48h) [reset = 0h]
14.5.6.16 P0_RX_DSCP_PRI_MAP7 Register (offset = 4Ch) [reset = 0h]
14.5.6.17 P1_CONTROL Register (offset = 100h) [reset = 0h]
14.5.6.18 P1_MAX_BLKS Register (offset = 108h) [reset = 113h]
14.5.6.19 P1_BLK_CNT Register (offset = 10Ch) [reset = 41h]
14.5.6.20 P1_TX_IN_CTL Register (offset = 110h) [reset = 80040C0h]
14.5.6.21 P1_PORT_VLAN Register (offset = 114h) [reset = 0h]
14.5.6.22 P1_TX_PRI_MAP Register (offset = 118h) [reset = 33221001h]
14.5.6.23 P1_TS_SEQ_MTYPE Register (offset = 11Ch) [reset = 1E0000h]
14.5.6.24 P1_SA_LO Register (offset = 120h) [reset = 0h]
14.5.6.25 P1_SA_HI Register (offset = 124h) [reset = 0h]
14.5.6.26 P1_SEND_PERCENT Register (offset = 128h) [reset = 0h]
14.5.6.27 P1_RX_DSCP_PRI_MAP0 Register (offset = 130h) [reset = 0h]
14.5.6.28 P1_RX_DSCP_PRI_MAP1 Register (offset = 134h) [reset = 0h]
14.5.6.29 P1_RX_DSCP_PRI_MAP2 Register (offset = 138h) [reset = 0h]
14.5.6.30 P1_RX_DSCP_PRI_MAP3 Register (offset = 13Ch) [reset = 0h]
14.5.6.31 P1_RX_DSCP_PRI_MAP4 Register (offset = 140h) [reset = 0h]
14.5.6.32 P1_RX_DSCP_PRI_MAP5 Register (offset = 144h) [reset = 0h]
14.5.6.33 P1_RX_DSCP_PRI_MAP6 Register (offset = 148h) [reset = 0h]
14.5.6.34 P1_RX_DSCP_PRI_MAP7 Register (offset = 14Ch) [reset = 0h]
14.5.6.35 P2_CONTROL Register (offset = 200h) [reset = 0h]
14.5.6.36 P2_MAX_BLKS Register (offset = 208h) [reset = 113h]
14.5.6.37 P2_BLK_CNT Register (offset = 20Ch) [reset = 41h]
14.5.6.38 P2_TX_IN_CTL Register (offset = 210h) [reset = 80040C0h]
14.5.6.39 P2_PORT_VLAN Register (offset = 214h) [reset = 0h]
14.5.6.40 P2_TX_PRI_MAP Register (offset = 218h) [reset = 33221001h]
14.5.6.41 P2_TS_SEQ_MTYPE Register (offset = 21Ch) [reset = 1E0000h]
14.5.6.42 P2_SA_LO Register (offset = 220h) [reset = 0h]
14.5.6.43 P2_SA_HI Register (offset = 224h) [reset = 0h]
14.5.6.44 P2_SEND_PERCENT Register (offset = 228h) [reset = 0h]
14.5.6.45 P2_RX_DSCP_PRI_MAP0 Register (offset = 230h) [reset = 0h]
14.5.6.46 P2_RX_DSCP_PRI_MAP1 Register (offset = 234h) [reset = 0h]
14.5.6.47 P2_RX_DSCP_PRI_MAP2 Register (offset = 238h) [reset = 0h]
14.5.6.48 P2_RX_DSCP_PRI_MAP3 Register (offset = 23Ch) [reset = 0h]
14.5.6.49 P2_RX_DSCP_PRI_MAP4 Register (offset = 240h) [reset = 0h]
14.5.6.50 P2_RX_DSCP_PRI_MAP5 Register (offset = 244h) [reset = 0h]
14.5.6.51 P2_RX_DSCP_PRI_MAP6 Register (offset = 248h) [reset = 0h]
14.5.6.52 P2_RX_DSCP_PRI_MAP7 Register (offset = 24Ch) [reset = 0h]
14.5.7 CPSW_SL Registers
14.5.7.1 IDVER Register (offset = 0h) [reset = 170112h]
14.5.7.2 MACCONTROL Register (offset = 4h) [reset = 0h]
14.5.7.3 MACSTATUS Register (offset = 8h) [reset = 0h]
14.5.7.4 SOFT_RESET Register (offset = Ch) [reset = 0h]
14.5.7.5 RX_MAXLEN Register (offset = 10h) [reset = 5EEh]
14.5.7.6 BOFFTEST Register (offset = 14h) [reset = 0h]
14.5.7.7 RX_PAUSE Register (offset = 18h) [reset = 0h]
14.5.7.8 TX_PAUSE Register (offset = 1Ch) [reset = 0h]
14.5.7.9 EMCONTROL Register (offset = 20h) [reset = 0h]
14.5.7.10 RX_PRI_MAP Register (offset = 24h) [reset = 76543210h]
14.5.7.11 TX_GAP Register (offset = 28h) [reset = Ch]
14.5.8 CPSW_SS Registers
14.5.8.1 ID_VER Register (offset = 0h) [reset = 190112h]
14.5.8.2 CONTROL Register (offset = 4h) [reset = 0h]
14.5.8.3 SOFT_RESET Register (offset = 8h) [reset = 0h]
14.5.8.4 STAT_PORT_EN Register (offset = Ch) [reset = 0h]
14.5.8.5 PTYPE Register (offset = 10h) [reset = 0h]
14.5.8.6 SOFT_IDLE Register (offset = 14h) [reset = 0h]
14.5.8.7 THRU_RATE Register (offset = 18h) [reset = 3003h]
14.5.8.8 GAP_THRESH Register (offset = 1Ch) [reset = Bh]
14.5.8.9 TX_START_WDS Register (offset = 20h) [reset = 20h]
14.5.8.10 FLOW_CONTROL Register (offset = 24h) [reset = 1h]
14.5.8.11 VLAN_LTYPE Register (offset = 28h) [reset = 81008100h]
14.5.8.12 TS_LTYPE Register (offset = 2Ch) [reset = 0h]
14.5.8.13 DLR_LTYPE Register (offset = 30h) [reset = 80E1h]
14.5.9 CPSW_WR Registers
14.5.9.1 IDVER Register (offset = 0h) [reset = 4EDB0100h]
14.5.9.2 SOFT_RESET Register (offset = 4h) [reset = 0h]
14.5.9.3 CONTROL Register (offset = 8h) [reset = 0h]
14.5.9.4 INT_CONTROL Register (offset = Ch) [reset = 0h]
14.5.9.5 C0_RX_THRESH_EN Register (offset = 10h) [reset = 0h]
14.5.9.6 C0_RX_EN Register (offset = 14h) [reset = 0h]
14.5.9.7 C0_TX_EN Register (offset = 18h) [reset = 0h]
14.5.9.8 C0_MISC_EN Register (offset = 1Ch) [reset = 0h]
14.5.9.9 C1_RX_THRESH_EN Register (offset = 20h) [reset = 0h]
14.5.9.10 C1_RX_EN Register (offset = 24h) [reset = 0h]
14.5.9.11 C1_TX_EN Register (offset = 28h) [reset = 0h]
14.5.9.12 C1_MISC_EN Register (offset = 2Ch) [reset = 0h]
14.5.9.13 C2_RX_THRESH_EN Register (offset = 30h) [reset = 0h]
14.5.9.14 C2_RX_EN Register (offset = 34h) [reset = 0h]
14.5.9.15 C2_TX_EN Register (offset = 38h) [reset = 0h]
14.5.9.16 C2_MISC_EN Register (offset = 3Ch) [reset = 0h]
14.5.9.17 C0_RX_THRESH_STAT Register (offset = 40h) [reset = 0h]
14.5.9.18 C0_RX_STAT Register (offset = 44h) [reset = 0h]
14.5.9.19 C0_TX_STAT Register (offset = 48h) [reset = 0h]
14.5.9.20 C0_MISC_STAT Register (offset = 4Ch) [reset = 0h]
14.5.9.21 C1_RX_THRESH_STAT Register (offset = 50h) [reset = 0h]
14.5.9.22 C1_RX_STAT Register (offset = 54h) [reset = 0h]
14.5.9.23 C1_TX_STAT Register (offset = 58h) [reset = 0h]
14.5.9.24 C1_MISC_STAT Register (offset = 5Ch) [reset = 0h]
14.5.9.25 C2_RX_THRESH_STAT Register (offset = 60h) [reset = 0h]
14.5.9.26 C2_RX_STAT Register (offset = 64h) [reset = 0h]
14.5.9.27 C2_TX_STAT Register (offset = 68h) [reset = 0h]
14.5.9.28 C2_MISC_STAT Register (offset = 6Ch) [reset = 0h]
14.5.9.29 C0_RX_IMAX Register (offset = 70h) [reset = 0h]
14.5.9.30 C0_TX_IMAX Register (offset = 74h) [reset = 0h]
14.5.9.31 C1_RX_IMAX Register (offset = 78h) [reset = 0h]
14.5.9.32 C1_TX_IMAX Register (offset = 7Ch) [reset = 0h]
14.5.9.33 C2_RX_IMAX Register (offset = 80h) [reset = 0h]
14.5.9.34 C2_TX_IMAX Register (offset = 84h) [reset = 0h]
14.5.9.35 RGMII_CTL Register (offset = 88h) [reset = 0h]
14.5.10 Management Data Input/Output (MDIO) Registers
14.5.10.1 MDIO Version Register (MDIOVER)
14.5.10.2 MDIO Control Register (MDIOCONTROL)
14.5.10.3 PHY Acknowledge Status Register (MDIOALIVE)
14.5.10.4 PHY Link Status Register (MDIOLINK)
14.5.10.5 MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW)
14.5.10.6 MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED)
14.5.10.7 MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW)
14.5.10.8 MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED)
14.5.10.9 MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET)
14.5.10.10 MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR)
14.5.10.11 MDIO User Access Register 0 (MDIOUSERACCESS0)
14.5.10.12 MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0)
14.5.10.13 MDIO User Access Register 1 (MDIOUSERACCESS1)
14.5.10.14 MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1)
15 Pulse-Width Modulation Subsystem (PWMSS)
15.1 Pulse-Width Modulation Subsystem (PWMSS)
15.1.1 Introduction
15.1.1.1 Features
15.1.1.2 UnsupportedFeatures
15.1.2 Integration
15.1.2.1 PWMSS Connectivity Attributes
15.1.2.2 PWMSS Clock and Reset Management
15.1.2.3 PWMSS Pin list
15.1.3 PWMSS Registers
15.1.3.1 IDVER Register (offset = 0h) [reset = 40000000h]
15.1.3.2 SYSCONFIG Register (offset = 4h) [reset = 28h]
15.1.3.3 CLKCONFIG Register (offset = 8h) [reset = 111h]
15.1.3.4 CLKSTATUS Register (offset = Ch) [reset = 0h]
15.2 Enhanced PWM (ePWM) Module
15.2.1 Introduction
15.2.1.1 Submodule Overview
15.2.2 Functional Description
15.2.2.1 Overview
15.2.2.2 Proper Interrupt Initialization Procedure
15.2.2.3 Time-Base (TB) Submodule
15.2.2.3.1 Purpose of the Time-Base Submodule
15.2.2.3.2 Controlling and Monitoring the Time-Base Submodule
15.2.2.3.3 Calculating PWM Period and Frequency
15.2.2.3.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
15.2.2.3.5 Time-Base Counter Modes and Timing Waveforms
15.2.2.4 Counter-Compare (CC) Submodule
15.2.2.4.1 Purpose of the Counter-Compare Submodule
15.2.2.4.2 Controlling and Monitoring the Counter-Compare Submodule
15.2.2.4.3 Operational Highlights for the Counter-Compare Submodule
15.2.2.4.4 Count Mode Timing Waveforms
15.2.2.5 Action-Qualifier (AQ) Submodule
15.2.2.5.1 Purpose of the Action-Qualifier Submodule
15.2.2.5.2 Controlling and Monitoring the Action-Qualifier Submodule
15.2.2.5.3 Action-Qualifier Event Priority
15.2.2.5.4 Waveforms for Common Configurations
15.2.2.6 Dead-Band Generator (DB) Submodule
15.2.2.6.1 Purpose of the Dead-Band Submodule
15.2.2.6.2 Controlling and Monitoring the Dead-Band Submodule
15.2.2.6.3 Operational Highlights for the Dead-Band Generator Submodule
15.2.2.7 PWM-Chopper (PC) Submodule
15.2.2.7.1 Purpose of the PWM-Chopper Submodule
15.2.2.7.2 Controlling the PWM-Chopper Submodule
15.2.2.7.3 Operational Highlights for the PWM-Chopper Submodule
15.2.2.7.4 Waveforms
15.2.2.8 Trip-Zone (TZ) Submodule
15.2.2.8.1 Purpose of the Trip-Zone Submodule
15.2.2.8.2 Controlling and Monitoring the Trip-Zone Submodule
15.2.2.8.3 Operational Highlights for the Trip-Zone Submodule
15.2.2.8.4 Generating Trip Event Interrupts
15.2.2.9 Event-Trigger (ET) Submodule
15.2.2.9.1 Purpose of the Event-Trigger Submodule
15.2.2.9.2 Controlling and Monitoring the Event-Trigger Submodule
15.2.2.9.3 Operational Overview of the Event-Trigger Submodule
15.2.2.10 High-Resolution PWM (HRPWM) Submodule
15.2.2.10.1 Purpose of the High-Resolution PWM Submodule
15.2.2.10.2 Architecture of the High-Resolution PWM Submodule
15.2.2.10.3 Controlling and Monitoring the High-Resolution PWM Submodule
15.2.2.10.4 Configuring the High-Resolution PWM Submodule
15.2.2.10.5 Operational Highlights for the High-Resolution PWM Submodule
15.2.3 Use Cases
15.2.3.1 Overview of Multiple Modules
15.2.3.2 Key Configuration Capabilities
15.2.3.3 Controlling Multiple Buck Converters With Independent Frequencies
15.2.3.4 Controlling Multiple Buck Converters With Same Frequencies
15.2.3.5 Controlling Multiple Half H-Bridge (HHB) Converters
15.2.3.6 Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
15.2.3.7 Practical Applications Using Phase Control Between PWM Modules
15.2.3.8 Controlling a 3-Phase Interleaved DC/DC Converter
15.2.3.9 Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
15.2.4 Registers
15.2.4.1 Time-Base Submodule Registers
15.2.4.1.1 Time-Base Control Register (TBCTL)
15.2.4.1.2 Time-Base Status Register (TBSTS)
15.2.4.1.3 Time-Base Phase Register (TBPHS)
15.2.4.1.4 Time-Base Counter Register (TBCNT)
15.2.4.1.5 Time-Base Period Register (TBPRD)
15.2.4.2 Counter-Compare Submodule Registers
15.2.4.2.1 Counter-Compare Control Register (CMPCTL)
15.2.4.2.2 Counter-Compare A Register (CMPA)
15.2.4.2.3 Counter-Compare B Register (CMPB)
15.2.4.3 Action-Qualifier Submodule Registers
15.2.4.3.1 Action-Qualifier Output A Control Register (AQCTLA)
15.2.4.3.2 Action-Qualifier Output B Control Register (AQCTLB)
15.2.4.3.3 Action-Qualifier Software Force Register (AQSFRC)
15.2.4.3.4 Action-Qualifier Continuous Software Force Register (AQCSFRC)
15.2.4.4 Dead-Band Generator Submodule Registers
15.2.4.4.1 Dead-Band Generator Control Register (DBCTL)
15.2.4.4.2 Dead-Band Generator Rising Edge Delay Register (DBRED)
15.2.4.4.3 Dead-Band Generator Falling Edge Delay Register (DBFED)
15.2.4.5 Trip-Zone Submodule Registers
15.2.4.5.1 Trip-Zone Select Register (TZSEL)
15.2.4.5.2 Trip-Zone Control Register (TZCTL)
15.2.4.5.3 Trip-Zone Enable Interrupt Register (TZEINT)
15.2.4.5.4 Trip-Zone Flag Register (TZFLG)
15.2.4.5.5 Trip-Zone Clear Register (TZCLR)
15.2.4.5.6 Trip-Zone Force Register (TZFRC)
15.2.4.6 Event-Trigger Submodule Registers
15.2.4.6.1 Event-Trigger Selection Register (ETSEL)
15.2.4.6.2 Event-Trigger Prescale Register (ETPS)
15.2.4.6.3 Event-Trigger Flag Register (ETFLG)
15.2.4.6.4 Event-Trigger Clear Register (ETCLR)
15.2.4.6.5 Event-Trigger Force Register (ETFRC)
15.2.4.7 PWM-Chopper Submodule Register
15.2.4.8 High-Resolution PWM Submodule Registers
15.2.4.8.1 Time-Base Phase High-Resolution Register (TBPHSHR)
15.2.4.8.2 Counter-Compare A High-Resolution Register (CMPAHR)
15.2.4.8.3 HRPWM Control Register (HRCTL)
15.3 Enhanced Capture (eCAP) Module
15.3.1 Introduction
15.3.1.1 Purpose of the Peripheral
15.3.1.2 Features
15.3.2 Functional Description
15.3.2.1 Capture and APWM Operating Mode
15.3.2.2 Capture Mode Description
15.3.2.2.1 Event Prescaler
15.3.2.2.2 Edge Polarity Select and Qualifier
15.3.2.2.3 Continuous/One-Shot Control
15.3.2.2.4 32-Bit Counter and Phase Control
15.3.2.2.5 CAP1-CAP4 Registers
15.3.2.2.6 Interrupt Control
15.3.2.2.7 Shadow Load and Lockout Control
15.3.2.2.8 APWM Mode Operation
15.3.3 Use Cases
15.3.3.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
15.3.3.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
15.3.3.3 Time Difference (Delta) Operation Rising Edge Trigger Example
15.3.3.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
15.3.3.5 Application of the APWM Mode
15.3.3.5.1 Simple PWM Generation (Independent Channel/s) Example
15.3.3.5.2 Multichannel PWM Generation with Synchronization Example
15.3.3.5.3 Multichannel PWM Generation with Phase Control Example
15.3.4 Registers
15.3.4.1 Time-Stamp Counter Register (TSCTR)
15.3.4.2 Counter Phase Control Register (CTRPHS)
15.3.4.3 Capture 1 Register (CAP1)
15.3.4.4 Capture 2 Register (CAP2)
15.3.4.5 Capture 3 Register (CAP3)
15.3.4.6 Capture 4 Register (CAP4)
15.3.4.7 ECAP Control Register 1 (ECCTL1)
15.3.4.8 ECAP Control Register 2 (ECCTL2)
15.3.4.9 ECAP Interrupt Enable Register (ECEINT)
15.3.4.10 ECAP Interrupt Flag Register (ECFLG)
15.3.4.11 ECAP Interrupt Clear Register (ECCLR)
15.3.4.12 ECAP Interrupt Forcing Register (ECFRC)
15.3.4.13 Revision ID Register (REVID)
15.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
15.4.1 Introduction
15.4.2 Functional Description
15.4.2.1 EQEP Inputs
15.4.2.2 Functional Description
15.4.2.3 Quadrature Decoder Unit (QDU)
15.4.2.3.1 Position Counter Input Modes
15.4.2.3.2 eQEP Input Polarity Selection
15.4.2.3.3 Position-Compare Sync Output
15.4.2.4 Position Counter and Control Unit (PCCU)
15.4.2.4.1 Position Counter Operating Modes
15.4.2.4.2 Position Counter Latch
15.4.2.4.3 Position Counter Initialization
15.4.2.4.4 eQEP Position-compare Unit
15.4.2.5 eQEP Edge Capture Unit
15.4.2.6 eQEP Watchdog
15.4.2.7 Unit Timer Base
15.4.2.8 eQEP Interrupt Structure
15.4.3 eQEP Registers
15.4.3.1 eQEP Position Counter Register (QPOSCNT)
15.4.3.2 eQEP Position Counter Initialization Register (QPOSINIT)
15.4.3.3 eQEP Maximum Position Count Register (QPOSMAX)
15.4.3.4 eQEP Position-Compare Register (QPOSCMP)
15.4.3.5 eQEP Index Position Latch Register (QPOSILAT)
15.4.3.6 eQEP Strobe Position Latch Register (QPOSSLAT)
15.4.3.7 eQEP Position Counter Latch Register (QPOSLAT)
15.4.3.8 eQEP Unit Timer Register (QUTMR)
15.4.3.9 eQEP Unit Period Register (QUPRD)
15.4.3.10 eQEP Watchdog Timer Register (QWDTMR)
15.4.3.11 eQEP Watchdog Period Register (QWDPRD)
15.4.3.12 QEP Decoder Control Register (QDECCTL)
15.4.3.13 eQEP Control Register (QEPCTL)
15.4.3.14 eQEP Capture Control Register (QCAPCTL)
15.4.3.15 eQEP Position-Compare Control Register (QPOSCTL)
15.4.3.16 eQEP Interrupt Enable Register (QEINT)
15.4.3.17 eQEP Interrupt Flag Register (QFLG)
15.4.3.18 eQEP Interrupt Clear Register (QCLR)
15.4.3.19 eQEP Interrupt Force Register (QFRC)
15.4.3.20 eQEP Status Register (QEPSTS)
15.4.3.21 eQEP Capture Timer Register (QCTMR)
15.4.3.22 eQEP Capture Period Register (QCPRD)
15.4.3.23 eQEP Capture Timer Latch Register (QCTMRLAT)
15.4.3.24 eQEP Capture Period Latch Register (QCPRDLAT)
15.4.3.25 eQEP Revision ID Register (REVID)
16 Universal Serial Bus (USB)
16.1 Introduction
16.1.1 Acronyms, Abbreviations, and Definitions
16.1.2 USB Features
16.1.3 Unsupported USB OTG and PHY Features
16.2 Integration
16.2.1 USB Connectivity Attributes
16.2.2 USB Clock and Reset Management
16.2.3 USB Pin List
16.2.4 USB GPIO Details
16.2.5 USB Unbonded PHY Pads
16.3 Functional Description
16.3.1 VBUS Voltage Sourcing Control
16.3.2 Pull-up/Pull-Down Resistors
16.3.3 Role Assuming Method
16.3.4 Clock, PLL, and PHY Initialization
16.3.5 Indexed and Non-Indexed Register Spaces
16.3.6 Dynamic FIFO Sizing
16.3.7 USB Controller Host and Peripheral Modes Operation
16.3.8 Protocol Description(s)
16.3.8.1 USB Controller Peripheral Mode Operation
16.3.8.1.1 Control Transactions:Peripheral Mode
16.3.8.1.2 Bulk Transfer: Peripheral Mode
16.3.8.1.3 Interrupt Transfer: Peripheral Mode
16.3.8.1.4 Isochronous Transfer: Peripheral Mode
16.3.8.2 USB Controller Host Mode Operation
16.3.8.2.1 Control Transactions: Host Mode
16.3.8.2.2 Bulk Transfer: Host Mode
16.3.8.2.3 Interrupt Transfer: Host Mode
16.3.8.2.4 Isochronous Transfer: Host Mode
16.3.9 Communications Port Programming Interface (CPPI) 4.1 DMA
16.3.9.1 CPPI Terminology
16.3.9.2 Data Structures
16.3.9.2.1 Host Packet Descriptor/ Packet Descriptor (SOP Descriptor)
16.3.9.2.2 Host Buffer Descriptor/Buffer Descriptor (BD)
16.3.9.2.3 Teardown Descriptor
16.3.9.3 Queue Manager
16.3.9.3.1 Queue Types
16.3.9.3.2 Free Descriptor Queue (Receive Submit Queue)
16.3.9.3.3 Transmit Submit Queue
16.3.9.3.4 Transmit Completion (Return) Queue
16.3.9.3.5 Receive Completion (Return) Queue
16.3.9.3.6 Diverting Queue Packets from one Queue to Another
16.3.9.3.7 Teardown Queue
16.3.9.4 Memory Regions and Linking RAM
16.3.9.5 Zero Length Packets
16.3.9.6 CPPI DMA Scheduler
16.3.9.6.1 CPPI DMA Scheduler Operation
16.3.9.7 CPPI DMA State Registers
16.3.9.7.1 Transmit DMA State Registers
16.3.9.7.2 Receive DMA State Registers
16.3.9.8 CPPI DMA Protocols Supported
16.3.9.8.1 Transparent DMA Transfer
16.3.9.8.2 RNDIS DMA Transfer
16.3.9.8.3 Generic RNDIS DMA Transfer
16.3.9.8.4 Linux CDC DMA Transfer
16.3.9.9 USB Data Flow Using DMA
16.3.9.9.1 Transmit USB Data Flow Using DMA
16.3.9.9.2 Receive USB Data Flow Using DMA
16.3.10 USB 2.0 Test Modes
16.3.10.1 TEST_SE0_NAK
16.3.10.2 TEST_J
16.3.10.3 TEST_K
16.3.10.4 TEST_PACKET
16.3.10.5 FIFO_ACCESS
16.3.10.6 FORCE_HOST
16.4 Supported Use Cases
16.5 USB Registers
16.5.1 USBSS Registers
16.5.1.1 REVREG Register (offset = 0h) [reset = 4EA20800h]
16.5.1.2 SYSCONFIG Register (offset = 10h) [reset = 28h]
16.5.1.3 IRQSTATRAW Register (offset = 24h) [reset = 0h]
16.5.1.4 IRQSTAT Register (offset = 28h) [reset = 0h]
16.5.1.5 IRQENABLER Register (offset = 2Ch) [reset = 0h]
16.5.1.6 IRQCLEARR Register (offset = 30h) [reset = 0h]
16.5.1.7 IRQDMATHOLDTX00 Register (offset = 100h) [reset = 0h]
16.5.1.8 IRQDMATHOLDTX01 Register (offset = 104h) [reset = 0h]
16.5.1.9 IRQDMATHOLDTX02 Register (offset = 108h) [reset = 0h]
16.5.1.10 IRQDMATHOLDTX03 Register (offset = 10Ch) [reset = 0h]
16.5.1.11 IRQDMATHOLDRX00 Register (offset = 110h) [reset = 0h]
16.5.1.12 IRQDMATHOLDRX01 Register (offset = 114h) [reset = 0h]
16.5.1.13 IRQDMATHOLDRX02 Register (offset = 118h) [reset = 0h]
16.5.1.14 IRQDMATHOLDRX03 Register (offset = 11Ch) [reset = 0h]
16.5.1.15 IRQDMATHOLDTX10 Register (offset = 120h) [reset = 0h]
16.5.1.16 IRQDMATHOLDTX11 Register (offset = 124h) [reset = 0h]
16.5.1.17 IRQDMATHOLDTX12 Register (offset = 128h) [reset = 0h]
16.5.1.18 IRQDMATHOLDTX13 Register (offset = 12Ch) [reset = 0h]
16.5.1.19 IRQDMATHOLDRX10 Register (offset = 130h) [reset = 0h]
16.5.1.20 IRQDMATHOLDRX11 Register (offset = 134h) [reset = 0h]
16.5.1.21 IRQDMATHOLDRX12 Register (offset = 138h) [reset = 0h]
16.5.1.22 IRQDMATHOLDRX13 Register (offset = 13Ch) [reset = 0h]
16.5.1.23 IRQDMAENABLE0 Register (offset = 140h) [reset = 0h]
16.5.1.24 IRQDMAENABLE1 Register (offset = 144h) [reset = 0h]
16.5.1.25 IRQFRAMETHOLDTX00 Register (offset = 200h) [reset = 0h]
16.5.1.26 IRQFRAMETHOLDTX01 Register (offset = 204h) [reset = 0h]
16.5.1.27 IRQFRAMETHOLDTX02 Register (offset = 208h) [reset = 0h]
16.5.1.28 IRQFRAMETHOLDTX03 Register (offset = 20Ch) [reset = 0h]
16.5.1.29 IRQFRAMETHOLDRX00 Register (offset = 210h) [reset = 0h]
16.5.1.30 IRQFRAMETHOLDRX01 Register (offset = 214h) [reset = 0h]
16.5.1.31 IRQFRAMETHOLDRX02 Register (offset = 218h) [reset = 0h]
16.5.1.32 IRQFRAMETHOLDRX03 Register (offset = 21Ch) [reset = 0h]
16.5.1.33 IRQFRAMETHOLDTX10 Register (offset = 220h) [reset = 0h]
16.5.1.34 IRQFRAMETHOLDTX11 Register (offset = 224h) [reset = 0h]
16.5.1.35 IRQFRAMETHOLDTX12 Register (offset = 228h) [reset = 0h]
16.5.1.36 IRQFRAMETHOLDTX13 Register (offset = 22Ch) [reset = 0h]
16.5.1.37 IRQFRAMETHOLDRX10 Register (offset = 230h) [reset = 0h]
16.5.1.38 IRQFRAMETHOLDRX11 Register (offset = 234h) [reset = 0h]
16.5.1.39 IRQFRAMETHOLDRX12 Register (offset = 238h) [reset = 0h]
16.5.1.40 IRQFRAMETHOLDRX13 Register (offset = 23Ch) [reset = 0h]
16.5.1.41 IRQFRAMEENABLE0 Register (offset = 240h) [reset = 0h]
16.5.1.42 IRQFRAMEENABLE1 Register (offset = 244h) [reset = 0h]
16.5.2 USB0_CTRL Registers
16.5.2.1 USB0REV Register (offset = 0h) [reset = 4EA20800h]
16.5.2.2 USB0CTRL Register (offset = 14h) [reset = 0h]
16.5.2.3 USB0STAT Register (offset = 18h) [reset = 0h]
16.5.2.4 USB0IRQMSTAT Register (offset = 20h) [reset = 0h]
16.5.2.5 USB0IRQSTATRAW0 Register (offset = 28h) [reset = 0h]
16.5.2.6 USB0IRQSTATRAW1 Register (offset = 2Ch) [reset = 0h]
16.5.2.7 USB0IRQSTAT0 Register (offset = 30h) [reset = 0h]
16.5.2.8 USB0IRQSTAT1 Register (offset = 34h) [reset = 0h]
16.5.2.9 USB0IRQENABLESET0 Register (offset = 38h) [reset = 0h]
16.5.2.10 USB0IRQENABLESET1 Register (offset = 3Ch) [reset = 0h]
16.5.2.11 USB0IRQENABLECLR0 Register (offset = 40h) [reset = 0h]
16.5.2.12 USB0IRQENABLECLR1 Register (offset = 44h) [reset = 0h]
16.5.2.13 USB0TXMODE Register (offset = 70h) [reset = 0h]
16.5.2.14 USB0RXMODE Register (offset = 74h) [reset = 0h]
16.5.2.15 USB0GENRNDISEP1 Register (offset = 80h) [reset = 0h]
16.5.2.16 USB0GENRNDISEP2 Register (offset = 84h) [reset = 0h]
16.5.2.17 USB0GENRNDISEP3 Register (offset = 88h) [reset = 0h]
16.5.2.18 USB0GENRNDISEP4 Register (offset = 8Ch) [reset = 0h]
16.5.2.19 USB0GENRNDISEP5 Register (offset = 90h) [reset = 0h]
16.5.2.20 USB0GENRNDISEP6 Register (offset = 94h) [reset = 0h]
16.5.2.21 USB0GENRNDISEP7 Register (offset = 98h) [reset = 0h]
16.5.2.22 USB0GENRNDISEP8 Register (offset = 9Ch) [reset = 0h]
16.5.2.23 USB0GENRNDISEP9 Register (offset = A0h) [reset = 0h]
16.5.2.24 USB0GENRNDISEP10 Register (offset = A4h) [reset = 0h]
16.5.2.25 USB0GENRNDISEP11 Register (offset = A8h) [reset = 0h]
16.5.2.26 USB0GENRNDISEP12 Register (offset = ACh) [reset = 0h]
16.5.2.27 USB0GENRNDISEP13 Register (offset = B0h) [reset = 0h]
16.5.2.28 USB0GENRNDISEP14 Register (offset = B4h) [reset = 0h]
16.5.2.29 USB0GENRNDISEP15 Register (offset = B8h) [reset = 0h]
16.5.2.30 USB0AUTOREQ Register (offset = D0h) [reset = 0h]
16.5.2.31 USB0SRPFIXTIME Register (offset = D4h) [reset = 280DE80h]
16.5.2.32 USB0_TDOWN Register (offset = D8h) [reset = 0h]
16.5.2.33 USB0UTMI Register (offset = E0h) [reset = 200002h]
16.5.2.34 USB0MGCUTMILB Register (offset = E4h) [reset = 82h]
16.5.2.35 USB0MODE Register (offset = E8h) [reset = 100h]
16.5.3 USB1_CTRL Registers
16.5.3.1 USB1REV Register (offset = 0h) [reset = 4EA20800h]
16.5.3.2 USB1CTRL Register (offset = 14h) [reset = 0h]
16.5.3.3 USB1STAT Register (offset = 18h) [reset = 0h]
16.5.3.4 USB1IRQMSTAT Register (offset = 20h) [reset = 0h]
16.5.3.5 USB1IRQSTATRAW0 Register (offset = 28h) [reset = 0h]
16.5.3.6 USB1IRQSTATRAW1 Register (offset = 2Ch) [reset = 0h]
16.5.3.7 USB1IRQSTAT0 Register (offset = 30h) [reset = 0h]
16.5.3.8 USB1IRQSTAT1 Register (offset = 34h) [reset = 0h]
16.5.3.9 USB1IRQENABLESET0 Register (offset = 38h) [reset = 0h]
16.5.3.10 USB1IRQENABLESET1 Register (offset = 3Ch) [reset = 0h]
16.5.3.11 USB1IRQENABLECLR0 Register (offset = 40h) [reset = 0h]
16.5.3.12 USB1IRQENABLECLR1 Register (offset = 44h) [reset = 0h]
16.5.3.13 USB1TXMODE Register (offset = 70h) [reset = 0h]
16.5.3.14 USB1RXMODE Register (offset = 74h) [reset = 0h]
16.5.3.15 USB1GENRNDISEP1 Register (offset = 80h) [reset = 0h]
16.5.3.16 USB1GENRNDISEP2 Register (offset = 84h) [reset = 0h]
16.5.3.17 USB1GENRNDISEP3 Register (offset = 88h) [reset = 0h]
16.5.3.18 USB1GENRNDISEP4 Register (offset = 8Ch) [reset = 0h]
16.5.3.19 USB1GENRNDISEP5 Register (offset = 90h) [reset = 0h]
16.5.3.20 USB1GENRNDISEP6 Register (offset = 94h) [reset = 0h]
16.5.3.21 USB1GENRNDISEP7 Register (offset = 98h) [reset = 0h]
16.5.3.22 USB1GENRNDISEP8 Register (offset = 9Ch) [reset = 0h]
16.5.3.23 USB1GENRNDISEP9 Register (offset = A0h) [reset = 0h]
16.5.3.24 USB1GENRNDISEP10 Register (offset = A4h) [reset = 0h]
16.5.3.25 USB1GENRNDISEP11 Register (offset = A8h) [reset = 0h]
16.5.3.26 USB1GENRNDISEP12 Register (offset = ACh) [reset = 0h]
16.5.3.27 USB1GENRNDISEP13 Register (offset = B0h) [reset = 0h]
16.5.3.28 USB1GENRNDISEP14 Register (offset = B4h) [reset = 0h]
16.5.3.29 USB1GENRNDISEP15 Register (offset = B8h) [reset = 0h]
16.5.3.30 USB1AUTOREQ Register (offset = D0h) [reset = 0h]
16.5.3.31 USB1SRPFIXTIME Register (offset = D4h) [reset = 280DE80h]
16.5.3.32 USB1TDOWN Register (offset = D8h) [reset = 0h]
16.5.3.33 USB1UTMI Register (offset = E0h) [reset = 200002h]
16.5.3.34 USB1UTMILB Register (offset = E4h) [reset = 82h]
16.5.3.35 USB1MODE Register (offset = E8h) [reset = 100h]
16.5.4 USB2PHY Registers
16.5.4.1 Termination_control Register (offset = 0h) [reset = 1000800h]
16.5.4.2 RX_CALIB Register (offset = 4h) [reset = 0h]
16.5.4.3 DLLHS_2 Register (offset = 8h) [reset = 1Fh]
16.5.4.4 RX_TEST_2 Register (offset = Ch) [reset = 0h]
16.5.4.5 CHRG_DET Register (offset = 14h) [reset = 0h]
16.5.4.6 PWR_CNTL Register (offset = 18h) [reset = 400000h]
16.5.4.7 UTMI_INTERFACE_CNTL_1 Register (offset = 1Ch) [reset = 0h]
16.5.4.8 UTMI_INTERFACE_CNTL_2 Register (offset = 20h) [reset = 0h]
16.5.4.9 BIST Register (offset = 24h) [reset = 0h]
16.5.4.10 BIST_CRC Register (offset = 28h) [reset = 0h]
16.5.4.11 CDR_BIST2 Register (offset = 2Ch) [reset = 0h]
16.5.4.12 GPIO Register (offset = 30h) [reset = 0h]
16.5.4.13 DLLHS Register (offset = 34h) [reset = 8000h]
16.5.4.14 USB2PHYCM_TRIM Register (offset = 38h) [reset = 0h]
16.5.4.15 USB2PHYCM_CONFIG Register (offset = 3Ch) [reset = 0h]
16.5.4.16 USBOTG Register (offset = 40h) [reset = 0h]
16.5.4.17 AD_INTERFACE_REG1 Register (offset = 44h) [reset = 0h]
16.5.4.18 AD_INTERFACE_REG2 Register (offset = 48h) [reset = 0h]
16.5.4.19 AD_INTERFACE_REG3 Register (offset = 4Ch) [reset = 0h]
16.5.4.20 ANA_CONFIG1 Register (offset = 50h) [reset = 0h]
16.5.4.21 ANA_CONFIG2 Register (offset = 54h) [reset = 0h]
16.5.5 CPPI_DMA Registers
16.5.5.1 DMAREVID Register (offset = 0h) [reset = 530901h]
16.5.5.2 TDFDQ Register (offset = 4h) [reset = 0h]
16.5.5.3 DMAEMU Register (offset = 8h) [reset = 0h]
16.5.5.4 TXGCR0 Register (offset = 800h) [reset = 0h]
16.5.5.5 RXGCR0 Register (offset = 808h) [reset = 0h]
16.5.5.6 RXHPCRA0 Register (offset = 80Ch) [reset = 0h]
16.5.5.7 RXHPCRB0 Register (offset = 810h) [reset = 0h]
16.5.5.8 TXGCR1 Register (offset = 820h) [reset = 0h]
16.5.5.9 RXGCR1 Register (offset = 828h) [reset = 0h]
16.5.5.10 RXHPCRA1 Register (offset = 82Ch) [reset = 0h]
16.5.5.11 RXHPCRB1 Register (offset = 830h) [reset = 0h]
16.5.5.12 TXGCR2 Register (offset = 840h) [reset = 0h]
16.5.5.13 RXGCR2 Register (offset = 848h) [reset = 0h]
16.5.5.14 RXHPCRA2 Register (offset = 84Ch) [reset = 0h]
16.5.5.15 RXHPCRB2 Register (offset = 850h) [reset = 0h]
16.5.5.16 TXGCR3 Register (offset = 860h) [reset = 0h]
16.5.5.17 RXGCR3 Register (offset = 868h) [reset = 0h]
16.5.5.18 RXHPCRA3 Register (offset = 86Ch) [reset = 0h]
16.5.5.19 RXHPCRB3 Register (offset = 870h) [reset = 0h]
16.5.5.20 TXGCR4 Register (offset = 880h) [reset = 0h]
16.5.5.21 RXGCR4 Register (offset = 888h) [reset = 0h]
16.5.5.22 RXHPCRA4 Register (offset = 88Ch) [reset = 0h]
16.5.5.23 RXHPCRB4 Register (offset = 890h) [reset = 0h]
16.5.5.24 TXGCR5 Register (offset = 8A0h) [reset = 0h]
16.5.5.25 RXGCR5 Register (offset = 8A8h) [reset = 0h]
16.5.5.26 RXHPCRA5 Register (offset = 8ACh) [reset = 0h]
16.5.5.27 RXHPCRB5 Register (offset = 8B0h) [reset = 0h]
16.5.5.28 TXGCR6 Register (offset = 8C0h) [reset = 0h]
16.5.5.29 RXGCR6 Register (offset = 8C8h) [reset = 0h]
16.5.5.30 RXHPCRA6 Register (offset = 8CCh) [reset = 0h]
16.5.5.31 RXHPCRB6 Register (offset = 8D0h) [reset = 0h]
16.5.5.32 TXGCR7 Register (offset = 8E0h) [reset = 0h]
16.5.5.33 RXGCR7 Register (offset = 8E8h) [reset = 0h]
16.5.5.34 RXHPCRA7 Register (offset = 8ECh) [reset = 0h]
16.5.5.35 RXHPCRB7 Register (offset = 8F0h) [reset = 0h]
16.5.5.36 TXGCR8 Register (offset = 900h) [reset = 0h]
16.5.5.37 RXGCR8 Register (offset = 908h) [reset = 0h]
16.5.5.38 RXHPCRA8 Register (offset = 90Ch) [reset = 0h]
16.5.5.39 RXHPCRB8 Register (offset = 910h) [reset = 0h]
16.5.5.40 TXGCR9 Register (offset = 920h) [reset = 0h]
16.5.5.41 RXGCR9 Register (offset = 928h) [reset = 0h]
16.5.5.42 RXHPCRA9 Register (offset = 92Ch) [reset = 0h]
16.5.5.43 RXHPCRB9 Register (offset = 930h) [reset = 0h]
16.5.5.44 TXGCR10 Register (offset = 940h) [reset = 0h]
16.5.5.45 RXGCR10 Register (offset = 948h) [reset = 0h]
16.5.5.46 RXHPCRA10 Register (offset = 94Ch) [reset = 0h]
16.5.5.47 RXHPCRB10 Register (offset = 950h) [reset = 0h]
16.5.5.48 TXGCR11 Register (offset = 960h) [reset = 0h]
16.5.5.49 RXGCR11 Register (offset = 968h) [reset = 0h]
16.5.5.50 RXHPCRA11 Register (offset = 96Ch) [reset = 0h]
16.5.5.51 RXHPCRB11 Register (offset = 970h) [reset = 0h]
16.5.5.52 TXGCR12 Register (offset = 980h) [reset = 0h]
16.5.5.53 RXGCR12 Register (offset = 988h) [reset = 0h]
16.5.5.54 RXHPCRA12 Register (offset = 98Ch) [reset = 0h]
16.5.5.55 RXHPCRB12 Register (offset = 990h) [reset = 0h]
16.5.5.56 TXGCR13 Register (offset = 9A0h) [reset = 0h]
16.5.5.57 RXGCR13 Register (offset = 9A8h) [reset = 0h]
16.5.5.58 RXHPCRA13 Register (offset = 9ACh) [reset = 0h]
16.5.5.59 RXHPCRB13 Register (offset = 9B0h) [reset = 0h]
16.5.5.60 TXGCR14 Register (offset = 9C0h) [reset = 0h]
16.5.5.61 RXGCR14 Register (offset = 9C8h) [reset = 0h]
16.5.5.62 RXHPCRA14 Register (offset = 9CCh) [reset = 0h]
16.5.5.63 RXHPCRB14 Register (offset = 9D0h) [reset = 0h]
16.5.5.64 TXGCR15 Register (offset = 9E0h) [reset = 0h]
16.5.5.65 RXGCR15 Register (offset = 9E8h) [reset = 0h]
16.5.5.66 RXHPCRA15 Register (offset = 9ECh) [reset = 0h]
16.5.5.67 RXHPCRB15 Register (offset = 9F0h) [reset = 0h]
16.5.5.68 TXGCR16 Register (offset = A00h) [reset = 0h]
16.5.5.69 RXGCR16 Register (offset = A08h) [reset = 0h]
16.5.5.70 RXHPCRA16 Register (offset = A0Ch) [reset = 0h]
16.5.5.71 RXHPCRB16 Register (offset = A10h) [reset = 0h]
16.5.5.72 TXGCR17 Register (offset = A20h) [reset = 0h]
16.5.5.73 RXGCR17 Register (offset = A28h) [reset = 0h]
16.5.5.74 RXHPCRA17 Register (offset = A2Ch) [reset = 0h]
16.5.5.75 RXHPCRB17 Register (offset = A30h) [reset = 0h]
16.5.5.76 TXGCR18 Register (offset = A40h) [reset = 0h]
16.5.5.77 RXGCR18 Register (offset = A48h) [reset = 0h]
16.5.5.78 RXHPCRA18 Register (offset = A4Ch) [reset = 0h]
16.5.5.79 RXHPCRB18 Register (offset = A50h) [reset = 0h]
16.5.5.80 TXGCR19 Register (offset = A60h) [reset = 0h]
16.5.5.81 RXGCR19 Register (offset = A68h) [reset = 0h]
16.5.5.82 RXHPCRA19 Register (offset = A6Ch) [reset = 0h]
16.5.5.83 RXHPCRB19 Register (offset = A70h) [reset = 0h]
16.5.5.84 TXGCR20 Register (offset = A80h) [reset = 0h]
16.5.5.85 RXGCR20 Register (offset = A88h) [reset = 0h]
16.5.5.86 RXHPCRA20 Register (offset = A8Ch) [reset = 0h]
16.5.5.87 RXHPCRB20 Register (offset = A90h) [reset = 0h]
16.5.5.88 TXGCR21 Register (offset = AA0h) [reset = 0h]
16.5.5.89 RXGCR21 Register (offset = AA8h) [reset = 0h]
16.5.5.90 RXHPCRA21 Register (offset = AACh) [reset = 0h]
16.5.5.91 RXHPCRB21 Register (offset = AB0h) [reset = 0h]
16.5.5.92 TXGCR22 Register (offset = AC0h) [reset = 0h]
16.5.5.93 RXGCR22 Register (offset = AC8h) [reset = 0h]
16.5.5.94 RXHPCRA22 Register (offset = ACCh) [reset = 0h]
16.5.5.95 RXHPCRB22 Register (offset = AD0h) [reset = 0h]
16.5.5.96 TXGCR23 Register (offset = AE0h) [reset = 0h]
16.5.5.97 RXGCR23 Register (offset = AE8h) [reset = 0h]
16.5.5.98 RXHPCRA23 Register (offset = AECh) [reset = 0h]
16.5.5.99 RXHPCRB23 Register (offset = AF0h) [reset = 0h]
16.5.5.100 TXGCR24 Register (offset = B00h) [reset = 0h]
16.5.5.101 RXGCR24 Register (offset = B08h) [reset = 0h]
16.5.5.102 RXHPCRA24 Register (offset = B0Ch) [reset = 0h]
16.5.5.103 RXHPCRB24 Register (offset = B10h) [reset = 0h]
16.5.5.104 TXGCR25 Register (offset = B20h) [reset = 0h]
16.5.5.105 RXGCR25 Register (offset = B28h) [reset = 0h]
16.5.5.106 RXHPCRA25 Register (offset = B2Ch) [reset = 0h]
16.5.5.107 RXHPCRB25 Register (offset = B30h) [reset = 0h]
16.5.5.108 TXGCR26 Register (offset = B40h) [reset = 0h]
16.5.5.109 RXGCR26 Register (offset = B48h) [reset = 0h]
16.5.5.110 RXHPCRA26 Register (offset = B4Ch) [reset = 0h]
16.5.5.111 RXHPCRB26 Register (offset = B50h) [reset = 0h]
16.5.5.112 TXGCR27 Register (offset = B60h) [reset = 0h]
16.5.5.113 RXGCR27 Register (offset = B68h) [reset = 0h]
16.5.5.114 RXHPCRA27 Register (offset = B6Ch) [reset = 0h]
16.5.5.115 RXHPCRB27 Register (offset = B70h) [reset = 0h]
16.5.5.116 TXGCR28 Register (offset = B80h) [reset = 0h]
16.5.5.117 RXGCR28 Register (offset = B88h) [reset = 0h]
16.5.5.118 RXHPCRA28 Register (offset = B8Ch) [reset = 0h]
16.5.5.119 RXHPCRB28 Register (offset = B90h) [reset = 0h]
16.5.5.120 TXGCR29 Register (offset = BA0h) [reset = 0h]
16.5.5.121 RXGCR29 Register (offset = BA8h) [reset = 0h]
16.5.5.122 RXHPCRA29 Register (offset = BACh) [reset = 0h]
16.5.5.123 RXHPCRB29 Register (offset = BB0h) [reset = 0h]
16.5.6 CPPI_DMA_SCHEDULER Registers
16.5.6.1 DMA_SCHED_CTRL Register (offset = 0h) [reset = 0h]
16.5.6.2 WORD0 Register (offset = 800h) [reset = 0h]
16.5.6.3 WORD1 Register (offset = 804h) [reset = 0h]
16.5.6.4 WORD2 Register (offset = 808h) [reset = 0h]
16.5.6.5 WORD5 Register (offset = 814h) [reset = 0h]
16.5.6.6 WORD6 Register (offset = 818h) [reset = 0h]
16.5.6.7 WORD7 Register (offset = 81Ch) [reset = 0h]
16.5.6.8 WORD8 Register (offset = 820h) [reset = 0h]
16.5.6.9 WORD9 Register (offset = 824h) [reset = 0h]
16.5.6.10 WORD10 Register (offset = 828h) [reset = 0h]
16.5.6.11 WORD11 Register (offset = 82Ch) [reset = 0h]
16.5.6.12 WORD12 Register (offset = 830h) [reset = 0h]
16.5.6.13 WORD13 Register (offset = 834h) [reset = 0h]
16.5.6.14 WORD14 Register (offset = 838h) [reset = 0h]
16.5.6.15 WORD15 Register (offset = 83Ch) [reset = 0h]
16.5.6.16 WORD16 Register (offset = 840h) [reset = 0h]
16.5.6.17 WORD17 Register (offset = 844h) [reset = 0h]
16.5.6.18 WORD18 Register (offset = 848h) [reset = 0h]
16.5.6.19 WORD19 Register (offset = 84Ch) [reset = 0h]
16.5.6.20 WORD20 Register (offset = 850h) [reset = 0h]
16.5.6.21 WORD21 Register (offset = 854h) [reset = 0h]
16.5.6.22 WORD22 Register (offset = 858h) [reset = 0h]
16.5.6.23 WORD23 Register (offset = 85Ch) [reset = 0h]
16.5.6.24 WORD24 Register (offset = 860h) [reset = 0h]
16.5.6.25 WORD25 Register (offset = 864h) [reset = 0h]
16.5.6.26 WORD26 Register (offset = 868h) [reset = 0h]
16.5.6.27 WORD27 Register (offset = 86Ch) [reset = 0h]
16.5.6.28 WORD28 Register (offset = 870h) [reset = 0h]
16.5.6.29 WORD29 Register (offset = 874h) [reset = 0h]
16.5.6.30 WORD30 Register (offset = 878h) [reset = 0h]
16.5.6.31 WORD31 Register (offset = 87Ch) [reset = 0h]
16.5.6.32 WORD32 Register (offset = 880h) [reset = 0h]
16.5.6.33 WORD33 Register (offset = 884h) [reset = 0h]
16.5.6.34 WORD34 Register (offset = 888h) [reset = 0h]
16.5.6.35 WORD35 Register (offset = 88Ch) [reset = 0h]
16.5.6.36 WORD36 Register (offset = 890h) [reset = 0h]
16.5.6.37 WORD37 Register (offset = 894h) [reset = 0h]
16.5.6.38 WORD38 Register (offset = 898h) [reset = 0h]
16.5.6.39 WORD39 Register (offset = 89Ch) [reset = 0h]
16.5.6.40 WORD40 Register (offset = 8A0h) [reset = 0h]
16.5.6.41 WORD41 Register (offset = 8A4h) [reset = 0h]
16.5.6.42 WORD42 Register (offset = 8A8h) [reset = 0h]
16.5.6.43 WORD43 Register (offset = 8ACh) [reset = 0h]
16.5.6.44 WORD44 Register (offset = 8B0h) [reset = 0h]
16.5.6.45 WORD45 Register (offset = 8B4h) [reset = 0h]
16.5.6.46 WORD46 Register (offset = 8B8h) [reset = 0h]
16.5.6.47 WORD47 Register (offset = 8BCh) [reset = 0h]
16.5.6.48 WORD48 Register (offset = 8C0h) [reset = 0h]
16.5.6.49 WORD49 Register (offset = 8C4h) [reset = 0h]
16.5.6.50 WORD50 Register (offset = 8C8h) [reset = 0h]
16.5.6.51 WORD51 Register (offset = 8CCh) [reset = 0h]
16.5.6.52 WORD52 Register (offset = 8D0h) [reset = 0h]
16.5.6.53 WORD53 Register (offset = 8D4h) [reset = 0h]
16.5.6.54 WORD54 Register (offset = 8D8h) [reset = 0h]
16.5.6.55 WORD55 Register (offset = 8DCh) [reset = 0h]
16.5.6.56 WORD56 Register (offset = 8E0h) [reset = 0h]
16.5.6.57 WORD57 Register (offset = 8E4h) [reset = 0h]
16.5.6.58 WORD58 Register (offset = 8E8h) [reset = 0h]
16.5.6.59 WORD59 Register (offset = 8ECh) [reset = 0h]
16.5.6.60 WORD60 Register (offset = 8F0h) [reset = 0h]
16.5.6.61 WORD61 Register (offset = 8F4h) [reset = 0h]
16.5.6.62 WORD62 Register (offset = 8F8h) [reset = 0h]
16.5.6.63 WORD63 Register (offset = 8FCh) [reset = 0h]
16.5.7 QUEUE_MGR Registers
16.5.7.1 QMGRREVID Register (offset = 0h) [reset = 4E530800h]
16.5.7.2 QMGRRST Register (offset = 8h) [reset = 0h]
16.5.7.3 FDBSC0 Register (offset = 20h) [reset = 0h]
16.5.7.4 FDBSC1 Register (offset = 24h) [reset = 0h]
16.5.7.5 FDBSC2 Register (offset = 28h) [reset = 0h]
16.5.7.6 FDBSC3 Register (offset = 2Ch) [reset = 0h]
16.5.7.7 FDBSC4 Register (offset = 30h) [reset = 0h]
16.5.7.8 FDBSC5 Register (offset = 34h) [reset = 0h]
16.5.7.9 FDBSC6 Register (offset = 38h) [reset = 0h]
16.5.7.10 FDBSC7 Register (offset = 3Ch) [reset = 0h]
16.5.7.11 LRAM0BASE Register (offset = 80h) [reset = 0h]
16.5.7.12 LRAM0SIZE Register (offset = 84h) [reset = 0h]
16.5.7.13 LRAM1BASE Register (offset = 88h) [reset = 0h]
16.5.7.14 PEND0 Register (offset = 90h) [reset = 0h]
16.5.7.15 PEND1 Register (offset = 94h) [reset = 0h]
16.5.7.16 PEND2 Register (offset = 98h) [reset = 0h]
16.5.7.17 PEND3 Register (offset = 9Ch) [reset = 0h]
16.5.7.18 PEND4 Register (offset = A0h) [reset = 0h]
16.5.7.19 QMEMRBASE0 Register (offset = 1000h) [reset = 0h]
16.5.7.20 QMEMCTRL0 Register (offset = 1004h) [reset = 0h]
16.5.7.21 QMEMRBASE1 Register (offset = 1010h) [reset = 0h]
16.5.7.22 QMEMCTRL1 Register (offset = 1014h) [reset = 0h]
16.5.7.23 QMEMRBASE2 Register (offset = 1020h) [reset = 0h]
16.5.7.24 QMEMCTRL2 Register (offset = 1024h) [reset = 0h]
16.5.7.25 QMEMRBASE3 Register (offset = 1030h) [reset = 0h]
16.5.7.26 QMEMCTRL3 Register (offset = 1034h) [reset = 0h]
16.5.7.27 QMEMRBASE4 Register (offset = 1040h) [reset = 0h]
16.5.7.28 QMEMCTRL4 Register (offset = 1044h) [reset = 0h]
16.5.7.29 QMEMRBASE5 Register (offset = 1050h) [reset = 0h]
16.5.7.30 QMEMCTRL5 Register (offset = 1054h) [reset = 0h]
16.5.7.31 QMEMRBASE6 Register (offset = 1060h) [reset = 0h]
16.5.7.32 QMEMCTRL6 Register (offset = 1064h) [reset = 0h]
16.5.7.33 QMEMRBASE7 Register (offset = 1070h) [reset = 0h]
16.5.7.34 QMEMCTRL7 Register (offset = 1074h) [reset = 0h]
16.5.7.35 QUEUE_0_A Register (offset = 2000h) [reset = 0h]
16.5.7.36 QUEUE_0_B Register (offset = 2004h) [reset = 0h]
16.5.7.37 QUEUE_0_C Register (offset = 2008h) [reset = 0h]
16.5.7.38 QUEUE_0_D Register (offset = 200Ch) [reset = 0h]
16.5.7.39 QUEUE_1_A Register (offset = 2010h) [reset = 0h]
16.5.7.40 QUEUE_1_B Register (offset = 2014h) [reset = 0h]
16.5.7.41 QUEUE_1_C Register (offset = 2018h) [reset = 0h]
16.5.7.42 QUEUE_1_D Register (offset = 201Ch) [reset = 0h]
16.5.7.43 QUEUE_2_A Register (offset = 2020h) [reset = 0h]
16.5.7.44 QUEUE_2_B Register (offset = 2024h) [reset = 0h]
16.5.7.45 QUEUE_2_C Register (offset = 2028h) [reset = 0h]
16.5.7.46 QUEUE_2_D Register (offset = 202Ch) [reset = 0h]
16.5.7.47 QUEUE_3_A Register (offset = 2030h) [reset = 0h]
16.5.7.48 QUEUE_3_B Register (offset = 2034h) [reset = 0h]
16.5.7.49 QUEUE_3_C Register (offset = 2038h) [reset = 0h]
16.5.7.50 QUEUE_3_D Register (offset = 203Ch) [reset = 0h]
16.5.7.51 QUEUE_4_A Register (offset = 2040h) [reset = 0h]
16.5.7.52 QUEUE_4_B Register (offset = 2044h) [reset = 0h]
16.5.7.53 QUEUE_4_C Register (offset = 2048h) [reset = 0h]
16.5.7.54 QUEUE_4_D Register (offset = 204Ch) [reset = 0h]
16.5.7.55 QUEUE_5_A Register (offset = 2050h) [reset = 0h]
16.5.7.56 QUEUE_5_B Register (offset = 2054h) [reset = 0h]
16.5.7.57 QUEUE_5_C Register (offset = 2058h) [reset = 0h]
16.5.7.58 QUEUE_5_D Register (offset = 205Ch) [reset = 0h]
16.5.7.59 QUEUE_6_A Register (offset = 2060h) [reset = 0h]
16.5.7.60 QUEUE_6_B Register (offset = 2064h) [reset = 0h]
16.5.7.61 QUEUE_6_C Register (offset = 2068h) [reset = 0h]
16.5.7.62 QUEUE_6_D Register (offset = 206Ch) [reset = 0h]
16.5.7.63 QUEUE_7_A Register (offset = 2070h) [reset = 0h]
16.5.7.64 QUEUE_7_B Register (offset = 2074h) [reset = 0h]
16.5.7.65 QUEUE_7_C Register (offset = 2078h) [reset = 0h]
16.5.7.66 QUEUE_7_D Register (offset = 207Ch) [reset = 0h]
16.5.7.67 QUEUE_8_A Register (offset = 2080h) [reset = 0h]
16.5.7.68 QUEUE_8_B Register (offset = 2084h) [reset = 0h]
16.5.7.69 QUEUE_8_C Register (offset = 2088h) [reset = 0h]
16.5.7.70 QUEUE_8_D Register (offset = 208Ch) [reset = 0h]
16.5.7.71 QUEUE_9_A Register (offset = 2090h) [reset = 0h]
16.5.7.72 QUEUE_9_B Register (offset = 2094h) [reset = 0h]
16.5.7.73 QUEUE_9_C Register (offset = 2098h) [reset = 0h]
16.5.7.74 QUEUE_9_D Register (offset = 209Ch) [reset = 0h]
16.5.7.75 QUEUE_10_A Register (offset = 20A0h) [reset = 0h]
16.5.7.76 QUEUE_10_B Register (offset = 20A4h) [reset = 0h]
16.5.7.77 QUEUE_10_C Register (offset = 20A8h) [reset = 0h]
16.5.7.78 QUEUE_10_D Register (offset = 20ACh) [reset = 0h]
16.5.7.79 QUEUE_11_A Register (offset = 20B0h) [reset = 0h]
16.5.7.80 QUEUE_11_B Register (offset = 20B4h) [reset = 0h]
16.5.7.81 QUEUE_11_C Register (offset = 20B8h) [reset = 0h]
16.5.7.82 QUEUE_11_D Register (offset = 20BCh) [reset = 0h]
16.5.7.83 QUEUE_12_A Register (offset = 20C0h) [reset = 0h]
16.5.7.84 QUEUE_12_B Register (offset = 20C4h) [reset = 0h]
16.5.7.85 QUEUE_12_C Register (offset = 20C8h) [reset = 0h]
16.5.7.86 QUEUE_12_D Register (offset = 20CCh) [reset = 0h]
16.5.7.87 QUEUE_13_A Register (offset = 20D0h) [reset = 0h]
16.5.7.88 QUEUE_13_B Register (offset = 20D4h) [reset = 0h]
16.5.7.89 QUEUE_13_C Register (offset = 20D8h) [reset = 0h]
16.5.7.90 QUEUE_13_D Register (offset = 20DCh) [reset = 0h]
16.5.7.91 QUEUE_14_A Register (offset = 20E0h) [reset = 0h]
16.5.7.92 QUEUE_14_B Register (offset = 20E4h) [reset = 0h]
16.5.7.93 QUEUE_14_C Register (offset = 20E8h) [reset = 0h]
16.5.7.94 QUEUE_14_D Register (offset = 20ECh) [reset = 0h]
16.5.7.95 QUEUE_15_A Register (offset = 20F0h) [reset = 0h]
16.5.7.96 QUEUE_15_B Register (offset = 20F4h) [reset = 0h]
16.5.7.97 QUEUE_15_C Register (offset = 20F8h) [reset = 0h]
16.5.7.98 QUEUE_15_D Register (offset = 20FCh) [reset = 0h]
16.5.7.99 QUEUE_16_A Register (offset = 2100h) [reset = 0h]
16.5.7.100 QUEUE_16_B Register (offset = 2104h) [reset = 0h]
16.5.7.101 QUEUE_16_C Register (offset = 2108h) [reset = 0h]
16.5.7.102 QUEUE_16_D Register (offset = 210Ch) [reset = 0h]
16.5.7.103 QUEUE_17_A Register (offset = 2110h) [reset = 0h]
16.5.7.104 QUEUE_17_B Register (offset = 2114h) [reset = 0h]
16.5.7.105 QUEUE_17_C Register (offset = 2118h) [reset = 0h]
16.5.7.106 QUEUE_17_D Register (offset = 211Ch) [reset = 0h]
16.5.7.107 QUEUE_18_A Register (offset = 2120h) [reset = 0h]
16.5.7.108 QUEUE_18_B Register (offset = 2124h) [reset = 0h]
16.5.7.109 QUEUE_18_C Register (offset = 2128h) [reset = 0h]
16.5.7.110 QUEUE_18_D Register (offset = 212Ch) [reset = 0h]
16.5.7.111 QUEUE_19_A Register (offset = 2130h) [reset = 0h]
16.5.7.112 QUEUE_19_B Register (offset = 2134h) [reset = 0h]
16.5.7.113 QUEUE_19_C Register (offset = 2138h) [reset = 0h]
16.5.7.114 QUEUE_19_D Register (offset = 213Ch) [reset = 0h]
16.5.7.115 QUEUE_20_A Register (offset = 2140h) [reset = 0h]
16.5.7.116 QUEUE_20_B Register (offset = 2144h) [reset = 0h]
16.5.7.117 QUEUE_20_C Register (offset = 2148h) [reset = 0h]
16.5.7.118 QUEUE_20_D Register (offset = 214Ch) [reset = 0h]
16.5.7.119 QUEUE_21_A Register (offset = 2150h) [reset = 0h]
16.5.7.120 QUEUE_21_B Register (offset = 2154h) [reset = 0h]
16.5.7.121 QUEUE_21_C Register (offset = 2158h) [reset = 0h]
16.5.7.122 QUEUE_21_D Register (offset = 215Ch) [reset = 0h]
16.5.7.123 QUEUE_22_A Register (offset = 2160h) [reset = 0h]
16.5.7.124 QUEUE_22_B Register (offset = 2164h) [reset = 0h]
16.5.7.125 QUEUE_22_C Register (offset = 2168h) [reset = 0h]
16.5.7.126 QUEUE_22_D Register (offset = 216Ch) [reset = 0h]
16.5.7.127 QUEUE_23_A Register (offset = 2170h) [reset = 0h]
16.5.7.128 QUEUE_23_B Register (offset = 2174h) [reset = 0h]
16.5.7.129 QUEUE_23_C Register (offset = 2178h) [reset = 0h]
16.5.7.130 QUEUE_23_D Register (offset = 217Ch) [reset = 0h]
16.5.7.131 QUEUE_24_A Register (offset = 2180h) [reset = 0h]
16.5.7.132 QUEUE_24_B Register (offset = 2184h) [reset = 0h]
16.5.7.133 QUEUE_24_C Register (offset = 2188h) [reset = 0h]
16.5.7.134 QUEUE_24_D Register (offset = 218Ch) [reset = 0h]
16.5.7.135 QUEUE_25_A Register (offset = 2190h) [reset = 0h]
16.5.7.136 QUEUE_25_B Register (offset = 2194h) [reset = 0h]
16.5.7.137 QUEUE_25_C Register (offset = 2198h) [reset = 0h]
16.5.7.138 QUEUE_25_D Register (offset = 219Ch) [reset = 0h]
16.5.7.139 QUEUE_26_A Register (offset = 21A0h) [reset = 0h]
16.5.7.140 QUEUE_26_B Register (offset = 21A4h) [reset = 0h]
16.5.7.141 QUEUE_26_C Register (offset = 21A8h) [reset = 0h]
16.5.7.142 QUEUE_26_D Register (offset = 21ACh) [reset = 0h]
16.5.7.143 QUEUE_27_A Register (offset = 21B0h) [reset = 0h]
16.5.7.144 QUEUE_27_B Register (offset = 21B4h) [reset = 0h]
16.5.7.145 QUEUE_27_C Register (offset = 21B8h) [reset = 0h]
16.5.7.146 QUEUE_27_D Register (offset = 21BCh) [reset = 0h]
16.5.7.147 QUEUE_28_A Register (offset = 21C0h) [reset = 0h]
16.5.7.148 QUEUE_28_B Register (offset = 21C4h) [reset = 0h]
16.5.7.149 QUEUE_28_C Register (offset = 21C8h) [reset = 0h]
16.5.7.150 QUEUE_28_D Register (offset = 21CCh) [reset = 0h]
16.5.7.151 QUEUE_29_A Register (offset = 21D0h) [reset = 0h]
16.5.7.152 QUEUE_29_B Register (offset = 21D4h) [reset = 0h]
16.5.7.153 QUEUE_29_C Register (offset = 21D8h) [reset = 0h]
16.5.7.154 QUEUE_29_D Register (offset = 21DCh) [reset = 0h]
16.5.7.155 QUEUE_30_A Register (offset = 21E0h) [reset = 0h]
16.5.7.156 QUEUE_30_B Register (offset = 21E4h) [reset = 0h]
16.5.7.157 QUEUE_30_C Register (offset = 21E8h) [reset = 0h]
16.5.7.158 QUEUE_30_D Register (offset = 21ECh) [reset = 0h]
16.5.7.159 QUEUE_31_A Register (offset = 21F0h) [reset = 0h]
16.5.7.160 QUEUE_31_B Register (offset = 21F4h) [reset = 0h]
16.5.7.161 QUEUE_31_C Register (offset = 21F8h) [reset = 0h]
16.5.7.162 QUEUE_31_D Register (offset = 21FCh) [reset = 0h]
16.5.7.163 QUEUE_32_A Register (offset = 2200h) [reset = 0h]
16.5.7.164 QUEUE_32_B Register (offset = 2204h) [reset = 0h]
16.5.7.165 QUEUE_32_C Register (offset = 2208h) [reset = 0h]
16.5.7.166 QUEUE_32_D Register (offset = 220Ch) [reset = 0h]
16.5.7.167 QUEUE_33_A Register (offset = 2210h) [reset = 0h]
16.5.7.168 QUEUE_33_B Register (offset = 2214h) [reset = 0h]
16.5.7.169 QUEUE_33_C Register (offset = 2218h) [reset = 0h]
16.5.7.170 QUEUE_33_D Register (offset = 221Ch) [reset = 0h]
16.5.7.171 QUEUE_34_A Register (offset = 2220h) [reset = 0h]
16.5.7.172 QUEUE_34_B Register (offset = 2224h) [reset = 0h]
16.5.7.173 QUEUE_34_C Register (offset = 2228h) [reset = 0h]
16.5.7.174 QUEUE_34_D Register (offset = 222Ch) [reset = 0h]
16.5.7.175 QUEUE_35_A Register (offset = 2230h) [reset = 0h]
16.5.7.176 QUEUE_35_B Register (offset = 2234h) [reset = 0h]
16.5.7.177 QUEUE_35_C Register (offset = 2238h) [reset = 0h]
16.5.7.178 QUEUE_35_D Register (offset = 223Ch) [reset = 0h]
16.5.7.179 QUEUE_36_A Register (offset = 2240h) [reset = 0h]
16.5.7.180 QUEUE_36_B Register (offset = 2244h) [reset = 0h]
16.5.7.181 QUEUE_36_C Register (offset = 2248h) [reset = 0h]
16.5.7.182 QUEUE_36_D Register (offset = 224Ch) [reset = 0h]
16.5.7.183 QUEUE_37_A Register (offset = 2250h) [reset = 0h]
16.5.7.184 QUEUE_37_B Register (offset = 2254h) [reset = 0h]
16.5.7.185 QUEUE_37_C Register (offset = 2258h) [reset = 0h]
16.5.7.186 QUEUE_37_D Register (offset = 225Ch) [reset = 0h]
16.5.7.187 QUEUE_38_A Register (offset = 2260h) [reset = 0h]
16.5.7.188 QUEUE_38_B Register (offset = 2264h) [reset = 0h]
16.5.7.189 QUEUE_38_C Register (offset = 2268h) [reset = 0h]
16.5.7.190 QUEUE_38_D Register (offset = 226Ch) [reset = 0h]
16.5.7.191 QUEUE_39_A Register (offset = 2270h) [reset = 0h]
16.5.7.192 QUEUE_39_B Register (offset = 2274h) [reset = 0h]
16.5.7.193 QUEUE_39_C Register (offset = 2278h) [reset = 0h]
16.5.7.194 QUEUE_39_D Register (offset = 227Ch) [reset = 0h]
16.5.7.195 QUEUE_40_A Register (offset = 2280h) [reset = 0h]
16.5.7.196 QUEUE_40_B Register (offset = 2284h) [reset = 0h]
16.5.7.197 QUEUE_40_C Register (offset = 2288h) [reset = 0h]
16.5.7.198 QUEUE_40_D Register (offset = 228Ch) [reset = 0h]
16.5.7.199 QUEUE_41_A Register (offset = 2290h) [reset = 0h]
16.5.7.200 QUEUE_41_B Register (offset = 2294h) [reset = 0h]
16.5.7.201 QUEUE_41_C Register (offset = 2298h) [reset = 0h]
16.5.7.202 QUEUE_41_D Register (offset = 229Ch) [reset = 0h]
16.5.7.203 QUEUE_42_A Register (offset = 22A0h) [reset = 0h]
16.5.7.204 QUEUE_42_B Register (offset = 22A4h) [reset = 0h]
16.5.7.205 QUEUE_42_C Register (offset = 22A8h) [reset = 0h]
16.5.7.206 QUEUE_42_D Register (offset = 22ACh) [reset = 0h]
16.5.7.207 QUEUE_43_A Register (offset = 22B0h) [reset = 0h]
16.5.7.208 QUEUE_43_B Register (offset = 22B4h) [reset = 0h]
16.5.7.209 QUEUE_43_C Register (offset = 22B8h) [reset = 0h]
16.5.7.210 QUEUE_43_D Register (offset = 22BCh) [reset = 0h]
16.5.7.211 QUEUE_44_A Register (offset = 22C0h) [reset = 0h]
16.5.7.212 QUEUE_44_B Register (offset = 22C4h) [reset = 0h]
16.5.7.213 QUEUE_44_C Register (offset = 22C8h) [reset = 0h]
16.5.7.214 QUEUE_44_D Register (offset = 22CCh) [reset = 0h]
16.5.7.215 QUEUE_45_A Register (offset = 22D0h) [reset = 0h]
16.5.7.216 QUEUE_45_B Register (offset = 22D4h) [reset = 0h]
16.5.7.217 QUEUE_45_C Register (offset = 22D8h) [reset = 0h]
16.5.7.218 QUEUE_45_D Register (offset = 22DCh) [reset = 0h]
16.5.7.219 QUEUE_46_A Register (offset = 22E0h) [reset = 0h]
16.5.7.220 QUEUE_46_B Register (offset = 22E4h) [reset = 0h]
16.5.7.221 QUEUE_46_C Register (offset = 22E8h) [reset = 0h]
16.5.7.222 QUEUE_46_D Register (offset = 22ECh) [reset = 0h]
16.5.7.223 QUEUE_47_A Register (offset = 22F0h) [reset = 0h]
16.5.7.224 QUEUE_47_B Register (offset = 22F4h) [reset = 0h]
16.5.7.225 QUEUE_47_C Register (offset = 22F8h) [reset = 0h]
16.5.7.226 QUEUE_47_D Register (offset = 22FCh) [reset = 0h]
16.5.7.227 QUEUE_48_A Register (offset = 2300h) [reset = 0h]
16.5.7.228 QUEUE_48_B Register (offset = 2304h) [reset = 0h]
16.5.7.229 QUEUE_48_C Register (offset = 2308h) [reset = 0h]
16.5.7.230 QUEUE_48_D Register (offset = 230Ch) [reset = 0h]
16.5.7.231 QUEUE_49_A Register (offset = 2310h) [reset = 0h]
16.5.7.232 QUEUE_49_B Register (offset = 2314h) [reset = 0h]
16.5.7.233 QUEUE_49_C Register (offset = 2318h) [reset = 0h]
16.5.7.234 QUEUE_49_D Register (offset = 231Ch) [reset = 0h]
16.5.7.235 QUEUE_50_A Register (offset = 2320h) [reset = 0h]
16.5.7.236 QUEUE_50_B Register (offset = 2324h) [reset = 0h]
16.5.7.237 QUEUE_50_C Register (offset = 2328h) [reset = 0h]
16.5.7.238 QUEUE_50_D Register (offset = 232Ch) [reset = 0h]
16.5.7.239 QUEUE_51_A Register (offset = 2330h) [reset = 0h]
16.5.7.240 QUEUE_51_B Register (offset = 2334h) [reset = 0h]
16.5.7.241 QUEUE_51_C Register (offset = 2338h) [reset = 0h]
16.5.7.242 QUEUE_51_D Register (offset = 233Ch) [reset = 0h]
16.5.7.243 QUEUE_52_A Register (offset = 2340h) [reset = 0h]
16.5.7.244 QUEUE_52_B Register (offset = 2344h) [reset = 0h]
16.5.7.245 QUEUE_52_C Register (offset = 2348h) [reset = 0h]
16.5.7.246 QUEUE_52_D Register (offset = 234Ch) [reset = 0h]
16.5.7.247 QUEUE_53_A Register (offset = 2350h) [reset = 0h]
16.5.7.248 QUEUE_53_B Register (offset = 2354h) [reset = 0h]
16.5.7.249 QUEUE_53_C Register (offset = 2358h) [reset = 0h]
16.5.7.250 QUEUE_53_D Register (offset = 235Ch) [reset = 0h]
16.5.7.251 QUEUE_54_A Register (offset = 2360h) [reset = 0h]
16.5.7.252 QUEUE_54_B Register (offset = 2364h) [reset = 0h]
16.5.7.253 QUEUE_54_C Register (offset = 2368h) [reset = 0h]
16.5.7.254 QUEUE_54_D Register (offset = 236Ch) [reset = 0h]
16.5.7.255 QUEUE_55_A Register (offset = 2370h) [reset = 0h]
16.5.7.256 QUEUE_55_B Register (offset = 2374h) [reset = 0h]
16.5.7.257 QUEUE_55_C Register (offset = 2378h) [reset = 0h]
16.5.7.258 QUEUE_55_D Register (offset = 237Ch) [reset = 0h]
16.5.7.259 QUEUE_56_A Register (offset = 2380h) [reset = 0h]
16.5.7.260 QUEUE_56_B Register (offset = 2384h) [reset = 0h]
16.5.7.261 QUEUE_56_C Register (offset = 2388h) [reset = 0h]
16.5.7.262 QUEUE_56_D Register (offset = 238Ch) [reset = 0h]
16.5.7.263 QUEUE_57_A Register (offset = 2390h) [reset = 0h]
16.5.7.264 QUEUE_57_B Register (offset = 2394h) [reset = 0h]
16.5.7.265 QUEUE_57_C Register (offset = 2398h) [reset = 0h]
16.5.7.266 QUEUE_57_D Register (offset = 239Ch) [reset = 0h]
16.5.7.267 QUEUE_58_A Register (offset = 23A0h) [reset = 0h]
16.5.7.268 QUEUE_58_B Register (offset = 23A4h) [reset = 0h]
16.5.7.269 QUEUE_58_C Register (offset = 23A8h) [reset = 0h]
16.5.7.270 QUEUE_58_D Register (offset = 23ACh) [reset = 0h]
16.5.7.271 QUEUE_59_A Register (offset = 23B0h) [reset = 0h]
16.5.7.272 QUEUE_59_B Register (offset = 23B4h) [reset = 0h]
16.5.7.273 QUEUE_59_C Register (offset = 23B8h) [reset = 0h]
16.5.7.274 QUEUE_59_D Register (offset = 23BCh) [reset = 0h]
16.5.7.275 QUEUE_60_A Register (offset = 23C0h) [reset = 0h]
16.5.7.276 QUEUE_60_B Register (offset = 23C4h) [reset = 0h]
16.5.7.277 QUEUE_60_C Register (offset = 23C8h) [reset = 0h]
16.5.7.278 QUEUE_60_D Register (offset = 23CCh) [reset = 0h]
16.5.7.279 QUEUE_61_A Register (offset = 23D0h) [reset = 0h]
16.5.7.280 QUEUE_61_B Register (offset = 23D4h) [reset = 0h]
16.5.7.281 QUEUE_61_C Register (offset = 23D8h) [reset = 0h]
16.5.7.282 QUEUE_61_D Register (offset = 23DCh) [reset = 0h]
16.5.7.283 QUEUE_62_A Register (offset = 23E0h) [reset = 0h]
16.5.7.284 QUEUE_62_B Register (offset = 23E4h) [reset = 0h]
16.5.7.285 QUEUE_62_C Register (offset = 23E8h) [reset = 0h]
16.5.7.286 QUEUE_62_D Register (offset = 23ECh) [reset = 0h]
16.5.7.287 QUEUE_63_A Register (offset = 23F0h) [reset = 0h]
16.5.7.288 QUEUE_63_B Register (offset = 23F4h) [reset = 0h]
16.5.7.289 QUEUE_63_C Register (offset = 23F8h) [reset = 0h]
16.5.7.290 QUEUE_63_D Register (offset = 23FCh) [reset = 0h]
16.5.7.291 QUEUE_64_A Register (offset = 2400h) [reset = 0h]
16.5.7.292 QUEUE_64_B Register (offset = 2404h) [reset = 0h]
16.5.7.293 QUEUE_64_C Register (offset = 2408h) [reset = 0h]
16.5.7.294 QUEUE_64_D Register (offset = 240Ch) [reset = 0h]
16.5.7.295 QUEUE_65_A Register (offset = 2410h) [reset = 0h]
16.5.7.296 QUEUE_65_B Register (offset = 2414h) [reset = 0h]
16.5.7.297 QUEUE_65_C Register (offset = 2418h) [reset = 0h]
16.5.7.298 QUEUE_65_D Register (offset = 241Ch) [reset = 0h]
16.5.7.299 QUEUE_66_A Register (offset = 2420h) [reset = 0h]
16.5.7.300 QUEUE_66_B Register (offset = 2424h) [reset = 0h]
16.5.7.301 QUEUE_66_C Register (offset = 2428h) [reset = 0h]
16.5.7.302 QUEUE_66_D Register (offset = 242Ch) [reset = 0h]
16.5.7.303 QUEUE_67_A Register (offset = 2430h) [reset = 0h]
16.5.7.304 QUEUE_67_B Register (offset = 2434h) [reset = 0h]
16.5.7.305 QUEUE_67_C Register (offset = 2438h) [reset = 0h]
16.5.7.306 QUEUE_67_D Register (offset = 243Ch) [reset = 0h]
16.5.7.307 QUEUE_68_A Register (offset = 2440h) [reset = 0h]
16.5.7.308 QUEUE_68_B Register (offset = 2444h) [reset = 0h]
16.5.7.309 QUEUE_68_C Register (offset = 2448h) [reset = 0h]
16.5.7.310 QUEUE_68_D Register (offset = 244Ch) [reset = 0h]
16.5.7.311 QUEUE_69_A Register (offset = 2450h) [reset = 0h]
16.5.7.312 QUEUE_69_B Register (offset = 2454h) [reset = 0h]
16.5.7.313 QUEUE_69_C Register (offset = 2458h) [reset = 0h]
16.5.7.314 QUEUE_69_D Register (offset = 245Ch) [reset = 0h]
16.5.7.315 QUEUE_70_A Register (offset = 2460h) [reset = 0h]
16.5.7.316 QUEUE_70_B Register (offset = 2464h) [reset = 0h]
16.5.7.317 QUEUE_70_C Register (offset = 2468h) [reset = 0h]
16.5.7.318 QUEUE_70_D Register (offset = 246Ch) [reset = 0h]
16.5.7.319 QUEUE_71_A Register (offset = 2470h) [reset = 0h]
16.5.7.320 QUEUE_71_B Register (offset = 2474h) [reset = 0h]
16.5.7.321 QUEUE_71_C Register (offset = 2478h) [reset = 0h]
16.5.7.322 QUEUE_71_D Register (offset = 247Ch) [reset = 0h]
16.5.7.323 QUEUE_72_A Register (offset = 2480h) [reset = 0h]
16.5.7.324 QUEUE_72_B Register (offset = 2484h) [reset = 0h]
16.5.7.325 QUEUE_72_C Register (offset = 2488h) [reset = 0h]
16.5.7.326 QUEUE_72_D Register (offset = 248Ch) [reset = 0h]
16.5.7.327 QUEUE_73_A Register (offset = 2490h) [reset = 0h]
16.5.7.328 QUEUE_73_B Register (offset = 2494h) [reset = 0h]
16.5.7.329 QUEUE_73_C Register (offset = 2498h) [reset = 0h]
16.5.7.330 QUEUE_73_D Register (offset = 249Ch) [reset = 0h]
16.5.7.331 QUEUE_74_A Register (offset = 24A0h) [reset = 0h]
16.5.7.332 QUEUE_74_B Register (offset = 24A4h) [reset = 0h]
16.5.7.333 QUEUE_74_C Register (offset = 24A8h) [reset = 0h]
16.5.7.334 QUEUE_74_D Register (offset = 24ACh) [reset = 0h]
16.5.7.335 QUEUE_75_A Register (offset = 24B0h) [reset = 0h]
16.5.7.336 QUEUE_75_B Register (offset = 24B4h) [reset = 0h]
16.5.7.337 QUEUE_75_C Register (offset = 24B8h) [reset = 0h]
16.5.7.338 QUEUE_75_D Register (offset = 24BCh) [reset = 0h]
16.5.7.339 QUEUE_76_A Register (offset = 24C0h) [reset = 0h]
16.5.7.340 QUEUE_76_B Register (offset = 24C4h) [reset = 0h]
16.5.7.341 QUEUE_76_C Register (offset = 24C8h) [reset = 0h]
16.5.7.342 QUEUE_76_D Register (offset = 24CCh) [reset = 0h]
16.5.7.343 QUEUE_77_A Register (offset = 24D0h) [reset = 0h]
16.5.7.344 QUEUE_77_B Register (offset = 24D4h) [reset = 0h]
16.5.7.345 QUEUE_77_C Register (offset = 24D8h) [reset = 0h]
16.5.7.346 QUEUE_77_D Register (offset = 24DCh) [reset = 0h]
16.5.7.347 QUEUE_78_A Register (offset = 24E0h) [reset = 0h]
16.5.7.348 QUEUE_78_B Register (offset = 24E4h) [reset = 0h]
16.5.7.349 QUEUE_78_C Register (offset = 24E8h) [reset = 0h]
16.5.7.350 QUEUE_78_D Register (offset = 24ECh) [reset = 0h]
16.5.7.351 QUEUE_79_A Register (offset = 24F0h) [reset = 0h]
16.5.7.352 QUEUE_79_B Register (offset = 24F4h) [reset = 0h]
16.5.7.353 QUEUE_79_C Register (offset = 24F8h) [reset = 0h]
16.5.7.354 QUEUE_79_D Register (offset = 24FCh) [reset = 0h]
16.5.7.355 QUEUE_80_A Register (offset = 2500h) [reset = 0h]
16.5.7.356 QUEUE_80_B Register (offset = 2504h) [reset = 0h]
16.5.7.357 QUEUE_80_C Register (offset = 2508h) [reset = 0h]
16.5.7.358 QUEUE_80_D Register (offset = 250Ch) [reset = 0h]
16.5.7.359 QUEUE_81_A Register (offset = 2510h) [reset = 0h]
16.5.7.360 QUEUE_81_B Register (offset = 2514h) [reset = 0h]
16.5.7.361 QUEUE_81_C Register (offset = 2518h) [reset = 0h]
16.5.7.362 QUEUE_81_D Register (offset = 251Ch) [reset = 0h]
16.5.7.363 QUEUE_82_A Register (offset = 2520h) [reset = 0h]
16.5.7.364 QUEUE_82_B Register (offset = 2524h) [reset = 0h]
16.5.7.365 QUEUE_82_C Register (offset = 2528h) [reset = 0h]
16.5.7.366 QUEUE_82_D Register (offset = 252Ch) [reset = 0h]
16.5.7.367 QUEUE_83_A Register (offset = 2530h) [reset = 0h]
16.5.7.368 QUEUE_83_B Register (offset = 2534h) [reset = 0h]
16.5.7.369 QUEUE_83_C Register (offset = 2538h) [reset = 0h]
16.5.7.370 QUEUE_83_D Register (offset = 253Ch) [reset = 0h]
16.5.7.371 QUEUE_84_A Register (offset = 2540h) [reset = 0h]
16.5.7.372 QUEUE_84_B Register (offset = 2544h) [reset = 0h]
16.5.7.373 QUEUE_84_C Register (offset = 2548h) [reset = 0h]
16.5.7.374 QUEUE_84_D Register (offset = 254Ch) [reset = 0h]
16.5.7.375 QUEUE_85_A Register (offset = 2550h) [reset = 0h]
16.5.7.376 QUEUE_85_B Register (offset = 2554h) [reset = 0h]
16.5.7.377 QUEUE_85_C Register (offset = 2558h) [reset = 0h]
16.5.7.378 QUEUE_85_D Register (offset = 255Ch) [reset = 0h]
16.5.7.379 QUEUE_86_A Register (offset = 2560h) [reset = 0h]
16.5.7.380 QUEUE_86_B Register (offset = 2564h) [reset = 0h]
16.5.7.381 QUEUE_86_C Register (offset = 2568h) [reset = 0h]
16.5.7.382 QUEUE_86_D Register (offset = 256Ch) [reset = 0h]
16.5.7.383 QUEUE_87_A Register (offset = 2570h) [reset = 0h]
16.5.7.384 QUEUE_87_B Register (offset = 2574h) [reset = 0h]
16.5.7.385 QUEUE_87_C Register (offset = 2578h) [reset = 0h]
16.5.7.386 QUEUE_87_D Register (offset = 257Ch) [reset = 0h]
16.5.7.387 QUEUE_88_A Register (offset = 2580h) [reset = 0h]
16.5.7.388 QUEUE_88_B Register (offset = 2584h) [reset = 0h]
16.5.7.389 QUEUE_88_C Register (offset = 2588h) [reset = 0h]
16.5.7.390 QUEUE_88_D Register (offset = 258Ch) [reset = 0h]
16.5.7.391 QUEUE_89_A Register (offset = 2590h) [reset = 0h]
16.5.7.392 QUEUE_89_B Register (offset = 2594h) [reset = 0h]
16.5.7.393 QUEUE_89_C Register (offset = 2598h) [reset = 0h]
16.5.7.394 QUEUE_89_D Register (offset = 259Ch) [reset = 0h]
16.5.7.395 QUEUE_90_A Register (offset = 25A0h) [reset = 0h]
16.5.7.396 QUEUE_90_B Register (offset = 25A4h) [reset = 0h]
16.5.7.397 QUEUE_90_C Register (offset = 25A8h) [reset = 0h]
16.5.7.398 QUEUE_90_D Register (offset = 25ACh) [reset = 0h]
16.5.7.399 QUEUE_91_A Register (offset = 25B0h) [reset = 0h]
16.5.7.400 QUEUE_91_B Register (offset = 25B4h) [reset = 0h]
16.5.7.401 QUEUE_91_C Register (offset = 25B8h) [reset = 0h]
16.5.7.402 QUEUE_91_D Register (offset = 25BCh) [reset = 0h]
16.5.7.403 QUEUE_92_A Register (offset = 25C0h) [reset = 0h]
16.5.7.404 QUEUE_92_B Register (offset = 25C4h) [reset = 0h]
16.5.7.405 QUEUE_92_C Register (offset = 25C8h) [reset = 0h]
16.5.7.406 QUEUE_92_D Register (offset = 25CCh) [reset = 0h]
16.5.7.407 QUEUE_93_A Register (offset = 25D0h) [reset = 0h]
16.5.7.408 QUEUE_93_B Register (offset = 25D4h) [reset = 0h]
16.5.7.409 QUEUE_93_C Register (offset = 25D8h) [reset = 0h]
16.5.7.410 QUEUE_93_D Register (offset = 25DCh) [reset = 0h]
16.5.7.411 QUEUE_94_A Register (offset = 25E0h) [reset = 0h]
16.5.7.412 QUEUE_94_B Register (offset = 25E4h) [reset = 0h]
16.5.7.413 QUEUE_94_C Register (offset = 25E8h) [reset = 0h]
16.5.7.414 QUEUE_94_D Register (offset = 25ECh) [reset = 0h]
16.5.7.415 QUEUE_95_A Register (offset = 25F0h) [reset = 0h]
16.5.7.416 QUEUE_95_B Register (offset = 25F4h) [reset = 0h]
16.5.7.417 QUEUE_95_C Register (offset = 25F8h) [reset = 0h]
16.5.7.418 QUEUE_95_D Register (offset = 25FCh) [reset = 0h]
16.5.7.419 QUEUE_96_A Register (offset = 2600h) [reset = 0h]
16.5.7.420 QUEUE_96_B Register (offset = 2604h) [reset = 0h]
16.5.7.421 QUEUE_96_C Register (offset = 2608h) [reset = 0h]
16.5.7.422 QUEUE_96_D Register (offset = 260Ch) [reset = 0h]
16.5.7.423 QUEUE_97_A Register (offset = 2610h) [reset = 0h]
16.5.7.424 QUEUE_97_B Register (offset = 2614h) [reset = 0h]
16.5.7.425 QUEUE_97_C Register (offset = 2618h) [reset = 0h]
16.5.7.426 QUEUE_97_D Register (offset = 261Ch) [reset = 0h]
16.5.7.427 QUEUE_98_A Register (offset = 2620h) [reset = 0h]
16.5.7.428 QUEUE_98_B Register (offset = 2624h) [reset = 0h]
16.5.7.429 QUEUE_98_C Register (offset = 2628h) [reset = 0h]
16.5.7.430 QUEUE_98_D Register (offset = 262Ch) [reset = 0h]
16.5.7.431 QUEUE_99_A Register (offset = 2630h) [reset = 0h]
16.5.7.432 QUEUE_99_B Register (offset = 2634h) [reset = 0h]
16.5.7.433 QUEUE_99_C Register (offset = 2638h) [reset = 0h]
16.5.7.434 QUEUE_99_D Register (offset = 263Ch) [reset = 0h]
16.5.7.435 QUEUE_100_A Register (offset = 2640h) [reset = 0h]
16.5.7.436 QUEUE_100_B Register (offset = 2644h) [reset = 0h]
16.5.7.437 QUEUE_100_C Register (offset = 2648h) [reset = 0h]
16.5.7.438 QUEUE_100_D Register (offset = 264Ch) [reset = 0h]
16.5.7.439 QUEUE_101_A Register (offset = 2650h) [reset = 0h]
16.5.7.440 QUEUE_101_B Register (offset = 2654h) [reset = 0h]
16.5.7.441 QUEUE_101_C Register (offset = 2658h) [reset = 0h]
16.5.7.442 QUEUE_101_D Register (offset = 265Ch) [reset = 0h]
16.5.7.443 QUEUE_102_A Register (offset = 2660h) [reset = 0h]
16.5.7.444 QUEUE_102_B Register (offset = 2664h) [reset = 0h]
16.5.7.445 QUEUE_102_C Register (offset = 2668h) [reset = 0h]
16.5.7.446 QUEUE_102_D Register (offset = 266Ch) [reset = 0h]
16.5.7.447 QUEUE_103_A Register (offset = 2670h) [reset = 0h]
16.5.7.448 QUEUE_103_B Register (offset = 2674h) [reset = 0h]
16.5.7.449 QUEUE_103_C Register (offset = 2678h) [reset = 0h]
16.5.7.450 QUEUE_103_D Register (offset = 267Ch) [reset = 0h]
16.5.7.451 QUEUE_104_A Register (offset = 2680h) [reset = 0h]
16.5.7.452 QUEUE_104_B Register (offset = 2684h) [reset = 0h]
16.5.7.453 QUEUE_104_C Register (offset = 2688h) [reset = 0h]
16.5.7.454 QUEUE_104_D Register (offset = 268Ch) [reset = 0h]
16.5.7.455 QUEUE_105_A Register (offset = 2690h) [reset = 0h]
16.5.7.456 QUEUE_105_B Register (offset = 2694h) [reset = 0h]
16.5.7.457 QUEUE_105_C Register (offset = 2698h) [reset = 0h]
16.5.7.458 QUEUE_105_D Register (offset = 269Ch) [reset = 0h]
16.5.7.459 QUEUE_106_A Register (offset = 26A0h) [reset = 0h]
16.5.7.460 QUEUE_106_B Register (offset = 26A4h) [reset = 0h]
16.5.7.461 QUEUE_106_C Register (offset = 26A8h) [reset = 0h]
16.5.7.462 QUEUE_106_D Register (offset = 26ACh) [reset = 0h]
16.5.7.463 QUEUE_107_A Register (offset = 26B0h) [reset = 0h]
16.5.7.464 QUEUE_107_B Register (offset = 26B4h) [reset = 0h]
16.5.7.465 QUEUE_107_C Register (offset = 26B8h) [reset = 0h]
16.5.7.466 QUEUE_107_D Register (offset = 26BCh) [reset = 0h]
16.5.7.467 QUEUE_108_A Register (offset = 26C0h) [reset = 0h]
16.5.7.468 QUEUE_108_B Register (offset = 26C4h) [reset = 0h]
16.5.7.469 QUEUE_108_C Register (offset = 26C8h) [reset = 0h]
16.5.7.470 QUEUE_108_D Register (offset = 26CCh) [reset = 0h]
16.5.7.471 QUEUE_109_A Register (offset = 26D0h) [reset = 0h]
16.5.7.472 QUEUE_109_B Register (offset = 26D4h) [reset = 0h]
16.5.7.473 QUEUE_109_C Register (offset = 26D8h) [reset = 0h]
16.5.7.474 QUEUE_109_D Register (offset = 26DCh) [reset = 0h]
16.5.7.475 QUEUE_110_A Register (offset = 26E0h) [reset = 0h]
16.5.7.476 QUEUE_110_B Register (offset = 26E4h) [reset = 0h]
16.5.7.477 QUEUE_110_C Register (offset = 26E8h) [reset = 0h]
16.5.7.478 QUEUE_110_D Register (offset = 26ECh) [reset = 0h]
16.5.7.479 QUEUE_111_A Register (offset = 26F0h) [reset = 0h]
16.5.7.480 QUEUE_111_B Register (offset = 26F4h) [reset = 0h]
16.5.7.481 QUEUE_111_C Register (offset = 26F8h) [reset = 0h]
16.5.7.482 QUEUE_111_D Register (offset = 26FCh) [reset = 0h]
16.5.7.483 QUEUE_112_A Register (offset = 2700h) [reset = 0h]
16.5.7.484 QUEUE_112_B Register (offset = 2704h) [reset = 0h]
16.5.7.485 QUEUE_112_C Register (offset = 2708h) [reset = 0h]
16.5.7.486 QUEUE_112_D Register (offset = 270Ch) [reset = 0h]
16.5.7.487 QUEUE_113_A Register (offset = 2710h) [reset = 0h]
16.5.7.488 QUEUE_113_B Register (offset = 2714h) [reset = 0h]
16.5.7.489 QUEUE_113_C Register (offset = 2718h) [reset = 0h]
16.5.7.490 QUEUE_113_D Register (offset = 271Ch) [reset = 0h]
16.5.7.491 QUEUE_114_A Register (offset = 2720h) [reset = 0h]
16.5.7.492 QUEUE_114_B Register (offset = 2724h) [reset = 0h]
16.5.7.493 QUEUE_114_C Register (offset = 2728h) [reset = 0h]
16.5.7.494 QUEUE_114_D Register (offset = 272Ch) [reset = 0h]
16.5.7.495 QUEUE_115_A Register (offset = 2730h) [reset = 0h]
16.5.7.496 QUEUE_115_B Register (offset = 2734h) [reset = 0h]
16.5.7.497 QUEUE_115_C Register (offset = 2738h) [reset = 0h]
16.5.7.498 QUEUE_115_D Register (offset = 273Ch) [reset = 0h]
16.5.7.499 QUEUE_116_A Register (offset = 2740h) [reset = 0h]
16.5.7.500 QUEUE_116_B Register (offset = 2744h) [reset = 0h]
16.5.7.501 QUEUE_116_C Register (offset = 2748h) [reset = 0h]
16.5.7.502 QUEUE_116_D Register (offset = 274Ch) [reset = 0h]
16.5.7.503 QUEUE_117_A Register (offset = 2750h) [reset = 0h]
16.5.7.504 QUEUE_117_B Register (offset = 2754h) [reset = 0h]
16.5.7.505 QUEUE_117_C Register (offset = 2758h) [reset = 0h]
16.5.7.506 QUEUE_117_D Register (offset = 275Ch) [reset = 0h]
16.5.7.507 QUEUE_118_A Register (offset = 2760h) [reset = 0h]
16.5.7.508 QUEUE_118_B Register (offset = 2764h) [reset = 0h]
16.5.7.509 QUEUE_118_C Register (offset = 2768h) [reset = 0h]
16.5.7.510 QUEUE_118_D Register (offset = 276Ch) [reset = 0h]
16.5.7.511 QUEUE_119_A Register (offset = 2770h) [reset = 0h]
16.5.7.512 QUEUE_119_B Register (offset = 2774h) [reset = 0h]
16.5.7.513 QUEUE_119_C Register (offset = 2778h) [reset = 0h]
16.5.7.514 QUEUE_119_D Register (offset = 277Ch) [reset = 0h]
16.5.7.515 QUEUE_120_A Register (offset = 2780h) [reset = 0h]
16.5.7.516 QUEUE_120_B Register (offset = 2784h) [reset = 0h]
16.5.7.517 QUEUE_120_C Register (offset = 2788h) [reset = 0h]
16.5.7.518 QUEUE_120_D Register (offset = 278Ch) [reset = 0h]
16.5.7.519 QUEUE_121_A Register (offset = 2790h) [reset = 0h]
16.5.7.520 QUEUE_121_B Register (offset = 2794h) [reset = 0h]
16.5.7.521 QUEUE_121_C Register (offset = 2798h) [reset = 0h]
16.5.7.522 QUEUE_121_D Register (offset = 279Ch) [reset = 0h]
16.5.7.523 QUEUE_122_A Register (offset = 27A0h) [reset = 0h]
16.5.7.524 QUEUE_122_B Register (offset = 27A4h) [reset = 0h]
16.5.7.525 QUEUE_122_C Register (offset = 27A8h) [reset = 0h]
16.5.7.526 QUEUE_122_D Register (offset = 27ACh) [reset = 0h]
16.5.7.527 QUEUE_123_A Register (offset = 27B0h) [reset = 0h]
16.5.7.528 QUEUE_123_B Register (offset = 27B4h) [reset = 0h]
16.5.7.529 QUEUE_123_C Register (offset = 27B8h) [reset = 0h]
16.5.7.530 QUEUE_123_D Register (offset = 27BCh) [reset = 0h]
16.5.7.531 QUEUE_124_A Register (offset = 27C0h) [reset = 0h]
16.5.7.532 QUEUE_124_B Register (offset = 27C4h) [reset = 0h]
16.5.7.533 QUEUE_124_C Register (offset = 27C8h) [reset = 0h]
16.5.7.534 QUEUE_124_D Register (offset = 27CCh) [reset = 0h]
16.5.7.535 QUEUE_125_A Register (offset = 27D0h) [reset = 0h]
16.5.7.536 QUEUE_125_B Register (offset = 27D4h) [reset = 0h]
16.5.7.537 QUEUE_125_C Register (offset = 27D8h) [reset = 0h]
16.5.7.538 QUEUE_125_D Register (offset = 27DCh) [reset = 0h]
16.5.7.539 QUEUE_126_A Register (offset = 27E0h) [reset = 0h]
16.5.7.540 QUEUE_126_B Register (offset = 27E4h) [reset = 0h]
16.5.7.541 QUEUE_126_C Register (offset = 27E8h) [reset = 0h]
16.5.7.542 QUEUE_126_D Register (offset = 27ECh) [reset = 0h]
16.5.7.543 QUEUE_127_A Register (offset = 27F0h) [reset = 0h]
16.5.7.544 QUEUE_127_B Register (offset = 27F4h) [reset = 0h]
16.5.7.545 QUEUE_127_C Register (offset = 27F8h) [reset = 0h]
16.5.7.546 QUEUE_127_D Register (offset = 27FCh) [reset = 0h]
16.5.7.547 QUEUE_128_A Register (offset = 2800h) [reset = 0h]
16.5.7.548 QUEUE_128_B Register (offset = 2804h) [reset = 0h]
16.5.7.549 QUEUE_128_C Register (offset = 2808h) [reset = 0h]
16.5.7.550 QUEUE_128_D Register (offset = 280Ch) [reset = 0h]
16.5.7.551 QUEUE_129_A Register (offset = 2810h) [reset = 0h]
16.5.7.552 QUEUE_129_B Register (offset = 2814h) [reset = 0h]
16.5.7.553 QUEUE_129_C Register (offset = 2818h) [reset = 0h]
16.5.7.554 QUEUE_129_D Register (offset = 281Ch) [reset = 0h]
16.5.7.555 QUEUE_130_A Register (offset = 2820h) [reset = 0h]
16.5.7.556 QUEUE_130_B Register (offset = 2824h) [reset = 0h]
16.5.7.557 QUEUE_130_C Register (offset = 2828h) [reset = 0h]
16.5.7.558 QUEUE_130_D Register (offset = 282Ch) [reset = 0h]
16.5.7.559 QUEUE_131_A Register (offset = 2830h) [reset = 0h]
16.5.7.560 QUEUE_131_B Register (offset = 2834h) [reset = 0h]
16.5.7.561 QUEUE_131_C Register (offset = 2838h) [reset = 0h]
16.5.7.562 QUEUE_131_D Register (offset = 283Ch) [reset = 0h]
16.5.7.563 QUEUE_132_A Register (offset = 2840h) [reset = 0h]
16.5.7.564 QUEUE_132_B Register (offset = 2844h) [reset = 0h]
16.5.7.565 QUEUE_132_C Register (offset = 2848h) [reset = 0h]
16.5.7.566 QUEUE_132_D Register (offset = 284Ch) [reset = 0h]
16.5.7.567 QUEUE_133_A Register (offset = 2850h) [reset = 0h]
16.5.7.568 QUEUE_133_B Register (offset = 2854h) [reset = 0h]
16.5.7.569 QUEUE_133_C Register (offset = 2858h) [reset = 0h]
16.5.7.570 QUEUE_133_D Register (offset = 285Ch) [reset = 0h]
16.5.7.571 QUEUE_134_A Register (offset = 2860h) [reset = 0h]
16.5.7.572 QUEUE_134_B Register (offset = 2864h) [reset = 0h]
16.5.7.573 QUEUE_134_C Register (offset = 2868h) [reset = 0h]
16.5.7.574 QUEUE_134_D Register (offset = 286Ch) [reset = 0h]
16.5.7.575 QUEUE_135_A Register (offset = 2870h) [reset = 0h]
16.5.7.576 QUEUE_135_B Register (offset = 2874h) [reset = 0h]
16.5.7.577 QUEUE_135_C Register (offset = 2878h) [reset = 0h]
16.5.7.578 QUEUE_135_D Register (offset = 287Ch) [reset = 0h]
16.5.7.579 QUEUE_136_A Register (offset = 2880h) [reset = 0h]
16.5.7.580 QUEUE_136_B Register (offset = 2884h) [reset = 0h]
16.5.7.581 QUEUE_136_C Register (offset = 2888h) [reset = 0h]
16.5.7.582 QUEUE_136_D Register (offset = 288Ch) [reset = 0h]
16.5.7.583 QUEUE_137_A Register (offset = 2890h) [reset = 0h]
16.5.7.584 QUEUE_137_B Register (offset = 2894h) [reset = 0h]
16.5.7.585 QUEUE_137_C Register (offset = 2898h) [reset = 0h]
16.5.7.586 QUEUE_137_D Register (offset = 289Ch) [reset = 0h]
16.5.7.587 QUEUE_138_A Register (offset = 28A0h) [reset = 0h]
16.5.7.588 QUEUE_138_B Register (offset = 28A4h) [reset = 0h]
16.5.7.589 QUEUE_138_C Register (offset = 28A8h) [reset = 0h]
16.5.7.590 QUEUE_138_D Register (offset = 28ACh) [reset = 0h]
16.5.7.591 QUEUE_139_A Register (offset = 28B0h) [reset = 0h]
16.5.7.592 QUEUE_139_B Register (offset = 28B4h) [reset = 0h]
16.5.7.593 QUEUE_139_C Register (offset = 28B8h) [reset = 0h]
16.5.7.594 QUEUE_139_D Register (offset = 28BCh) [reset = 0h]
16.5.7.595 QUEUE_140_A Register (offset = 28C0h) [reset = 0h]
16.5.7.596 QUEUE_140_B Register (offset = 28C4h) [reset = 0h]
16.5.7.597 QUEUE_140_C Register (offset = 28C8h) [reset = 0h]
16.5.7.598 QUEUE_140_D Register (offset = 28CCh) [reset = 0h]
16.5.7.599 QUEUE_141_A Register (offset = 28D0h) [reset = 0h]
16.5.7.600 QUEUE_141_B Register (offset = 28D4h) [reset = 0h]
16.5.7.601 QUEUE_141_C Register (offset = 28D8h) [reset = 0h]
16.5.7.602 QUEUE_141_D Register (offset = 28DCh) [reset = 0h]
16.5.7.603 QUEUE_142_A Register (offset = 28E0h) [reset = 0h]
16.5.7.604 QUEUE_142_B Register (offset = 28E4h) [reset = 0h]
16.5.7.605 QUEUE_142_C Register (offset = 28E8h) [reset = 0h]
16.5.7.606 QUEUE_142_D Register (offset = 28ECh) [reset = 0h]
16.5.7.607 QUEUE_143_A Register (offset = 28F0h) [reset = 0h]
16.5.7.608 QUEUE_143_B Register (offset = 28F4h) [reset = 0h]
16.5.7.609 QUEUE_143_C Register (offset = 28F8h) [reset = 0h]
16.5.7.610 QUEUE_143_D Register (offset = 28FCh) [reset = 0h]
16.5.7.611 QUEUE_144_A Register (offset = 2900h) [reset = 0h]
16.5.7.612 QUEUE_144_B Register (offset = 2904h) [reset = 0h]
16.5.7.613 QUEUE_144_C Register (offset = 2908h) [reset = 0h]
16.5.7.614 QUEUE_144_D Register (offset = 290Ch) [reset = 0h]
16.5.7.615 QUEUE_145_A Register (offset = 2910h) [reset = 0h]
16.5.7.616 QUEUE_145_B Register (offset = 2914h) [reset = 0h]
16.5.7.617 QUEUE_145_C Register (offset = 2918h) [reset = 0h]
16.5.7.618 QUEUE_145_D Register (offset = 291Ch) [reset = 0h]
16.5.7.619 QUEUE_146_A Register (offset = 2920h) [reset = 0h]
16.5.7.620 QUEUE_146_B Register (offset = 2924h) [reset = 0h]
16.5.7.621 QUEUE_146_C Register (offset = 2928h) [reset = 0h]
16.5.7.622 QUEUE_146_D Register (offset = 292Ch) [reset = 0h]
16.5.7.623 QUEUE_147_A Register (offset = 2930h) [reset = 0h]
16.5.7.624 QUEUE_147_B Register (offset = 2934h) [reset = 0h]
16.5.7.625 QUEUE_147_C Register (offset = 2938h) [reset = 0h]
16.5.7.626 QUEUE_147_D Register (offset = 293Ch) [reset = 0h]
16.5.7.627 QUEUE_148_A Register (offset = 2940h) [reset = 0h]
16.5.7.628 QUEUE_148_B Register (offset = 2944h) [reset = 0h]
16.5.7.629 QUEUE_148_C Register (offset = 2948h) [reset = 0h]
16.5.7.630 QUEUE_148_D Register (offset = 294Ch) [reset = 0h]
16.5.7.631 QUEUE_149_A Register (offset = 2950h) [reset = 0h]
16.5.7.632 QUEUE_149_B Register (offset = 2954h) [reset = 0h]
16.5.7.633 QUEUE_149_C Register (offset = 2958h) [reset = 0h]
16.5.7.634 QUEUE_149_D Register (offset = 295Ch) [reset = 0h]
16.5.7.635 QUEUE_150_A Register (offset = 2960h) [reset = 0h]
16.5.7.636 QUEUE_150_B Register (offset = 2964h) [reset = 0h]
16.5.7.637 QUEUE_150_C Register (offset = 2968h) [reset = 0h]
16.5.7.638 QUEUE_150_D Register (offset = 296Ch) [reset = 0h]
16.5.7.639 QUEUE_151_A Register (offset = 2970h) [reset = 0h]
16.5.7.640 QUEUE_151_B Register (offset = 2974h) [reset = 0h]
16.5.7.641 QUEUE_151_C Register (offset = 2978h) [reset = 0h]
16.5.7.642 QUEUE_151_D Register (offset = 297Ch) [reset = 0h]
16.5.7.643 QUEUE_152_A Register (offset = 2980h) [reset = 0h]
16.5.7.644 QUEUE_152_B Register (offset = 2984h) [reset = 0h]
16.5.7.645 QUEUE_152_C Register (offset = 2988h) [reset = 0h]
16.5.7.646 QUEUE_152_D Register (offset = 298Ch) [reset = 0h]
16.5.7.647 QUEUE_153_A Register (offset = 2990h) [reset = 0h]
16.5.7.648 QUEUE_153_B Register (offset = 2994h) [reset = 0h]
16.5.7.649 QUEUE_153_C Register (offset = 2998h) [reset = 0h]
16.5.7.650 QUEUE_153_D Register (offset = 299Ch) [reset = 0h]
16.5.7.651 QUEUE_154_A Register (offset = 29A0h) [reset = 0h]
16.5.7.652 QUEUE_154_B Register (offset = 29A4h) [reset = 0h]
16.5.7.653 QUEUE_154_C Register (offset = 29A8h) [reset = 0h]
16.5.7.654 QUEUE_154_D Register (offset = 29ACh) [reset = 0h]
16.5.7.655 QUEUE_155_A Register (offset = 29B0h) [reset = 0h]
16.5.7.656 QUEUE_155_B Register (offset = 29B4h) [reset = 0h]
16.5.7.657 QUEUE_155_C Register (offset = 29B8h) [reset = 0h]
16.5.7.658 QUEUE_155_D Register (offset = 29BCh) [reset = 0h]
16.5.7.659 QUEUE_0_STATUS_A Register (offset = 3000h) [reset = 0h]
16.5.7.660 QUEUE_0_STATUS_B Register (offset = 3004h) [reset = 0h]
16.5.7.661 QUEUE_0_STATUS_C Register (offset = 3008h) [reset = 0h]
16.5.7.662 QUEUE_1_STATUS_A Register (offset = 3010h) [reset = 0h]
16.5.7.663 QUEUE_1_STATUS_B Register (offset = 3014h) [reset = 0h]
16.5.7.664 QUEUE_1_STATUS_C Register (offset = 3018h) [reset = 0h]
16.5.7.665 QUEUE_2_STATUS_A Register (offset = 3020h) [reset = 0h]
16.5.7.666 QUEUE_2_STATUS_B Register (offset = 3024h) [reset = 0h]
16.5.7.667 QUEUE_2_STATUS_C Register (offset = 3028h) [reset = 0h]
16.5.7.668 QUEUE_3_STATUS_A Register (offset = 3030h) [reset = 0h]
16.5.7.669 QUEUE_3_STATUS_B Register (offset = 3034h) [reset = 0h]
16.5.7.670 QUEUE_3_STATUS_C Register (offset = 3038h) [reset = 0h]
16.5.7.671 QUEUE_4_STATUS_A Register (offset = 3040h) [reset = 0h]
16.5.7.672 QUEUE_4_STATUS_B Register (offset = 3044h) [reset = 0h]
16.5.7.673 QUEUE_4_STATUS_C Register (offset = 3048h) [reset = 0h]
16.5.7.674 QUEUE_5_STATUS_A Register (offset = 3050h) [reset = 0h]
16.5.7.675 QUEUE_5_STATUS_B Register (offset = 3054h) [reset = 0h]
16.5.7.676 QUEUE_5_STATUS_C Register (offset = 3058h) [reset = 0h]
16.5.7.677 QUEUE_6_STATUS_A Register (offset = 3060h) [reset = 0h]
16.5.7.678 QUEUE_6_STATUS_B Register (offset = 3064h) [reset = 0h]
16.5.7.679 QUEUE_6_STATUS_C Register (offset = 3068h) [reset = 0h]
16.5.7.680 QUEUE_7_STATUS_A Register (offset = 3070h) [reset = 0h]
16.5.7.681 QUEUE_7_STATUS_B Register (offset = 3074h) [reset = 0h]
16.5.7.682 QUEUE_7_STATUS_C Register (offset = 3078h) [reset = 0h]
16.5.7.683 QUEUE_8_STATUS_A Register (offset = 3080h) [reset = 0h]
16.5.7.684 QUEUE_8_STATUS_B Register (offset = 3084h) [reset = 0h]
16.5.7.685 QUEUE_8_STATUS_C Register (offset = 3088h) [reset = 0h]
16.5.7.686 QUEUE_9_STATUS_A Register (offset = 3090h) [reset = 0h]
16.5.7.687 QUEUE_9_STATUS_B Register (offset = 3094h) [reset = 0h]
16.5.7.688 QUEUE_9_STATUS_C Register (offset = 3098h) [reset = 0h]
16.5.7.689 QUEUE_10_STATUS_A Register (offset = 30A0h) [reset = 0h]
16.5.7.690 QUEUE_10_STATUS_B Register (offset = 30A4h) [reset = 0h]
16.5.7.691 QUEUE_10_STATUS_C Register (offset = 30A8h) [reset = 0h]
16.5.7.692 QUEUE_11_STATUS_A Register (offset = 30B0h) [reset = 0h]
16.5.7.693 QUEUE_11_STATUS_B Register (offset = 30B4h) [reset = 0h]
16.5.7.694 QUEUE_11_STATUS_C Register (offset = 30B8h) [reset = 0h]
16.5.7.695 QUEUE_12_STATUS_A Register (offset = 30C0h) [reset = 0h]
16.5.7.696 QUEUE_12_STATUS_B Register (offset = 30C4h) [reset = 0h]
16.5.7.697 QUEUE_12_STATUS_C Register (offset = 30C8h) [reset = 0h]
16.5.7.698 QUEUE_13_STATUS_A Register (offset = 30D0h) [reset = 0h]
16.5.7.699 QUEUE_13_STATUS_B Register (offset = 30D4h) [reset = 0h]
16.5.7.700 QUEUE_13_STATUS_C Register (offset = 30D8h) [reset = 0h]
16.5.7.701 QUEUE_14_STATUS_A Register (offset = 30E0h) [reset = 0h]
16.5.7.702 QUEUE_14_STATUS_B Register (offset = 30E4h) [reset = 0h]
16.5.7.703 QUEUE_14_STATUS_C Register (offset = 30E8h) [reset = 0h]
16.5.7.704 QUEUE_15_STATUS_A Register (offset = 30F0h) [reset = 0h]
16.5.7.705 QUEUE_15_STATUS_B Register (offset = 30F4h) [reset = 0h]
16.5.7.706 QUEUE_15_STATUS_C Register (offset = 30F8h) [reset = 0h]
16.5.7.707 QUEUE_16_STATUS_A Register (offset = 3100h) [reset = 0h]
16.5.7.708 QUEUE_16_STATUS_B Register (offset = 3104h) [reset = 0h]
16.5.7.709 QUEUE_16_STATUS_C Register (offset = 3108h) [reset = 0h]
16.5.7.710 QUEUE_17_STATUS_A Register (offset = 3110h) [reset = 0h]
16.5.7.711 QUEUE_17_STATUS_B Register (offset = 3114h) [reset = 0h]
16.5.7.712 QUEUE_17_STATUS_C Register (offset = 3118h) [reset = 0h]
16.5.7.713 QUEUE_18_STATUS_A Register (offset = 3120h) [reset = 0h]
16.5.7.714 QUEUE_18_STATUS_B Register (offset = 3124h) [reset = 0h]
16.5.7.715 QUEUE_18_STATUS_C Register (offset = 3128h) [reset = 0h]
16.5.7.716 QUEUE_19_STATUS_A Register (offset = 3130h) [reset = 0h]
16.5.7.717 QUEUE_19_STATUS_B Register (offset = 3134h) [reset = 0h]
16.5.7.718 QUEUE_19_STATUS_C Register (offset = 3138h) [reset = 0h]
16.5.7.719 QUEUE_20_STATUS_A Register (offset = 3140h) [reset = 0h]
16.5.7.720 QUEUE_20_STATUS_B Register (offset = 3144h) [reset = 0h]
16.5.7.721 QUEUE_20_STATUS_C Register (offset = 3148h) [reset = 0h]
16.5.7.722 QUEUE_21_STATUS_A Register (offset = 3150h) [reset = 0h]
16.5.7.723 QUEUE_21_STATUS_B Register (offset = 3154h) [reset = 0h]
16.5.7.724 QUEUE_21_STATUS_C Register (offset = 3158h) [reset = 0h]
16.5.7.725 QUEUE_22_STATUS_A Register (offset = 3160h) [reset = 0h]
16.5.7.726 QUEUE_22_STATUS_B Register (offset = 3164h) [reset = 0h]
16.5.7.727 QUEUE_22_STATUS_C Register (offset = 3168h) [reset = 0h]
16.5.7.728 QUEUE_23_STATUS_A Register (offset = 3170h) [reset = 0h]
16.5.7.729 QUEUE_23_STATUS_B Register (offset = 3174h) [reset = 0h]
16.5.7.730 QUEUE_23_STATUS_C Register (offset = 3178h) [reset = 0h]
16.5.7.731 QUEUE_24_STATUS_A Register (offset = 3180h) [reset = 0h]
16.5.7.732 QUEUE_24_STATUS_B Register (offset = 3184h) [reset = 0h]
16.5.7.733 QUEUE_24_STATUS_C Register (offset = 3188h) [reset = 0h]
16.5.7.734 QUEUE_25_STATUS_A Register (offset = 3190h) [reset = 0h]
16.5.7.735 QUEUE_25_STATUS_B Register (offset = 3194h) [reset = 0h]
16.5.7.736 QUEUE_25_STATUS_C Register (offset = 3198h) [reset = 0h]
16.5.7.737 QUEUE_26_STATUS_A Register (offset = 31A0h) [reset = 0h]
16.5.7.738 QUEUE_26_STATUS_B Register (offset = 31A4h) [reset = 0h]
16.5.7.739 QUEUE_26_STATUS_C Register (offset = 31A8h) [reset = 0h]
16.5.7.740 QUEUE_27_STATUS_A Register (offset = 31B0h) [reset = 0h]
16.5.7.741 QUEUE_27_STATUS_B Register (offset = 31B4h) [reset = 0h]
16.5.7.742 QUEUE_27_STATUS_C Register (offset = 31B8h) [reset = 0h]
16.5.7.743 QUEUE_28_STATUS_A Register (offset = 31C0h) [reset = 0h]
16.5.7.744 QUEUE_28_STATUS_B Register (offset = 31C4h) [reset = 0h]
16.5.7.745 QUEUE_28_STATUS_C Register (offset = 31C8h) [reset = 0h]
16.5.7.746 QUEUE_29_STATUS_A Register (offset = 31D0h) [reset = 0h]
16.5.7.747 QUEUE_29_STATUS_B Register (offset = 31D4h) [reset = 0h]
16.5.7.748 QUEUE_29_STATUS_C Register (offset = 31D8h) [reset = 0h]
16.5.7.749 QUEUE_30_STATUS_A Register (offset = 31E0h) [reset = 0h]
16.5.7.750 QUEUE_30_STATUS_B Register (offset = 31E4h) [reset = 0h]
16.5.7.751 QUEUE_30_STATUS_C Register (offset = 31E8h) [reset = 0h]
16.5.7.752 QUEUE_31_STATUS_A Register (offset = 31F0h) [reset = 0h]
16.5.7.753 QUEUE_31_STATUS_B Register (offset = 31F4h) [reset = 0h]
16.5.7.754 QUEUE_31_STATUS_C Register (offset = 31F8h) [reset = 0h]
16.5.7.755 QUEUE_32_STATUS_A Register (offset = 3200h) [reset = 0h]
16.5.7.756 QUEUE_32_STATUS_B Register (offset = 3204h) [reset = 0h]
16.5.7.757 QUEUE_32_STATUS_C Register (offset = 3208h) [reset = 0h]
16.5.7.758 QUEUE_33_STATUS_A Register (offset = 3210h) [reset = 0h]
16.5.7.759 QUEUE_33_STATUS_B Register (offset = 3214h) [reset = 0h]
16.5.7.760 QUEUE_33_STATUS_C Register (offset = 3218h) [reset = 0h]
16.5.7.761 QUEUE_34_STATUS_A Register (offset = 3220h) [reset = 0h]
16.5.7.762 QUEUE_34_STATUS_B Register (offset = 3224h) [reset = 0h]
16.5.7.763 QUEUE_34_STATUS_C Register (offset = 3228h) [reset = 0h]
16.5.7.764 QUEUE_35_STATUS_A Register (offset = 3230h) [reset = 0h]
16.5.7.765 QUEUE_35_STATUS_B Register (offset = 3234h) [reset = 0h]
16.5.7.766 QUEUE_35_STATUS_C Register (offset = 3238h) [reset = 0h]
16.5.7.767 QUEUE_36_STATUS_A Register (offset = 3240h) [reset = 0h]
16.5.7.768 QUEUE_36_STATUS_B Register (offset = 3244h) [reset = 0h]
16.5.7.769 QUEUE_36_STATUS_C Register (offset = 3248h) [reset = 0h]
16.5.7.770 QUEUE_37_STATUS_A Register (offset = 3250h) [reset = 0h]
16.5.7.771 QUEUE_37_STATUS_B Register (offset = 3254h) [reset = 0h]
16.5.7.772 QUEUE_37_STATUS_C Register (offset = 3258h) [reset = 0h]
16.5.7.773 QUEUE_38_STATUS_A Register (offset = 3260h) [reset = 0h]
16.5.7.774 QUEUE_38_STATUS_B Register (offset = 3264h) [reset = 0h]
16.5.7.775 QUEUE_38_STATUS_C Register (offset = 3268h) [reset = 0h]
16.5.7.776 QUEUE_39_STATUS_A Register (offset = 3270h) [reset = 0h]
16.5.7.777 QUEUE_39_STATUS_B Register (offset = 3274h) [reset = 0h]
16.5.7.778 QUEUE_39_STATUS_C Register (offset = 3278h) [reset = 0h]
16.5.7.779 QUEUE_40_STATUS_A Register (offset = 3280h) [reset = 0h]
16.5.7.780 QUEUE_40_STATUS_B Register (offset = 3284h) [reset = 0h]
16.5.7.781 QUEUE_40_STATUS_C Register (offset = 3288h) [reset = 0h]
16.5.7.782 QUEUE_41_STATUS_A Register (offset = 3290h) [reset = 0h]
16.5.7.783 QUEUE_41_STATUS_B Register (offset = 3294h) [reset = 0h]
16.5.7.784 QUEUE_41_STATUS_C Register (offset = 3298h) [reset = 0h]
16.5.7.785 QUEUE_42_STATUS_A Register (offset = 32A0h) [reset = 0h]
16.5.7.786 QUEUE_42_STATUS_B Register (offset = 32A4h) [reset = 0h]
16.5.7.787 QUEUE_42_STATUS_C Register (offset = 32A8h) [reset = 0h]
16.5.7.788 QUEUE_43_STATUS_A Register (offset = 32B0h) [reset = 0h]
16.5.7.789 QUEUE_43_STATUS_B Register (offset = 32B4h) [reset = 0h]
16.5.7.790 QUEUE_43_STATUS_C Register (offset = 32B8h) [reset = 0h]
16.5.7.791 QUEUE_44_STATUS_A Register (offset = 32C0h) [reset = 0h]
16.5.7.792 QUEUE_44_STATUS_B Register (offset = 32C4h) [reset = 0h]
16.5.7.793 QUEUE_44_STATUS_C Register (offset = 32C8h) [reset = 0h]
16.5.7.794 QUEUE_45_STATUS_A Register (offset = 32D0h) [reset = 0h]
16.5.7.795 QUEUE_45_STATUS_B Register (offset = 32D4h) [reset = 0h]
16.5.7.796 QUEUE_45_STATUS_C Register (offset = 32D8h) [reset = 0h]
16.5.7.797 QUEUE_46_STATUS_A Register (offset = 32E0h) [reset = 0h]
16.5.7.798 QUEUE_46_STATUS_B Register (offset = 32E4h) [reset = 0h]
16.5.7.799 QUEUE_46_STATUS_C Register (offset = 32E8h) [reset = 0h]
16.5.7.800 QUEUE_47_STATUS_A Register (offset = 32F0h) [reset = 0h]
16.5.7.801 QUEUE_47_STATUS_B Register (offset = 32F4h) [reset = 0h]
16.5.7.802 QUEUE_47_STATUS_C Register (offset = 32F8h) [reset = 0h]
16.5.7.803 QUEUE_48_STATUS_A Register (offset = 3300h) [reset = 0h]
16.5.7.804 QUEUE_48_STATUS_B Register (offset = 3304h) [reset = 0h]
16.5.7.805 QUEUE_48_STATUS_C Register (offset = 3308h) [reset = 0h]
16.5.7.806 QUEUE_49_STATUS_A Register (offset = 3310h) [reset = 0h]
16.5.7.807 QUEUE_49_STATUS_B Register (offset = 3314h) [reset = 0h]
16.5.7.808 QUEUE_49_STATUS_C Register (offset = 3318h) [reset = 0h]
16.5.7.809 QUEUE_50_STATUS_A Register (offset = 3320h) [reset = 0h]
16.5.7.810 QUEUE_50_STATUS_B Register (offset = 3324h) [reset = 0h]
16.5.7.811 QUEUE_50_STATUS_C Register (offset = 3328h) [reset = 0h]
16.5.7.812 QUEUE_51_STATUS_A Register (offset = 3330h) [reset = 0h]
16.5.7.813 QUEUE_51_STATUS_B Register (offset = 3334h) [reset = 0h]
16.5.7.814 QUEUE_51_STATUS_C Register (offset = 3338h) [reset = 0h]
16.5.7.815 QUEUE_52_STATUS_A Register (offset = 3340h) [reset = 0h]
16.5.7.816 QUEUE_52_STATUS_B Register (offset = 3344h) [reset = 0h]
16.5.7.817 QUEUE_52_STATUS_C Register (offset = 3348h) [reset = 0h]
16.5.7.818 QUEUE_53_STATUS_A Register (offset = 3350h) [reset = 0h]
16.5.7.819 QUEUE_53_STATUS_B Register (offset = 3354h) [reset = 0h]
16.5.7.820 QUEUE_53_STATUS_C Register (offset = 3358h) [reset = 0h]
16.5.7.821 QUEUE_54_STATUS_A Register (offset = 3360h) [reset = 0h]
16.5.7.822 QUEUE_54_STATUS_B Register (offset = 3364h) [reset = 0h]
16.5.7.823 QUEUE_54_STATUS_C Register (offset = 3368h) [reset = 0h]
16.5.7.824 QUEUE_55_STATUS_A Register (offset = 3370h) [reset = 0h]
16.5.7.825 QUEUE_55_STATUS_B Register (offset = 3374h) [reset = 0h]
16.5.7.826 QUEUE_55_STATUS_C Register (offset = 3378h) [reset = 0h]
16.5.7.827 QUEUE_56_STATUS_A Register (offset = 3380h) [reset = 0h]
16.5.7.828 QUEUE_56_STATUS_B Register (offset = 3384h) [reset = 0h]
16.5.7.829 QUEUE_56_STATUS_C Register (offset = 3388h) [reset = 0h]
16.5.7.830 QUEUE_57_STATUS_A Register (offset = 3390h) [reset = 0h]
16.5.7.831 QUEUE_57_STATUS_B Register (offset = 3394h) [reset = 0h]
16.5.7.832 QUEUE_57_STATUS_C Register (offset = 3398h) [reset = 0h]
16.5.7.833 QUEUE_58_STATUS_A Register (offset = 33A0h) [reset = 0h]
16.5.7.834 QUEUE_58_STATUS_B Register (offset = 33A4h) [reset = 0h]
16.5.7.835 QUEUE_58_STATUS_C Register (offset = 33A8h) [reset = 0h]
16.5.7.836 QUEUE_59_STATUS_A Register (offset = 33B0h) [reset = 0h]
16.5.7.837 QUEUE_59_STATUS_B Register (offset = 33B4h) [reset = 0h]
16.5.7.838 QUEUE_59_STATUS_C Register (offset = 33B8h) [reset = 0h]
16.5.7.839 QUEUE_60_STATUS_A Register (offset = 33C0h) [reset = 0h]
16.5.7.840 QUEUE_60_STATUS_B Register (offset = 33C4h) [reset = 0h]
16.5.7.841 QUEUE_60_STATUS_C Register (offset = 33C8h) [reset = 0h]
16.5.7.842 QUEUE_61_STATUS_A Register (offset = 33D0h) [reset = 0h]
16.5.7.843 QUEUE_61_STATUS_B Register (offset = 33D4h) [reset = 0h]
16.5.7.844 QUEUE_61_STATUS_C Register (offset = 33D8h) [reset = 0h]
16.5.7.845 QUEUE_62_STATUS_A Register (offset = 33E0h) [reset = 0h]
16.5.7.846 QUEUE_62_STATUS_B Register (offset = 33E4h) [reset = 0h]
16.5.7.847 QUEUE_62_STATUS_C Register (offset = 33E8h) [reset = 0h]
16.5.7.848 QUEUE_63_STATUS_A Register (offset = 33F0h) [reset = 0h]
16.5.7.849 QUEUE_63_STATUS_B Register (offset = 33F4h) [reset = 0h]
16.5.7.850 QUEUE_63_STATUS_C Register (offset = 33F8h) [reset = 0h]
16.5.7.851 QUEUE_64_STATUS_A Register (offset = 3400h) [reset = 0h]
16.5.7.852 QUEUE_64_STATUS_B Register (offset = 3404h) [reset = 0h]
16.5.7.853 QUEUE_64_STATUS_C Register (offset = 3408h) [reset = 0h]
16.5.7.854 QUEUE_65_STATUS_A Register (offset = 3410h) [reset = 0h]
16.5.7.855 QUEUE_65_STATUS_B Register (offset = 3414h) [reset = 0h]
16.5.7.856 QUEUE_65_STATUS_C Register (offset = 3418h) [reset = 0h]
16.5.7.857 QUEUE_66_STATUS_A Register (offset = 3420h) [reset = 0h]
16.5.7.858 QUEUE_66_STATUS_B Register (offset = 3424h) [reset = 0h]
16.5.7.859 QUEUE_66_STATUS_C Register (offset = 3428h) [reset = 0h]
16.5.7.860 QUEUE_67_STATUS_A Register (offset = 3430h) [reset = 0h]
16.5.7.861 QUEUE_67_STATUS_B Register (offset = 3434h) [reset = 0h]
16.5.7.862 QUEUE_67_STATUS_C Register (offset = 3438h) [reset = 0h]
16.5.7.863 QUEUE_68_STATUS_A Register (offset = 3440h) [reset = 0h]
16.5.7.864 QUEUE_68_STATUS_B Register (offset = 3444h) [reset = 0h]
16.5.7.865 QUEUE_68_STATUS_C Register (offset = 3448h) [reset = 0h]
16.5.7.866 QUEUE_69_STATUS_A Register (offset = 3450h) [reset = 0h]
16.5.7.867 QUEUE_69_STATUS_B Register (offset = 3454h) [reset = 0h]
16.5.7.868 QUEUE_69_STATUS_C Register (offset = 3458h) [reset = 0h]
16.5.7.869 QUEUE_70_STATUS_A Register (offset = 3460h) [reset = 0h]
16.5.7.870 QUEUE_70_STATUS_B Register (offset = 3464h) [reset = 0h]
16.5.7.871 QUEUE_70_STATUS_C Register (offset = 3468h) [reset = 0h]
16.5.7.872 QUEUE_71_STATUS_A Register (offset = 3470h) [reset = 0h]
16.5.7.873 QUEUE_71_STATUS_B Register (offset = 3474h) [reset = 0h]
16.5.7.874 QUEUE_71_STATUS_C Register (offset = 3478h) [reset = 0h]
16.5.7.875 QUEUE_72_STATUS_A Register (offset = 3480h) [reset = 0h]
16.5.7.876 QUEUE_72_STATUS_B Register (offset = 3484h) [reset = 0h]
16.5.7.877 QUEUE_72_STATUS_C Register (offset = 3488h) [reset = 0h]
16.5.7.878 QUEUE_73_STATUS_A Register (offset = 3490h) [reset = 0h]
16.5.7.879 QUEUE_73_STATUS_B Register (offset = 3494h) [reset = 0h]
16.5.7.880 QUEUE_73_STATUS_C Register (offset = 3498h) [reset = 0h]
16.5.7.881 QUEUE_74_STATUS_A Register (offset = 34A0h) [reset = 0h]
16.5.7.882 QUEUE_74_STATUS_B Register (offset = 34A4h) [reset = 0h]
16.5.7.883 QUEUE_74_STATUS_C Register (offset = 34A8h) [reset = 0h]
16.5.7.884 QUEUE_75_STATUS_A Register (offset = 34B0h) [reset = 0h]
16.5.7.885 QUEUE_75_STATUS_B Register (offset = 34B4h) [reset = 0h]
16.5.7.886 QUEUE_75_STATUS_C Register (offset = 34B8h) [reset = 0h]
16.5.7.887 QUEUE_76_STATUS_A Register (offset = 34C0h) [reset = 0h]
16.5.7.888 QUEUE_76_STATUS_B Register (offset = 34C4h) [reset = 0h]
16.5.7.889 QUEUE_76_STATUS_C Register (offset = 34C8h) [reset = 0h]
16.5.7.890 QUEUE_77_STATUS_A Register (offset = 34D0h) [reset = 0h]
16.5.7.891 QUEUE_77_STATUS_B Register (offset = 34D4h) [reset = 0h]
16.5.7.892 QUEUE_77_STATUS_C Register (offset = 34D8h) [reset = 0h]
16.5.7.893 QUEUE_78_STATUS_A Register (offset = 34E0h) [reset = 0h]
16.5.7.894 QUEUE_78_STATUS_B Register (offset = 34E4h) [reset = 0h]
16.5.7.895 QUEUE_78_STATUS_C Register (offset = 34E8h) [reset = 0h]
16.5.7.896 QUEUE_79_STATUS_A Register (offset = 34F0h) [reset = 0h]
16.5.7.897 QUEUE_79_STATUS_B Register (offset = 34F4h) [reset = 0h]
16.5.7.898 QUEUE_79_STATUS_C Register (offset = 34F8h) [reset = 0h]
16.5.7.899 QUEUE_80_STATUS_A Register (offset = 3500h) [reset = 0h]
16.5.7.900 QUEUE_80_STATUS_B Register (offset = 3504h) [reset = 0h]
16.5.7.901 QUEUE_80_STATUS_C Register (offset = 3508h) [reset = 0h]
16.5.7.902 QUEUE_81_STATUS_A Register (offset = 3510h) [reset = 0h]
16.5.7.903 QUEUE_81_STATUS_B Register (offset = 3514h) [reset = 0h]
16.5.7.904 QUEUE_81_STATUS_C Register (offset = 3518h) [reset = 0h]
16.5.7.905 QUEUE_82_STATUS_A Register (offset = 3520h) [reset = 0h]
16.5.7.906 QUEUE_82_STATUS_B Register (offset = 3524h) [reset = 0h]
16.5.7.907 QUEUE_82_STATUS_C Register (offset = 3528h) [reset = 0h]
16.5.7.908 QUEUE_83_STATUS_A Register (offset = 3530h) [reset = 0h]
16.5.7.909 QUEUE_83_STATUS_B Register (offset = 3534h) [reset = 0h]
16.5.7.910 QUEUE_83_STATUS_C Register (offset = 3538h) [reset = 0h]
16.5.7.911 QUEUE_84_STATUS_A Register (offset = 3540h) [reset = 0h]
16.5.7.912 QUEUE_84_STATUS_B Register (offset = 3544h) [reset = 0h]
16.5.7.913 QUEUE_84_STATUS_C Register (offset = 3548h) [reset = 0h]
16.5.7.914 QUEUE_85_STATUS_A Register (offset = 3550h) [reset = 0h]
16.5.7.915 QUEUE_85_STATUS_B Register (offset = 3554h) [reset = 0h]
16.5.7.916 QUEUE_85_STATUS_C Register (offset = 3558h) [reset = 0h]
16.5.7.917 QUEUE_86_STATUS_A Register (offset = 3560h) [reset = 0h]
16.5.7.918 QUEUE_86_STATUS_B Register (offset = 3564h) [reset = 0h]
16.5.7.919 QUEUE_86_STATUS_C Register (offset = 3568h) [reset = 0h]
16.5.7.920 QUEUE_87_STATUS_A Register (offset = 3570h) [reset = 0h]
16.5.7.921 QUEUE_87_STATUS_B Register (offset = 3574h) [reset = 0h]
16.5.7.922 QUEUE_87_STATUS_C Register (offset = 3578h) [reset = 0h]
16.5.7.923 QUEUE_88_STATUS_A Register (offset = 3580h) [reset = 0h]
16.5.7.924 QUEUE_88_STATUS_B Register (offset = 3584h) [reset = 0h]
16.5.7.925 QUEUE_88_STATUS_C Register (offset = 3588h) [reset = 0h]
16.5.7.926 QUEUE_89_STATUS_A Register (offset = 3590h) [reset = 0h]
16.5.7.927 QUEUE_89_STATUS_B Register (offset = 3594h) [reset = 0h]
16.5.7.928 QUEUE_89_STATUS_C Register (offset = 3598h) [reset = 0h]
16.5.7.929 QUEUE_90_STATUS_A Register (offset = 35A0h) [reset = 0h]
16.5.7.930 QUEUE_90_STATUS_B Register (offset = 35A4h) [reset = 0h]
16.5.7.931 QUEUE_90_STATUS_C Register (offset = 35A8h) [reset = 0h]
16.5.7.932 QUEUE_91_STATUS_A Register (offset = 35B0h) [reset = 0h]
16.5.7.933 QUEUE_91_STATUS_B Register (offset = 35B4h) [reset = 0h]
16.5.7.934 QUEUE_91_STATUS_C Register (offset = 35B8h) [reset = 0h]
16.5.7.935 QUEUE_92_STATUS_A Register (offset = 35C0h) [reset = 0h]
16.5.7.936 QUEUE_92_STATUS_B Register (offset = 35C4h) [reset = 0h]
16.5.7.937 QUEUE_92_STATUS_C Register (offset = 35C8h) [reset = 0h]
16.5.7.938 QUEUE_93_STATUS_A Register (offset = 35D0h) [reset = 0h]
16.5.7.939 QUEUE_93_STATUS_B Register (offset = 35D4h) [reset = 0h]
16.5.7.940 QUEUE_93_STATUS_C Register (offset = 35D8h) [reset = 0h]
16.5.7.941 QUEUE_94_STATUS_A Register (offset = 35E0h) [reset = 0h]
16.5.7.942 QUEUE_94_STATUS_B Register (offset = 35E4h) [reset = 0h]
16.5.7.943 QUEUE_94_STATUS_C Register (offset = 35E8h) [reset = 0h]
16.5.7.944 QUEUE_95_STATUS_A Register (offset = 35F0h) [reset = 0h]
16.5.7.945 QUEUE_95_STATUS_B Register (offset = 35F4h) [reset = 0h]
16.5.7.946 QUEUE_95_STATUS_C Register (offset = 35F8h) [reset = 0h]
16.5.7.947 QUEUE_96_STATUS_A Register (offset = 3600h) [reset = 0h]
16.5.7.948 QUEUE_96_STATUS_B Register (offset = 3604h) [reset = 0h]
16.5.7.949 QUEUE_96_STATUS_C Register (offset = 3608h) [reset = 0h]
16.5.7.950 QUEUE_97_STATUS_A Register (offset = 3610h) [reset = 0h]
16.5.7.951 QUEUE_97_STATUS_B Register (offset = 3614h) [reset = 0h]
16.5.7.952 QUEUE_97_STATUS_C Register (offset = 3618h) [reset = 0h]
16.5.7.953 QUEUE_98_STATUS_A Register (offset = 3620h) [reset = 0h]
16.5.7.954 QUEUE_98_STATUS_B Register (offset = 3624h) [reset = 0h]
16.5.7.955 QUEUE_98_STATUS_C Register (offset = 3628h) [reset = 0h]
16.5.7.956 QUEUE_99_STATUS_A Register (offset = 3630h) [reset = 0h]
16.5.7.957 QUEUE_99_STATUS_B Register (offset = 3634h) [reset = 0h]
16.5.7.958 QUEUE_99_STATUS_C Register (offset = 3638h) [reset = 0h]
16.5.7.959 QUEUE_100_STATUS_A Register (offset = 3640h) [reset = 0h]
16.5.7.960 QUEUE_100_STATUS_B Register (offset = 3644h) [reset = 0h]
16.5.7.961 QUEUE_100_STATUS_C Register (offset = 3648h) [reset = 0h]
16.5.7.962 QUEUE_101_STATUS_A Register (offset = 3650h) [reset = 0h]
16.5.7.963 QUEUE_101_STATUS_B Register (offset = 3654h) [reset = 0h]
16.5.7.964 QUEUE_101_STATUS_C Register (offset = 3658h) [reset = 0h]
16.5.7.965 QUEUE_102_STATUS_A Register (offset = 3660h) [reset = 0h]
16.5.7.966 QUEUE_102_STATUS_B Register (offset = 3664h) [reset = 0h]
16.5.7.967 QUEUE_102_STATUS_C Register (offset = 3668h) [reset = 0h]
16.5.7.968 QUEUE_103_STATUS_A Register (offset = 3670h) [reset = 0h]
16.5.7.969 QUEUE_103_STATUS_B Register (offset = 3674h) [reset = 0h]
16.5.7.970 QUEUE_103_STATUS_C Register (offset = 3678h) [reset = 0h]
16.5.7.971 QUEUE_104_STATUS_A Register (offset = 3680h) [reset = 0h]
16.5.7.972 QUEUE_104_STATUS_B Register (offset = 3684h) [reset = 0h]
16.5.7.973 QUEUE_104_STATUS_C Register (offset = 3688h) [reset = 0h]
16.5.7.974 QUEUE_105_STATUS_A Register (offset = 3690h) [reset = 0h]
16.5.7.975 QUEUE_105_STATUS_B Register (offset = 3694h) [reset = 0h]
16.5.7.976 QUEUE_105_STATUS_C Register (offset = 3698h) [reset = 0h]
16.5.7.977 QUEUE_106_STATUS_A Register (offset = 36A0h) [reset = 0h]
16.5.7.978 QUEUE_106_STATUS_B Register (offset = 36A4h) [reset = 0h]
16.5.7.979 QUEUE_106_STATUS_C Register (offset = 36A8h) [reset = 0h]
16.5.7.980 QUEUE_107_STATUS_A Register (offset = 36B0h) [reset = 0h]
16.5.7.981 QUEUE_107_STATUS_B Register (offset = 36B4h) [reset = 0h]
16.5.7.982 QUEUE_107_STATUS_C Register (offset = 36B8h) [reset = 0h]
16.5.7.983 QUEUE_108_STATUS_A Register (offset = 36C0h) [reset = 0h]
16.5.7.984 QUEUE_108_STATUS_B Register (offset = 36C4h) [reset = 0h]
16.5.7.985 QUEUE_108_STATUS_C Register (offset = 36C8h) [reset = 0h]
16.5.7.986 QUEUE_109_STATUS_A Register (offset = 36D0h) [reset = 0h]
16.5.7.987 QUEUE_109_STATUS_B Register (offset = 36D4h) [reset = 0h]
16.5.7.988 QUEUE_109_STATUS_C Register (offset = 36D8h) [reset = 0h]
16.5.7.989 QUEUE_110_STATUS_A Register (offset = 36E0h) [reset = 0h]
16.5.7.990 QUEUE_110_STATUS_B Register (offset = 36E4h) [reset = 0h]
16.5.7.991 QUEUE_110_STATUS_C Register (offset = 36E8h) [reset = 0h]
16.5.7.992 QUEUE_111_STATUS_A Register (offset = 36F0h) [reset = 0h]
16.5.7.993 QUEUE_111_STATUS_B Register (offset = 36F4h) [reset = 0h]
16.5.7.994 QUEUE_111_STATUS_C Register (offset = 36F8h) [reset = 0h]
16.5.7.995 QUEUE_112_STATUS_A Register (offset = 3700h) [reset = 0h]
16.5.7.996 QUEUE_112_STATUS_B Register (offset = 3704h) [reset = 0h]
16.5.7.997 QUEUE_112_STATUS_C Register (offset = 3708h) [reset = 0h]
16.5.7.998 QUEUE_113_STATUS_A Register (offset = 3710h) [reset = 0h]
16.5.7.999 QUEUE_113_STATUS_B Register (offset = 3714h) [reset = 0h]
16.5.7.1000 QUEUE_113_STATUS_C Register (offset = 3718h) [reset = 0h]
16.5.7.1001 QUEUE_114_STATUS_A Register (offset = 3720h) [reset = 0h]
16.5.7.1002 QUEUE_114_STATUS_B Register (offset = 3724h) [reset = 0h]
16.5.7.1003 QUEUE_114_STATUS_C Register (offset = 3728h) [reset = 0h]
16.5.7.1004 QUEUE_115_STATUS_A Register (offset = 3730h) [reset = 0h]
16.5.7.1005 QUEUE_115_STATUS_B Register (offset = 3734h) [reset = 0h]
16.5.7.1006 QUEUE_115_STATUS_C Register (offset = 3738h) [reset = 0h]
16.5.7.1007 QUEUE_116_STATUS_A Register (offset = 3740h) [reset = 0h]
16.5.7.1008 QUEUE_116_STATUS_B Register (offset = 3744h) [reset = 0h]
16.5.7.1009 QUEUE_116_STATUS_C Register (offset = 3748h) [reset = 0h]
16.5.7.1010 QUEUE_117_STATUS_A Register (offset = 3750h) [reset = 0h]
16.5.7.1011 QUEUE_117_STATUS_B Register (offset = 3754h) [reset = 0h]
16.5.7.1012 QUEUE_117_STATUS_C Register (offset = 3758h) [reset = 0h]
16.5.7.1013 QUEUE_118_STATUS_A Register (offset = 3760h) [reset = 0h]
16.5.7.1014 QUEUE_118_STATUS_B Register (offset = 3764h) [reset = 0h]
16.5.7.1015 QUEUE_118_STATUS_C Register (offset = 3768h) [reset = 0h]
16.5.7.1016 QUEUE_119_STATUS_A Register (offset = 3770h) [reset = 0h]
16.5.7.1017 QUEUE_119_STATUS_B Register (offset = 3774h) [reset = 0h]
16.5.7.1018 QUEUE_119_STATUS_C Register (offset = 3778h) [reset = 0h]
16.5.7.1019 QUEUE_120_STATUS_A Register (offset = 3780h) [reset = 0h]
16.5.7.1020 QUEUE_120_STATUS_B Register (offset = 3784h) [reset = 0h]
16.5.7.1021 QUEUE_120_STATUS_C Register (offset = 3788h) [reset = 0h]
16.5.7.1022 QUEUE_121_STATUS_A Register (offset = 3790h) [reset = 0h]
16.5.7.1023 QUEUE_121_STATUS_B Register (offset = 3794h) [reset = 0h]
16.5.7.1024 QUEUE_121_STATUS_C Register (offset = 3798h) [reset = 0h]
16.5.7.1025 QUEUE_122_STATUS_A Register (offset = 37A0h) [reset = 0h]
16.5.7.1026 QUEUE_122_STATUS_B Register (offset = 37A4h) [reset = 0h]
16.5.7.1027 QUEUE_122_STATUS_C Register (offset = 37A8h) [reset = 0h]
16.5.7.1028 QUEUE_123_STATUS_A Register (offset = 37B0h) [reset = 0h]
16.5.7.1029 QUEUE_123_STATUS_B Register (offset = 37B4h) [reset = 0h]
16.5.7.1030 QUEUE_123_STATUS_C Register (offset = 37B8h) [reset = 0h]
16.5.7.1031 QUEUE_124_STATUS_A Register (offset = 37C0h) [reset = 0h]
16.5.7.1032 QUEUE_124_STATUS_B Register (offset = 37C4h) [reset = 0h]
16.5.7.1033 QUEUE_124_STATUS_C Register (offset = 37C8h) [reset = 0h]
16.5.7.1034 QUEUE_125_STATUS_A Register (offset = 37D0h) [reset = 0h]
16.5.7.1035 QUEUE_125_STATUS_B Register (offset = 37D4h) [reset = 0h]
16.5.7.1036 QUEUE_125_STATUS_C Register (offset = 37D8h) [reset = 0h]
16.5.7.1037 QUEUE_126_STATUS_A Register (offset = 37E0h) [reset = 0h]
16.5.7.1038 QUEUE_126_STATUS_B Register (offset = 37E4h) [reset = 0h]
16.5.7.1039 QUEUE_126_STATUS_C Register (offset = 37E8h) [reset = 0h]
16.5.7.1040 QUEUE_127_STATUS_A Register (offset = 37F0h) [reset = 0h]
16.5.7.1041 QUEUE_127_STATUS_B Register (offset = 37F4h) [reset = 0h]
16.5.7.1042 QUEUE_127_STATUS_C Register (offset = 37F8h) [reset = 0h]
16.5.7.1043 QUEUE_128_STATUS_A Register (offset = 3800h) [reset = 0h]
16.5.7.1044 QUEUE_128_STATUS_B Register (offset = 3804h) [reset = 0h]
16.5.7.1045 QUEUE_128_STATUS_C Register (offset = 3808h) [reset = 0h]
16.5.7.1046 QUEUE_129_STATUS_A Register (offset = 3810h) [reset = 0h]
16.5.7.1047 QUEUE_129_STATUS_B Register (offset = 3814h) [reset = 0h]
16.5.7.1048 QUEUE_129_STATUS_C Register (offset = 3818h) [reset = 0h]
16.5.7.1049 QUEUE_130_STATUS_A Register (offset = 3820h) [reset = 0h]
16.5.7.1050 QUEUE_130_STATUS_B Register (offset = 3824h) [reset = 0h]
16.5.7.1051 QUEUE_130_STATUS_C Register (offset = 3828h) [reset = 0h]
16.5.7.1052 QUEUE_131_STATUS_A Register (offset = 3830h) [reset = 0h]
16.5.7.1053 QUEUE_131_STATUS_B Register (offset = 3834h) [reset = 0h]
16.5.7.1054 QUEUE_131_STATUS_C Register (offset = 3838h) [reset = 0h]
16.5.7.1055 QUEUE_132_STATUS_A Register (offset = 3840h) [reset = 0h]
16.5.7.1056 QUEUE_132_STATUS_B Register (offset = 3844h) [reset = 0h]
16.5.7.1057 QUEUE_132_STATUS_C Register (offset = 3848h) [reset = 0h]
16.5.7.1058 QUEUE_133_STATUS_A Register (offset = 3850h) [reset = 0h]
16.5.7.1059 QUEUE_133_STATUS_B Register (offset = 3854h) [reset = 0h]
16.5.7.1060 QUEUE_133_STATUS_C Register (offset = 3858h) [reset = 0h]
16.5.7.1061 QUEUE_134_STATUS_A Register (offset = 3860h) [reset = 0h]
16.5.7.1062 QUEUE_134_STATUS_B Register (offset = 3864h) [reset = 0h]
16.5.7.1063 QUEUE_134_STATUS_C Register (offset = 3868h) [reset = 0h]
16.5.7.1064 QUEUE_135_STATUS_A Register (offset = 3870h) [reset = 0h]
16.5.7.1065 QUEUE_135_STATUS_B Register (offset = 3874h) [reset = 0h]
16.5.7.1066 QUEUE_135_STATUS_C Register (offset = 3878h) [reset = 0h]
16.5.7.1067 QUEUE_136_STATUS_A Register (offset = 3880h) [reset = 0h]
16.5.7.1068 QUEUE_136_STATUS_B Register (offset = 3884h) [reset = 0h]
16.5.7.1069 QUEUE_136_STATUS_C Register (offset = 3888h) [reset = 0h]
16.5.7.1070 QUEUE_137_STATUS_A Register (offset = 3890h) [reset = 0h]
16.5.7.1071 QUEUE_137_STATUS_B Register (offset = 3894h) [reset = 0h]
16.5.7.1072 QUEUE_137_STATUS_C Register (offset = 3898h) [reset = 0h]
16.5.7.1073 QUEUE_138_STATUS_A Register (offset = 38A0h) [reset = 0h]
16.5.7.1074 QUEUE_138_STATUS_B Register (offset = 38A4h) [reset = 0h]
16.5.7.1075 QUEUE_138_STATUS_C Register (offset = 38A8h) [reset = 0h]
16.5.7.1076 QUEUE_139_STATUS_A Register (offset = 38B0h) [reset = 0h]
16.5.7.1077 QUEUE_139_STATUS_B Register (offset = 38B4h) [reset = 0h]
16.5.7.1078 QUEUE_139_STATUS_C Register (offset = 38B8h) [reset = 0h]
16.5.7.1079 QUEUE_140_STATUS_A Register (offset = 38C0h) [reset = 0h]
16.5.7.1080 QUEUE_140_STATUS_B Register (offset = 38C4h) [reset = 0h]
16.5.7.1081 QUEUE_140_STATUS_C Register (offset = 38C8h) [reset = 0h]
16.5.7.1082 QUEUE_141_STATUS_A Register (offset = 38D0h) [reset = 0h]
16.5.7.1083 QUEUE_141_STATUS_B Register (offset = 38D4h) [reset = 0h]
16.5.7.1084 QUEUE_141_STATUS_C Register (offset = 38D8h) [reset = 0h]
16.5.7.1085 QUEUE_142_STATUS_A Register (offset = 38E0h) [reset = 0h]
16.5.7.1086 QUEUE_142_STATUS_B Register (offset = 38E4h) [reset = 0h]
16.5.7.1087 QUEUE_142_STATUS_C Register (offset = 38E8h) [reset = 0h]
16.5.7.1088 QUEUE_143_STATUS_A Register (offset = 38F0h) [reset = 0h]
16.5.7.1089 QUEUE_143_STATUS_B Register (offset = 38F4h) [reset = 0h]
16.5.7.1090 QUEUE_143_STATUS_C Register (offset = 38F8h) [reset = 0h]
16.5.7.1091 QUEUE_144_STATUS_A Register (offset = 3900h) [reset = 0h]
16.5.7.1092 QUEUE_144_STATUS_B Register (offset = 3904h) [reset = 0h]
16.5.7.1093 QUEUE_144_STATUS_C Register (offset = 3908h) [reset = 0h]
16.5.7.1094 QUEUE_145_STATUS_A Register (offset = 3910h) [reset = 0h]
16.5.7.1095 QUEUE_145_STATUS_B Register (offset = 3914h) [reset = 0h]
16.5.7.1096 QUEUE_145_STATUS_C Register (offset = 3918h) [reset = 0h]
16.5.7.1097 QUEUE_146_STATUS_A Register (offset = 3920h) [reset = 0h]
16.5.7.1098 QUEUE_146_STATUS_B Register (offset = 3924h) [reset = 0h]
16.5.7.1099 QUEUE_146_STATUS_C Register (offset = 3928h) [reset = 0h]
16.5.7.1100 QUEUE_147_STATUS_A Register (offset = 3930h) [reset = 0h]
16.5.7.1101 QUEUE_147_STATUS_B Register (offset = 3934h) [reset = 0h]
16.5.7.1102 QUEUE_147_STATUS_C Register (offset = 3938h) [reset = 0h]
16.5.7.1103 QUEUE_148_STATUS_A Register (offset = 3940h) [reset = 0h]
16.5.7.1104 QUEUE_148_STATUS_B Register (offset = 3944h) [reset = 0h]
16.5.7.1105 QUEUE_148_STATUS_C Register (offset = 3948h) [reset = 0h]
16.5.7.1106 QUEUE_149_STATUS_A Register (offset = 3950h) [reset = 0h]
16.5.7.1107 QUEUE_149_STATUS_B Register (offset = 3954h) [reset = 0h]
16.5.7.1108 QUEUE_149_STATUS_C Register (offset = 3958h) [reset = 0h]
16.5.7.1109 QUEUE_150_STATUS_A Register (offset = 3960h) [reset = 0h]
16.5.7.1110 QUEUE_150_STATUS_B Register (offset = 3964h) [reset = 0h]
16.5.7.1111 QUEUE_150_STATUS_C Register (offset = 3968h) [reset = 0h]
16.5.7.1112 QUEUE_151_STATUS_A Register (offset = 3970h) [reset = 0h]
16.5.7.1113 QUEUE_151_STATUS_B Register (offset = 3974h) [reset = 0h]
16.5.7.1114 QUEUE_151_STATUS_C Register (offset = 3978h) [reset = 0h]
16.5.7.1115 QUEUE_152_STATUS_A Register (offset = 3980h) [reset = 0h]
16.5.7.1116 QUEUE_152_STATUS_B Register (offset = 3984h) [reset = 0h]
16.5.7.1117 QUEUE_152_STATUS_C Register (offset = 3988h) [reset = 0h]
16.5.7.1118 QUEUE_153_STATUS_A Register (offset = 3990h) [reset = 0h]
16.5.7.1119 QUEUE_153_STATUS_B Register (offset = 3994h) [reset = 0h]
16.5.7.1120 QUEUE_153_STATUS_C Register (offset = 3998h) [reset = 0h]
16.5.7.1121 QUEUE_154_STATUS_A Register (offset = 39A0h) [reset = 0h]
16.5.7.1122 QUEUE_154_STATUS_B Register (offset = 39A4h) [reset = 0h]
16.5.7.1123 QUEUE_154_STATUS_C Register (offset = 39A8h) [reset = 0h]
16.5.7.1124 QUEUE_155_STATUS_A Register (offset = 39B0h) [reset = 0h]
16.5.7.1125 QUEUE_155_STATUS_B Register (offset = 39B4h) [reset = 0h]
16.5.7.1126 QUEUE_155_STATUS_C Register (offset = 39B8h) [reset = 0h]
17 Interprocessor Communication
17.1 Mailbox
17.1.1 Introduction
17.1.1.1 Features
17.1.1.2 Unsupported Features
17.1.2 Integration
17.1.2.1 Mailbox Connectivity Attributes
17.1.2.2 Mailbox Clock and Reset Management
17.1.2.3 Mailbox Pin List
17.1.3 Functional Description
17.1.3.1 Mailbox Block Diagram
17.1.3.2 Software Reset
17.1.3.3 Power Management
17.1.3.4 Interrupt Requests
17.1.3.5 Assignment
17.1.3.5.1 Description
17.1.3.6 Sending and Receiving Messages
17.1.3.6.1 Description
17.1.3.7 16-Bit Register Access
17.1.3.7.1 Description
17.1.4 Programming Guide
17.1.4.1 Low-level Programming Models
17.1.4.1.1 Global Initialization
17.1.4.1.2 Operational Modes Configuration
17.1.4.1.3 Events Servicing
17.1.5 MAILBOX Registers
17.1.5.1 REVISION Register (offset = 0h) [reset = 400h]
17.1.5.2 SYSCONFIG Register (offset = 10h) [reset = 8h]
17.1.5.3 MESSAGE_0 Register (offset = 40h) [reset = 0h]
17.1.5.4 MESSAGE_1 Register (offset = 44h) [reset = 0h]
17.1.5.5 MESSAGE_2 Register (offset = 48h) [reset = 0h]
17.1.5.6 MESSAGE_3 Register (offset = 4Ch) [reset = 0h]
17.1.5.7 MESSAGE_4 Register (offset = 50h) [reset = 0h]
17.1.5.8 MESSAGE_5 Register (offset = 54h) [reset = 0h]
17.1.5.9 MESSAGE_6 Register (offset = 58h) [reset = 0h]
17.1.5.10 MESSAGE_7 Register (offset = 5Ch) [reset = 0h]
17.1.5.11 FIFOSTATUS_0 Register (offset = 80h) [reset = 0h]
17.1.5.12 FIFOSTATUS_1 Register (offset = 84h) [reset = 0h]
17.1.5.13 FIFOSTATUS_2 Register (offset = 88h) [reset = 0h]
17.1.5.14 FIFOSTATUS_3 Register (offset = 8Ch) [reset = 0h]
17.1.5.15 FIFOSTATUS_4 Register (offset = 90h) [reset = 0h]
17.1.5.16 FIFOSTATUS_5 Register (offset = 94h) [reset = 0h]
17.1.5.17 FIFOSTATUS_6 Register (offset = 98h) [reset = 0h]
17.1.5.18 FIFOSTATUS_7 Register (offset = 9Ch) [reset = 0h]
17.1.5.19 MSGSTATUS_0 Register (offset = C0h) [reset = 0h]
17.1.5.20 MSGSTATUS_1 Register (offset = C4h) [reset = 0h]
17.1.5.21 MSGSTATUS_2 Register (offset = C8h) [reset = 0h]
17.1.5.22 MSGSTATUS_3 Register (offset = CCh) [reset = 0h]
17.1.5.23 MSGSTATUS_4 Register (offset = D0h) [reset = 0h]
17.1.5.24 MSGSTATUS_5 Register (offset = D4h) [reset = 0h]
17.1.5.25 MSGSTATUS_6 Register (offset = D8h) [reset = 0h]
17.1.5.26 MSGSTATUS_7 Register (offset = DCh) [reset = 0h]
17.1.5.27 IRQSTATUS_RAW_0 Register (offset = 100h) [reset = 0h]
17.1.5.28 IRQSTATUS_CLR_0 Register (offset = 104h) [reset = 0h]
17.1.5.29 IRQENABLE_SET_0 Register (offset = 108h) [reset = 0h]
17.1.5.30 IRQENABLE_CLR_0 Register (offset = 10Ch) [reset = 0h]
17.1.5.31 IRQSTATUS_RAW_1 Register (offset = 110h) [reset = 0h]
17.1.5.32 IRQSTATUS_CLR_1 Register (offset = 114h) [reset = 0h]
17.1.5.33 IRQENABLE_SET_1 Register (offset = 118h) [reset = 0h]
17.1.5.34 IRQENABLE_CLR_1 Register (offset = 11Ch) [reset = 0h]
17.1.5.35 IRQSTATUS_RAW_2 Register (offset = 120h) [reset = 0h]
17.1.5.36 IRQSTATUS_CLR_2 Register (offset = 124h) [reset = 0h]
17.1.5.37 IRQENABLE_SET_2 Register (offset = 128h) [reset = 0h]
17.1.5.38 IRQENABLE_CLR_2 Register (offset = 12Ch) [reset = 0h]
17.1.5.39 IRQSTATUS_RAW_3 Register (offset = 130h) [reset = 0h]
17.1.5.40 IRQSTATUS_CLR_3 Register (offset = 134h) [reset = 0h]
17.1.5.41 IRQENABLE_SET_3 Register (offset = 138h) [reset = 0h]
17.1.5.42 IRQENABLE_CLR_3 Register (offset = 13Ch) [reset = 0h]
17.2 Spinlock
17.2.1 SPINLOCK Registers
17.2.1.1 REV Register (offset = 0h) [reset = 50020000h]
17.2.1.2 SYSCONFIG Register (offset = 10h) [reset = 11h]
17.2.1.3 SYSTATUS Register (offset = 14h) [reset = 1000001h]
17.2.1.4 LOCK_REG_0 Register (offset = 800h) [reset = 0h]
17.2.1.5 LOCK_REG_1 Register (offset = 804h) [reset = 0h]
17.2.1.6 LOCK_REG_2 Register (offset = 808h) [reset = 0h]
17.2.1.7 LOCK_REG_3 Register (offset = 80Ch) [reset = 0h]
17.2.1.8 LOCK_REG_4 Register (offset = 810h) [reset = 0h]
17.2.1.9 LOCK_REG_5 Register (offset = 814h) [reset = 0h]
17.2.1.10 LOCK_REG_6 Register (offset = 818h) [reset = 0h]
17.2.1.11 LOCK_REG_7 Register (offset = 81Ch) [reset = 0h]
17.2.1.12 LOCK_REG_8 Register (offset = 820h) [reset = 0h]
17.2.1.13 LOCK_REG_9 Register (offset = 824h) [reset = 0h]
17.2.1.14 LOCK_REG_10 Register (offset = 828h) [reset = 0h]
17.2.1.15 LOCK_REG_11 Register (offset = 82Ch) [reset = 0h]
17.2.1.16 LOCK_REG_12 Register (offset = 830h) [reset = 0h]
17.2.1.17 LOCK_REG_13 Register (offset = 834h) [reset = 0h]
17.2.1.18 LOCK_REG_14 Register (offset = 838h) [reset = 0h]
17.2.1.19 LOCK_REG_15 Register (offset = 83Ch) [reset = 0h]
17.2.1.20 LOCK_REG_16 Register (offset = 840h) [reset = 0h]
17.2.1.21 LOCK_REG_17 Register (offset = 844h) [reset = 0h]
17.2.1.22 LOCK_REG_18 Register (offset = 848h) [reset = 0h]
17.2.1.23 LOCK_REG_19 Register (offset = 84Ch) [reset = 0h]
17.2.1.24 LOCK_REG_20 Register (offset = 850h) [reset = 0h]
17.2.1.25 LOCK_REG_21 Register (offset = 854h) [reset = 0h]
17.2.1.26 LOCK_REG_22 Register (offset = 858h) [reset = 0h]
17.2.1.27 LOCK_REG_23 Register (offset = 85Ch) [reset = 0h]
17.2.1.28 LOCK_REG_24 Register (offset = 860h) [reset = 0h]
17.2.1.29 LOCK_REG_25 Register (offset = 864h) [reset = 0h]
17.2.1.30 LOCK_REG_26 Register (offset = 868h) [reset = 0h]
17.2.1.31 LOCK_REG_27 Register (offset = 86Ch) [reset = 0h]
17.2.1.32 LOCK_REG_28 Register (offset = 870h) [reset = 0h]
17.2.1.33 LOCK_REG_29 Register (offset = 874h) [reset = 0h]
17.2.1.34 LOCK_REG_30 Register (offset = 878h) [reset = 0h]
17.2.1.35 LOCK_REG_31 Register (offset = 87Ch) [reset = 0h]
18 Multimedia Card (MMC)
18.1 Introduction
18.1.1 MMCHS Features
18.1.2 Unsupported MMCHS Features
18.2 Integration
18.2.1 MMCHS Connectivity Attributes
18.2.2 MMCHS Clock and Reset Management
18.2.3 MMCHS Pin List
18.3 Functional Description
18.3.1 MMC/SD/SDIO Functional Modes
18.3.1.1 MMC/SD/SDIO Connected to an MMC, an SD Card, or an SDIO Card
18.3.1.2 Protocol and Data Format
18.3.1.2.1 Protocol
18.3.1.2.2 Data Format
18.3.2 Resets
18.3.2.1 Hardware Reset
18.3.2.2 Software Reset
18.3.3 Power Management
18.3.3.1 Normal Mode
18.3.3.2 Idle Mode
18.3.3.3 Transition from Normal Mode to Smart-Idle Mode
18.3.3.4 Transition from Smart-Idle Mode to Normal Mode
18.3.3.5 Force-Idle Mode
18.3.3.6 Local Power Management
18.3.4 Interrupt Requests
18.3.4.1 Interrupt-Driven Operation
18.3.4.2 Polling
18.3.5 DMA Modes
18.3.5.1 DMA Slave Mode Operations
18.3.5.1.1 DMA Receive Mode
18.3.5.1.2 DMA Transmit Mode
18.3.6 Mode Selection
18.3.7 Buffer Management
18.3.7.1 Data Buffer
18.3.7.1.1 Memory Size, Block Length, and Buffer Management Relationship
18.3.7.1.2 Data Buffer Status
18.3.8 Transfer Process
18.3.8.1 Different Types of Commands
18.3.8.2 Different Types of Responses
18.3.9 Transfer or Command Status and Error Reporting
18.3.9.1 Busy Timeout for R1b, R5b Response Type
18.3.9.2 Busy Timeout After Write CRC Status
18.3.9.3 Write CRC Status Timeout
18.3.9.4 Read Data Timeout
18.3.9.5 Boot Acknowledge Timeout
18.3.10 Auto Command 12 Timings
18.3.10.1 Auto Command 12 Timings During Write Transfer
18.3.10.2 Auto Command 12 Timings During Read Transfer
18.3.11 Transfer Stop
18.3.12 Output Signals Generation
18.3.12.1 Generation on Falling Edge of MMC Clock
18.3.12.2 Generation on Rising Edge of MMC Clock
18.3.13 Card Boot Mode Management
18.3.13.1 Boot Mode Using CMD0
18.3.13.2 Boot Mode With CMD Held Low
18.3.14 CE-ATA Command Completion Disable Management
18.3.15 Test Registers
18.3.16 MMC/SD/SDIO Hardware Status Features
18.4 Low-Level Programming Models
18.4.1 Surrounding Modules Global Initialization
18.4.2 MMC/SD/SDIO Controller Initialization Flow
18.4.2.1 Enable OCP and CLKADPI Clocks
18.4.2.2 SD Soft Reset Flow
18.4.2.3 Set SD Default Capabilities
18.4.2.4 Wake-Up Configuration
18.4.2.5 MMC Host and Bus Configuration
18.4.3 Operational Modes Configuration
18.4.3.1 Basic Operations for MMC/SD/SDIO Host Controller
18.4.3.2 Card Detection, Identification, and Selection
18.5 Multimedia Card Registers
18.5.1 MULTIMEDIA_CARD Registers
18.5.1.1 SD_SYSCONFIG Register (offset = 110h) [reset = 0h]
18.5.1.2 SD_SYSSTATUS Register (offset = 114h) [reset = 0h]
18.5.1.3 SD_CSRE Register (offset = 124h) [reset = 0h]
18.5.1.4 SD_SYSTEST Register (offset = 128h) [reset = 0h]
18.5.1.5 SD_CON Register (offset = 12Ch) [reset = 0h]
18.5.1.6 SD_PWCNT Register (offset = 130h) [reset = 0h]
18.5.1.7 SD_SDMASA Register (offset = 200h) [reset = 0h]
18.5.1.8 SD_BLK Register (offset = 204h) [reset = 0h]
18.5.1.9 SD_ARG Register (offset = 208h) [reset = 0h]
18.5.1.10 SD_CMD Register (offset = 20Ch) [reset = 0h]
18.5.1.11 SD_RSP10 Register (offset = 210h) [reset = 0h]
18.5.1.12 SD_RSP32 Register (offset = 214h) [reset = 0h]
18.5.1.13 SD_RSP54 Register (offset = 218h) [reset = 0h]
18.5.1.14 SD_RSP76 Register (offset = 21Ch) [reset = 0h]
18.5.1.15 SD_DATA Register (offset = 220h) [reset = 0h]
18.5.1.16 SD_PSTATE Register (offset = 224h) [reset = 0h]
18.5.1.17 SD_HCTL Register (offset = 228h) [reset = 0h]
18.5.1.18 SD_SYSCTL Register (offset = 22Ch) [reset = 0h]
18.5.1.19 SD_STAT Register (offset = 230h) [reset = 0h]
18.5.1.20 SD_IE Register (offset = 234h) [reset = 0h]
18.5.1.21 SD_ISE Register (offset = 238h) [reset = 0h]
18.5.1.22 SD_AC12 Register (offset = 23Ch) [reset = 0h]
18.5.1.23 SD_CAPA Register (offset = 240h) [reset = 0h]
18.5.1.24 SD_CUR_CAPA Register (offset = 248h) [reset = 0h]
18.5.1.25 SD_FE Register (offset = 250h) [reset = 0h]
18.5.1.26 SD_ADMAES Register (offset = 254h) [reset = 0h]
18.5.1.27 SD_ADMASAL Register (offset = 258h) [reset = 0h]
18.5.1.28 SD_ADMASAH Register (offset = 25Ch) [reset = 0h]
18.5.1.29 SD_REV Register (offset = 2FCh) [reset = 0h]
19 Universal Asynchronous Receiver/Transmitter (UART)
19.1 Introduction
19.1.1 UART Mode Features
19.1.2 IrDA Mode Features
19.1.3 CIR Mode Features
19.1.4 Unsupported UART Features
19.2 Integration
19.2.1 UART Connectivity Attributes
19.2.2 UART Clock and Reset Management
19.2.3 UART Pin List
19.3 Functional Description
19.3.1 Block Diagram
19.3.2 Clock Configuration
19.3.3 Software Reset
19.3.4 Power Management
19.3.4.1 UART Mode Power Management
19.3.4.1.1 Module Power Saving
19.3.4.1.2 System Power Saving
19.3.4.2 IrDA/CIR Mode Power Management
19.3.4.2.1 Module Power Saving
19.3.4.2.2 System Power Saving
19.3.4.3 Local Power Management
19.3.5 Interrupt Requests
19.3.5.1 UART Mode Interrupt Management
19.3.5.1.1 UART Interrupts
19.3.5.2 Wake-Up Interrupt
19.3.5.3 IrDA Mode Interrupt Management
19.3.5.3.1 IrDA Interrupts
19.3.5.4 CIR Mode Interrupt Management
19.3.5.4.1 CIR Interrupts
19.3.6 FIFO Management
19.3.6.1 FIFO Trigger
19.3.6.1.1 Transmit FIFO Trigger
19.3.6.1.2 Receive FIFO Trigger
19.3.6.2 FIFO Interrupt Mode
19.3.6.3 FIFO Polled Mode Operation
19.3.6.4 FIFO DMA Mode Operation
19.3.6.4.1 DMA Transfers (DMA Mode 1, 2, or 3)
19.3.6.4.2 DMA Transmission
19.3.6.4.3 DMA Reception
19.3.7 Mode Selection
19.3.7.1 Register Access Modes
19.3.7.1.1 Operational Mode and Configuration Modes
19.3.7.1.2 Register Access Submode
19.3.7.1.3 Registers Available for the Register Access Modes
19.3.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
19.3.7.2.1 Registers Available for the UART Function
19.3.7.2.2 Registers Available for the IrDA Function
19.3.7.2.3 Registers Available for the CIR Function
19.3.8 Protocol Formatting
19.3.8.1 UART Mode
19.3.8.1.1 UART Clock Generation: Baud Rate Generation
19.3.8.1.2 Choosing the Appropriate Divisor Value
19.3.8.1.3 UART Data Formatting
19.3.8.2 IrDA Mode
19.3.8.2.1 SIR Mode
19.3.8.2.2 MIR Mode
19.3.8.2.3 FIR Mode
19.3.8.2.4 IrDA Clock Generation: Baud Generator
19.3.8.2.5 Choosing the Appropriate Divisor Value
19.3.8.2.6 IrDA Data Formatting
19.3.8.2.7 SIR Mode Data Formatting
19.3.8.2.8 MIR and FIR Mode Data Formatting
19.3.8.3 CIR Mode
19.3.8.3.1 Consumer IR Encoding
19.3.8.3.2 CIR Mode Operation
19.3.8.3.3 Carrier Modulation
19.3.8.3.4 Frequency Divider Values
19.4 UART/IrDA/CIR Basic Programming Model
19.4.1 UART Programming Model
19.4.1.1 Quick Start
19.4.1.1.1 Software Reset
19.4.1.1.2 FIFOs and DMA Settings
19.4.1.1.3 Protocol, Baud Rate, and Interrupt Settings
19.4.1.2 Hardware and Software Flow Control Configuration
19.4.1.2.1 Hardware Flow Control Configuration
19.4.1.2.2 Software Flow Control Configuration
19.4.2 IrDA Programming Model
19.4.2.1 SIR Mode
19.4.2.1.1 Receive
19.4.2.1.2 Transmit
19.4.2.2 MIR Mode
19.4.2.2.1 Receive
19.4.2.2.2 Transmit
19.4.2.3 FIR Mode
19.4.2.3.1 Receive
19.4.2.3.2 Transmit
19.5 UART Registers
19.5.1 UART Registers
19.5.1.1 Receiver Holding Register (RHR)
19.5.1.2 Transmit Holding Register (THR)
19.5.1.3 Interrupt Enable Register (IER) - UART Mode
19.5.1.4 Interrupt Enable Register (IER) - IrDA Mode
19.5.1.5 Interrupt Enable Register (IER) - CIR Mode
19.5.1.6 Interrupt Identification Register (IIR) - UART Mode
19.5.1.7 Interrupt Identification Register (IIR) - IrDA Mode
19.5.1.8 Interrupt Identification Register (IIR) - CIR Mode
19.5.1.9 FIFO Control Register (FCR)
19.5.1.10 Line Control Register (LCR)
19.5.1.11 Modem Control Register (MCR)
19.5.1.12 Line Status Register (LSR) - UART Mode
19.5.1.13 Line Status Register (LSR) - IrDA Mode
19.5.1.14 Line Status Register (LSR) - CIR Mode
19.5.1.15 Modem Status Register (MSR)
19.5.1.16 Transmission Control Register (TCR)
19.5.1.17 Scratchpad Register (SPR)
19.5.1.18 Trigger Level Register (TLR)
19.5.1.19 Mode Definition Register 1 (MDR1)
19.5.1.20 Mode Definition Register 2 (MDR2)
19.5.1.21 Status FIFO Line Status Register (SFLSR)
19.5.1.22 RESUME Register
19.5.1.23 Status FIFO Register Low (SFREGL)
19.5.1.24 Status FIFO Register High (SFREGH)
19.5.1.25 BOF Control Register (BLR)
19.5.1.26 Auxiliary Control Register (ACREG)
19.5.1.27 Supplementary Control Register (SCR)
19.5.1.28 Supplementary Status Register (SSR)
19.5.1.29 BOF Length Register (EBLR)
19.5.1.30 Module Version Register (MVR)
19.5.1.31 System Configuration Register (SYSC)
19.5.1.32 System Status Register (SYSS)
19.5.1.33 Wake-Up Enable Register (WER)
19.5.1.34 Carrier Frequency Prescaler Register (CFPS)
19.5.1.35 Divisor Latches Low Register (DLL)
19.5.1.36 Divisor Latches High Register (DLH)
19.5.1.37 Enhanced Feature Register (EFR)
19.5.1.38 XON1/ADDR1 Register
19.5.1.39 XON2/ADDR2 Register
19.5.1.40 XOFF1 Register
19.5.1.41 XOFF2 Register
19.5.1.42 Transmit Frame Length Low Register (TXFLL)
19.5.1.43 Transmit Frame Length High Register (TXFLH)
19.5.1.44 Received Frame Length Low Register (RXFLL)
19.5.1.45 Received Frame Length High Register (RXFLH)
19.5.1.46 UART Autobauding Status Register (UASR)
19.5.1.47 Received FIFO Level (RXFIFO_LVL) Register
19.5.1.48 Transmit FIFO Level (TXFIFO_LVL) Register
19.5.1.49 IER2 Register
19.5.1.50 ISR2 Register
19.5.1.51 FREQ_SEL Register
19.5.1.52 Mode Definition Register 3 (MDR3) Register
19.5.1.53 TX_DMA_THRESHOLD Register
20 Timers
20.1 DMTimer
20.1.1 Introduction
20.1.1.1 Overview
20.1.1.2 Features
20.1.1.3 Functional Block Diagram
20.1.2 Integration
20.1.2.1 Timer Connectivity Attributes
20.1.2.2 Timer Clock and Reset Management
20.1.2.3 Timer Clock Signals
20.1.2.4 Timer Pin List
20.1.3 Functional Description
20.1.3.1 Functional Description
20.1.3.1.1 Timer Mode Functionality
20.1.3.1.2 Capture Mode Functionality
20.1.3.1.3 Compare Mode Functionality
20.1.3.1.4 Prescaler Functionality
20.1.3.1.5 Pulse-Width Modulation
20.1.3.1.6 Timer Counting Rate
20.1.3.1.7 Dual Mode Timer Under Emulation
20.1.3.2 Accessing Registers
20.1.3.2.1 Programming the Timer Registers
20.1.3.2.2 Reading the Timer Registers
20.1.3.2.3 OCP Error Generation
20.1.3.3 Posted Mode Selection
20.1.3.4 Write Registers Access
20.1.3.4.1 Write Posted
20.1.3.4.2 Write Non-Posted
20.1.3.5 Read Registers Access
20.1.3.5.1 Read Posted
20.1.3.5.2 Read Non-Posted
20.1.4 Use Cases
20.1.5 TIMER Registers
20.1.5.1 TIDR Register (offset = 00h) [reset = 40000100h]
20.1.5.2 TIOCP_CFG Register (offset = 10h) [reset = 0h]
20.1.5.3 IRQSTATUS_RAW Register (offset = 24h) [reset = 0h]
20.1.5.4 IRQSTATUS Register (offset = 28h) [reset = 0h]
20.1.5.5 IRQENABLE_SET Register (offset = 2Ch) [reset = 0h]
20.1.5.6 IRQENABLE_CLR Register (offset = 30h) [reset = 0h]
20.1.5.7 IRQWAKEEN Register (offset = 34h) [reset = 0h]
20.1.5.8 TCLR Register (offset = 38h) [reset = 0h]
20.1.5.9 TCRR Register (offset = 3Ch) [reset = 0h]
20.1.5.10 TLDR Register (offset = 40h) [reset = 0h]
20.1.5.11 TTGR Register (offset = 44h) [reset = FFFFFFFFh]
20.1.5.12 TWPS Register (offset = 48h) [reset = 0h]
20.1.5.13 TMAR Register (offset = 4Ch) [reset = 0h]
20.1.5.14 TCAR1 Register (offset = 50h) [reset = 0h]
20.1.5.15 TSICR Register (offset = 54h) [reset = 0h]
20.1.5.16 TCAR2 Register (offset = 58h) [reset = 0h]
20.2 DMTimer 1ms
20.2.1 Introduction
20.2.2 Integration
20.2.2.1 Timer Connectivity Attributes
20.2.2.2 Timer Clock and Reset Manangement
20.2.2.3 Timer Clock Signals
20.2.3 Functional Description
20.2.3.1 Timer Mode Functionality
20.2.3.1.1 1 ms Tick Generation
20.2.3.2 Capture Mode Functionality
20.2.3.3 Compare Mode Functionality
20.2.3.4 Prescaler Functionality
20.2.3.5 Pulse-Width Modulation
20.2.3.6 Timer Interrupt Control
20.2.3.7 Sleep Mode Request and Acknowledge
20.2.3.7.1 Wake-up Line Release
20.2.3.8 Timer Counting Rate
20.2.3.9 Dual Mode Timer Under Emulation
20.2.4 Use Cases
20.2.5 DMTIMER_1MS Registers
20.2.5.1 TIDR Register (offset = 0h) [reset = 15h]
20.2.5.2 TIOCP_CFG Register (offset = 10h) [reset = 0h]
20.2.5.3 TISTAT Register (offset = 14h) [reset = 0h]
20.2.5.4 TISR Register (offset = 18h) [reset = 0h]
20.2.5.5 TIER Register (offset = 1Ch) [reset = 0h]
20.2.5.6 TWER Register (offset = 20h) [reset = 0h]
20.2.5.7 TCLR Register (offset = 24h) [reset = 0h]
20.2.5.8 TCRR Register (offset = 28h) [reset = 0h]
20.2.5.9 TLDR Register (offset = 2Ch) [reset = 0h]
20.2.5.10 TTGR Register (offset = 30h) [reset = FFFFFFFFh]
20.2.5.11 TWPS Register (offset = 34h) [reset = 0h]
20.2.5.12 TMAR Register (offset = 38h) [reset = 0h]
20.2.5.13 TCAR1 Register (offset = 3Ch) [reset = 0h]
20.2.5.14 TSICR Register (offset = 40h) [reset = 0h]
20.2.5.15 TCAR2 Register (offset = 44h) [reset = 0h]
20.2.5.16 TPIR Register (offset = 48h) [reset = 0h]
20.2.5.17 TNIR Register (offset = 4Ch) [reset = 0h]
20.2.5.18 TCVR Register (offset = 50h) [reset = 0h]
20.2.5.19 TOCR Register (offset = 54h) [reset = 0h]
20.2.5.20 TOWR Register (offset = 58h) [reset = 0h]
20.3 RTC_SS
20.3.1 Introduction
20.3.1.1 Features
20.3.1.2 Unsupported RTC Features
20.3.2 Integration
20.3.2.1 RTC Connectivity Attributes
20.3.2.2 RTC Clock and Reset Management
20.3.2.3 RTC Pin List
20.3.3 Functional Description
20.3.3.1 Functional Block Diagram
20.3.3.2 Clock Source
20.3.3.3 Signal Descriptions
20.3.3.4 Interrupt Support
20.3.3.4.1 CPU Interrupts
20.3.3.4.2 Interrupt Description
20.3.3.5 Programming/Usage Guide
20.3.3.5.1 Time/Calendar Data Format
20.3.3.5.2 Register Access
20.3.3.5.3 OCP MMR Spurious WRT Protection
20.3.3.5.4 Reading the Timer/Calendar (TC) Registers
20.3.3.5.5 Modifying the TC Registers
20.3.3.5.6 Crystal Compensation
20.3.3.6 Scratch Registers
20.3.3.7 Power Management
20.3.3.8 Power Management—System Level (PMIC Mode)
20.3.4 Use Cases
20.3.5 RTC Registers
20.3.5.1 SECONDS_REG Register (offset = 0h) [reset = 0h]
20.3.5.2 MINUTES_REG Register (offset = 4h) [reset = 0h]
20.3.5.3 HOURS_REG Register (offset = 8h) [reset = 0h]
20.3.5.4 DAYS_REG Register (offset = Ch) [reset = 1h]
20.3.5.5 MONTHS_REG Register (offset = 10h) [reset = 1h]
20.3.5.6 YEARS_REG Register (offset = 14h) [reset = 0h]
20.3.5.7 WEEKS_REG Register (offset = 18h) [reset = 0h]
20.3.5.8 ALARM_SECONDS_REG Register (offset = 20h) [reset = 0h]
20.3.5.9 ALARM_MINUTES_REG Register (offset = 24h) [reset = 0h]
20.3.5.10 ALARM_HOURS_REG Register (offset = 28h) [reset = 0h]
20.3.5.11 ALARM_DAYS_REG Register (offset = 2Ch) [reset = 1h]
20.3.5.12 ALARM_MONTHS_REG Register (offset = 30h) [reset = 1h]
20.3.5.13 ALARM_YEARS_REG Register (offset = 34h) [reset = 0h]
20.3.5.14 RTC_CTRL_REG Register (offset = 40h) [reset = 0h]
20.3.5.15 RTC_STATUS_REG Register (offset = 44h) [reset = 0h]
20.3.5.16 RTC_INTERRUPTS_REG Register (offset = 48h) [reset = 0h]
20.3.5.17 RTC_COMP_LSB_REG Register (offset = 4Ch) [reset = 0h]
20.3.5.18 RTC_COMP_MSB_REG Register (offset = 50h) [reset = 0h]
20.3.5.19 RTC_OSC_REG Register (offset = 54h) [reset = 10h]
20.3.5.20 RTC_SCRATCH0_REG Register (offset = 60h) [reset = 0h]
20.3.5.21 RTC_SCRATCH1_REG Register (offset = 64h) [reset = 0h]
20.3.5.22 RTC_SCRATCH2_REG Register (offset = 68h) [reset = 0h]
20.3.5.23 KICK0R Register (offset = 6Ch) [reset = 0h]
20.3.5.24 KICK1R Register (offset = 70h) [reset = 0h]
20.3.5.25 RTC_REVISION Register (offset = 74h) [reset = 4EB00904h]
20.3.5.26 RTC_SYSCONFIG Register (offset = 78h) [reset = 2h]
20.3.5.27 RTC_IRQWAKEEN Register (offset = 7Ch) [reset = 0h]
20.3.5.28 ALARM2_SECONDS_REG Register (offset = 80h) [reset = 0h]
20.3.5.29 ALARM2_MINUTES_REG Register (offset = 84h) [reset = 0h]
20.3.5.30 ALARM2_HOURS_REG Register (offset = 88h) [reset = 0h]
20.3.5.31 ALARM2_DAYS_REG Register (offset = 8Ch) [reset = 1h]
20.3.5.32 ALARM2_MONTHS_REG Register (offset = 90h) [reset = 1h]
20.3.5.33 ALARM2_YEARS_REG Register (offset = 94h) [reset = 0h]
20.3.5.34 RTC_PMIC Register (offset = 98h) [reset = 0h]
20.3.5.35 RTC_DEBOUNCE Register (offset = 9Ch) [reset = 0h]
20.4 WATCHDOG
20.4.1 Introduction
20.4.1.1 Features
20.4.1.2 Unsupported Featres
20.4.2 Integration
20.4.2.1 Public WD Timer Connectivity Attributes
20.4.2.2 Public WD Timer Clock and Reset Management
20.4.3 Functional Description
20.4.3.1 Power Management
20.4.3.2 Interrupts
20.4.3.3 General Watchdog Timer Operation
20.4.3.4 Reset Context
20.4.3.5 Overflow/Reset Generation
20.4.3.6 Prescaler Value/Timer Reset Frequency
20.4.3.7 Triggering a Timer Reload
20.4.3.8 Start/Stop Sequence for Watchdog Timers (Using the WDT_WSPR Register)
20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting
20.4.3.10 Watchdog Counter Register Access Restriction (WDT_WCRR Register)
20.4.3.11 Watchdog Timer Interrupt Generation
20.4.3.12 Watchdog Timers Under Emulation
20.4.3.13 Accessing Watchdog Timer Registers
20.4.3.14 Low-Level Programming Model
20.4.3.14.1 Global Initialization
20.4.3.14.2 Operational Mode Configuration
20.4.4 Watchdog Registers
20.4.4.1 WATCHDOG_TIMER Registers
20.4.4.1.1 WDT_WIDR Register (offset = 0h) [reset = 0h]
20.4.4.1.2 WDT_WDSC Register (offset = 10h) [reset = 0h]
20.4.4.1.3 WDT_WDST Register (offset = 14h) [reset = 1h]
20.4.4.1.4 WDT_WISR Register (offset = 18h) [reset = 0h]
20.4.4.1.5 WDT_WIER Register (offset = 1Ch) [reset = 0h]
20.4.4.1.6 WDT_WCLR Register (offset = 24h) [reset = 20h]
20.4.4.1.7 WDT_WCRR Register (offset = 28h) [reset = 0h]
20.4.4.1.8 WDT_WLDR Register (offset = 2Ch) [reset = 0h]
20.4.4.1.9 WDT_WTGR Register (offset = 30h) [reset = 0h]
20.4.4.1.10 WDT_WWPS Register (offset = 34h) [reset = 0h]
20.4.4.1.11 WDT_WDLY Register (offset = 44h) [reset = 0h]
20.4.4.1.12 WDT_WSPR Register (offset = 48h) [reset = 0h]
20.4.4.1.13 WDT_WIRQSTATRAW Register (offset = 54h) [reset = 0h]
20.4.4.1.14 WDT_WIRQSTAT Register (offset = 58h) [reset = 0h]
20.4.4.1.15 WDT_WIRQENSET Register (offset = 5Ch) [reset = 0h]
20.4.4.1.16 WDT_WIRQENCLR Register (offset = 60h) [reset = 0h]
21 I2C
21.1 Introduction
21.1.1 I2C Features
21.1.2 Unsupported I2C Features
21.2 Integration
21.2.1 I2C Connectivity Attributes
21.2.2 I2C Clock and Reset Management
21.2.3 I2C Pin List
21.3 Functional Description
21.3.1 Functional Block Diagram
21.3.2 I2C Master/Slave Contoller Signals
21.3.3 I2C Reset
21.3.4 Data Validity
21.3.5 START & STOP Conditions
21.3.6 I2C Operation
21.3.6.1 Serial Data Formats
21.3.6.2 Master Transmitter
21.3.6.3 Master Receiver
21.3.6.4 Slave Transmitter
21.3.6.5 Slave Receiver
21.3.7 Arbitration
21.3.8 I2C Clock Generation and I2C Clock Synchronization
21.3.9 Prescaler (SCLK/ICLK)
21.3.10 Noise Filter
21.3.11 I2C Interrupts
21.3.12 DMA Events
21.3.13 Interrupt and DMA Events
21.3.14 FIFO Management
21.3.14.1 FIFO Interrupt Mode Operation
21.3.14.2 FIFO Polling Mode Operation
21.3.14.3 FIFO DMA Mode Operation
21.3.14.4 Draining Feature
21.3.15 How to Program I2C
21.3.15.1 Module Configuration Before Enabling the Module
21.3.15.2 Initialization Procedure
21.3.15.3 Configure Slave Address and DATA Counter Registers
21.3.15.4 Initiate a Transfer
21.3.15.5 Receive Data
21.3.15.6 Transmit Data
21.4 Registers
21.4.1 I2C Registers
21.4.1.1 I2C_REVNB_LO Register (Module Revision LOW BYTES)
21.4.1.2 I2C_REVNB_HI Register (HIGH BYTES) (Module Revision)
21.4.1.3 I2C_SYSC Register (System Configuration)
21.4.1.4 I2C_IRQSTATUS_RAW Register (I2C Status Raw)
21.4.1.5 I2C_IRQSTATUS Register (I2C Status)
21.4.1.6 I2C_IRQENABLE_SET Register (I2C Interrupt Enable Set)
21.4.1.7 I2C_IRQENABLE_CLR Register (I2C Interrupt Enable Clear)
21.4.1.8 I2C_WE Register (I2C Wakeup Enable)
21.4.1.9 I2C_DMARXENABLE_SET Register (Receive DMA Enable Set)
21.4.1.10 I2C_DMATXENABLE_SET Register (Transmit DMA Enable Set)
21.4.1.11 I2C_DMARXENABLE_CLR Register (Receive DMA Enable Clear)
21.4.1.12 I2C_DMATXENABLE_CLR Register (Transmit DMA Enable Clear)
21.4.1.13 I2C_DMARXWAKE_EN Register (Receive DMA Wakeup)
21.4.1.14 I2C_DMATXWAKE_EN Register (Transmit DMA Wakeup)
21.4.1.15 I2C_SYSS Register (System Status)
21.4.1.16 I2C_BUF Register (Buffer Configuration)
21.4.1.17 I2C_CNT Register (Data Counter)
21.4.1.18 I2C_DATA Register (Data Access)
21.4.1.19 I2C_CON Register (I2C Configuration)
21.4.1.20 I2C_OA Register (I2C Own Address)
21.4.1.21 I2C_SA Register (I2C Slave Address)
21.4.1.22 I2C_PSC Register (I2C Clock Prescaler)
21.4.1.23 I2C_SCLL Register (I2C SCL Low Time)
21.4.1.24 I2C_SCLH Register (I2C SCL High Time)
21.4.1.25 I2C_SYSTEST Register (System Test)
21.4.1.26 I2C_BUFSTAT Register (I2C Buffer Status)
21.4.1.27 I2C_OA1 Register (OA1) (Own Address 1)
21.4.1.28 I2C_OA2 Register (I2C Own Address 2)
21.4.1.29 I2C_OA3 Register (I2C Own Address 3)
21.4.1.30 I2C_ACTOA Register (Active Own Address)
21.4.1.31 I2C_SBLOCK Register (I2C Clock Blocking Enable)
22 Multichannel Audio Serial Port (McASP)
22.1 Introduction
22.1.1 Purpose of the Peripheral
22.1.2 Features
22.1.3 Protocols Supported
22.1.4 Unsupported McASP Features
22.2 Integration
22.2.1 McASP Connectivity Attributes
22.2.2 McASP Clock and Reset Management
22.2.3 McASP Pin List
22.3 Functional Description
22.3.1 Overview
22.3.2 Functional Block Diagram
22.3.2.1 System Level Connections
22.3.3 Industry Standard Compliance Statement
22.3.3.1 TDM Format
22.3.3.1.1 TDM Format
22.3.3.1.2 Inter-Integrated Sound (I2S) Format
22.3.3.2 S/PDIF Coding Format
22.3.3.2.1 Biphase-Mark Code (BMC)
22.3.3.2.2 Subframe Format
22.3.3.2.3 Frame Format
22.3.4 Definition of Terms
22.3.5 Clock and Frame Sync Generators
22.3.5.1 Transmit Clock
22.3.5.2 Receive Clock
22.3.5.3 Frame Sync Generator
22.3.5.4 Clocking Examples
22.3.6 Signal Descriptions
22.3.7 Pin Multiplexing
22.3.8 Transfer Modes
22.3.8.1 Burst Transfer Mode
22.3.8.2 Time-Division Multiplexed (TDM) Transfer Mode
22.3.8.2.1 TDM Time Slots
22.3.8.2.2 Special 384 Slot TDM Mode for Connection to External DIR
22.3.8.3 Digital Audio Interface Transmit (DIT) Transfer Mode
22.3.8.3.1 Transmit DIT Encoding
22.3.8.3.2 Transmit DIT Clock and Frame Sync Generation
22.3.8.3.3 DIT Channel Status and User Data Register Files
22.3.9 General Architecture
22.3.9.1 Serializers
22.3.9.2 Format Unit
22.3.9.3 State Machine
22.3.9.4 TDM Sequencer
22.3.9.5 Clock Check Circuit
22.3.9.6 Pin Function Control
22.3.9.6.1 McASP Pin Control-Transmit and Receive
22.3.10 Operation
22.3.10.1 Data Transmission and Reception
22.3.10.1.1 Data Ready Status and Event/Interrupt Generation
22.3.10.1.2 Transfers Through the Data Port (DAT)
22.3.10.1.3 Transfers Through the Configuration Bus (CFG)
22.3.10.1.4 Using the CPU for McASP Servicing
22.3.10.2 McASP Audio FIFO (AFIFO)
22.3.10.2.1 AFIFO Data Transmission
22.3.10.2.2 AFIFO Data Reception
22.3.10.2.3 Arbitration Between Transmit and Receive DMA Requests
22.3.10.3 Formatter
22.3.10.3.1 Transmit Bit Stream Data Alignment
22.3.10.3.2 Receive Bit Stream Data Alignment
22.3.10.4 Error Handling and Management
22.3.10.4.1 Unexpected Frame Sync Error
22.3.10.4.2 Buffer Underrun Error - Transmitter
22.3.10.4.3 Buffer Overrun Error - Receiver
22.3.10.4.4 DMA Error - Transmitter
22.3.10.4.5 DMA Error - Receiver
22.3.10.4.6 Clock Failure Detection
22.3.10.5 Loopback Modes
22.3.10.5.1 Loopback Mode Configurations
22.3.11 Reset Considerations
22.3.11.1 Software Reset Considerations
22.3.11.2 Hardware Reset Considerations
22.3.12 Setup and Initialization
22.3.12.1 Considerations When Using a McASP
22.3.12.1.1 Clocks
22.3.12.1.2 Data Pins
22.3.12.1.3 Data Format
22.3.12.1.4 Data Transfers
22.3.12.2 Transmit/Receive Section Initialization
22.3.12.3 Separate Transmit and Receive Initialization
22.3.12.4 Importance of Reading Back GBLCTL
22.3.12.5 Synchronous Transmit and Receive Operation (ASYNC = 0)
22.3.12.6 Asynchronous Transmit and Receive Operation (ASYNC = 1)
22.3.13 Interrupts
22.3.13.1 Interrupt Multiplexing
22.3.13.2 Transmit Data Ready Interrupt
22.3.13.3 Receive Data Ready Interrupt
22.3.13.4 Error Interrupts
22.3.13.5 Audio Mute (AMUTE) Function
22.3.13.6 Multiple Interrupts
22.3.14 EDMA Event Support
22.3.14.1 EDMA Events
22.3.14.2 Using the DMA for McASP Servicing
22.3.15 Power Management
22.3.16 Emulation Considerations
22.4 McASP Registers
22.4.1 McASP CFG Registers
22.4.1.1 Revision Identification Register (REV)
22.4.1.2 Pin Function Register (PFUNC)
22.4.1.3 Pin Direction Register (PDIR)
22.4.1.4 Pin Data Output Register (PDOUT)
22.4.1.5 Pin Data Input Register (PDIN)
22.4.1.6 Pin Data Set Register (PDSET)
22.4.1.7 Pin Data Clear Register (PDCLR)
22.4.1.8 Global Control Register (GBLCTL)
22.4.1.9 Audio Mute Control Register (AMUTE)
22.4.1.10 Digital Loopback Control Register (DLBCTL)
22.4.1.11 Digital Mode Control Register (DITCTL)
22.4.1.12 Receiver Global Control Register (RGBLCTL)
22.4.1.13 Receive Format Unit Bit Mask Register (RMASK)
22.4.1.14 Receive Bit Stream Format Register (RFMT)
22.4.1.15 Receive Frame Sync Control Register (AFSRCTL)
22.4.1.16 Receive Clock Control Register (ACLKRCTL)
22.4.1.17 Receive High-Frequency Clock Control Register (AHCLKRCTL)
22.4.1.18 Receive TDM Time Slot Register (RTDM)
22.4.1.19 Receiver Interrupt Control Register (RINTCTL)
22.4.1.20 Receiver Status Register (RSTAT)
22.4.1.21 Current Receive TDM Time Slot Registers (RSLOT)
22.4.1.22 Receive Clock Check Control Register (RCLKCHK)
22.4.1.23 Receiver DMA Event Control Register (REVTCTL)
22.4.1.24 Transmitter Global Control Register (XGBLCTL)
22.4.1.25 Transmit Format Unit Bit Mask Register (XMASK)
22.4.1.26 Transmit Bit Stream Format Register (XFMT)
22.4.1.27 Transmit Frame Sync Control Register (AFSXCTL)
22.4.1.28 Transmit Clock Control Register (ACLKXCTL)
22.4.1.29 Transmit High-Frequency Clock Control Register (AHCLKXCTL)
22.4.1.30 Transmit TDM Time Slot Register (XTDM)
22.4.1.31 Transmitter Interrupt Control Register (XINTCTL)
22.4.1.32 Transmitter Status Register (XSTAT)
22.4.1.33 Current Transmit TDM Time Slot Register (XSLOT)
22.4.1.34 Transmit Clock Check Control Register (XCLKCHK)
22.4.1.35 Transmitter DMA Event Control Register (XEVTCTL)
22.4.1.36 Serializer Control Registers (SRCTLn)
22.4.1.37 DIT Left Channel Status Registers (DITCSRA0-DITCSRA5)
22.4.1.38 DIT Right Channel Status Registers (DITCSRB0-DITCSRB5)
22.4.1.39 DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5)
22.4.1.40 DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5)
22.4.1.41 Transmit Buffer Registers (XBUFn)
22.4.1.42 Receive Buffer Registers (RBUFn)
22.4.1.43 Write FIFO Control Register (WFIFOCTL)
22.4.1.44 Write FIFO Status Register (WFIFOSTS)
22.4.1.45 Read FIFO Control Register (RFIFOCTL)
22.4.1.46 Read FIFO Status Register (RFIFOSTS)
22.4.2 McASP Data Port Registers
23 Controller Area Network (CAN)
23.1 Introduction
23.1.1 DCAN Features
23.1.2 Unsupported DCAN Features
23.2 Integration
23.2.1 DCAN Connectivity Attributes
23.2.2 DCAN Clock and Reset Management
23.2.3 DCAN Pin List
23.3 Functional Description
23.3.1 CAN Core
23.3.2 Message Handler
23.3.3 Message RAM
23.3.4 Message RAM Interface
23.3.5 Registers and Message Object Access
23.3.6 Module Interface
23.3.7 Dual Clock Source
23.3.8 CAN Operation
23.3.8.1 CAN Module Initialization
23.3.8.1.1 Configuration of CAN Bit Timing
23.3.8.1.2 Configuration of Message Objects
23.3.8.1.3 DCAN RAM Hardware Initialization
23.3.8.2 CAN Message Transfer (Normal Operation)
23.3.8.2.1 Automatic Retransmission
23.3.8.2.2 Auto-Bus-On
23.3.8.3 Test Modes
23.3.8.3.1 Silent Mode
23.3.8.3.2 Loopback Mode
23.3.8.3.3 External Loopback Mode
23.3.8.3.4 Loopback Mode Combined With Silent Mode
23.3.8.3.5 Software Control of CAN_TX pin
23.3.9 Dual Clock Source
23.3.10 Interrupt Functionality
23.3.10.1 Message Object Interrupts
23.3.10.2 Status Change Interrupts
23.3.10.3 Error Interrupts
23.3.11 Local Power-Down Mode
23.3.11.1 Entering Local Power-Down Mode
23.3.11.2 Wakeup From Local Power Down
23.3.12 Parity Check Mechanism
23.3.12.1 Behavior on Parity Error
23.3.12.2 Parity Testing
23.3.13 Debug/Suspend Mode
23.3.14 Configuration of Message Objects
23.3.14.1 Configuration of a Transmit Object for Data Frames
23.3.14.2 Configuration of a Transmit Object for Remote Frames
23.3.14.3 Configuration of a Single Receive Object for Data Frames
23.3.14.4 Configuration of a Single Receive Object for Remote Frames
23.3.14.5 Configuration of a FIFO Buffer
23.3.15 Message Handling
23.3.15.1 Message Handler Overview
23.3.15.2 Receive/Transmit Priority
23.3.15.3 Transmission of Messages in Event-Driven CAN Communication
23.3.15.4 Updating a Transmit Object
23.3.15.5 Changing a Transmit Object
23.3.15.6 Acceptance Filtering of Received Messages
23.3.15.7 Reception of Data Frames
23.3.15.8 Reception of Remote Frames
23.3.15.9 Reading Received Messages
23.3.15.10 Requesting New Data for a Receive Object
23.3.15.11 Storing Received Messages in FIFO Buffers
23.3.15.12 Reading From a FIFO Buffer
23.3.16 CAN Bit Timing
23.3.16.1 Bit Time and Bit Rate
23.3.16.1.1 Synchronization Segment
23.3.16.1.2 Propagation Time Segment
23.3.16.1.3 Phase Buffer Segments and Synchronization
23.3.16.1.4 Oscillator Tolerance Range
23.3.16.2 DCAN Bit Timing Registers
23.3.16.2.1 Calculation of the Bit Timing Parameters
23.3.16.2.2 Example for Bit Timing at High Baud Rate
23.3.16.2.3 Example for Bit Timing at Low Baud Rate
23.3.17 Message Interface Register Sets
23.3.17.1 Message Interface Register Sets 1 and 2
23.3.17.2 IF3 Register Set
23.3.18 Message RAM
23.3.18.1 Structure of Message Objects
23.3.18.2 Addressing Message Objects in RAM
23.3.18.3 Message RAM Representation in Debug/Suspend Mode
23.3.18.4 Message RAM Representation in Direct Access Mode
23.3.19 GIO Support
23.4 DCAN Registers
23.4.1 DCAN Control Registers
23.4.1.1 CAN Control Register (DCAN CTL)
23.4.1.2 Error and Status Register (DCAN ES)
23.4.1.3 Error Counter Register (DCAN ERRC)
23.4.1.4 Bit Timing Register (DCAN BTR)
23.4.1.5 Interrupt Register (DCAN INT)
23.4.1.6 Test Register (DCAN TEST)
23.4.1.7 Parity Error Code Register (DCAN PERR)
23.4.1.8 Auto-Bus-On Time Register (DCAN ABOTR)
23.4.1.9 Transmission Request X Register (DCAN TXRQ X)
23.4.1.10 Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78)
23.4.1.11 New Data X Register (DCAN NWDAT X)
23.4.1.12 New Data Registers (DCAN NWDAT12 to DCAN NWDAT78)
23.4.1.13 Interrupt Pending X Register (DCAN INTPND X)
23.4.1.14 Interrupt Pending Registers (DCAN INTPND12 to DCAN INTPND78)
23.4.1.15 Message Valid X Register (DCAN MSGVAL X)
23.4.1.16 Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78)
23.4.1.17 Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78)
23.4.1.18 IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD)
23.4.1.19 IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK)
23.4.1.20 IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB)
23.4.1.21 IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL)
23.4.1.22 IF1/IF2 Data A and Data B Registers (DCAN IF1DATA/DATB, DCAN IF2DATA/DATB)
23.4.1.23 IF3 Observation Register (DCAN IF3OBS)
23.4.1.24 IF3 Mask Register (DCAN IF3MSK)
23.4.1.25 IF3 Arbitration Register (DCAN IF3ARB)
23.4.1.26 IF3 Message Control Register (DCAN IF3MCTL)
23.4.1.27 IF3 Data A and Data B Registers (DCAN IF3DATA/DATB)
23.4.1.28 Update Enable Registers (DCAN IF3UPD12 to IF3UPD78)
23.4.1.29 CAN TX I/O Control Register (DCAN TIOC)
23.4.1.30 CAN RX IO Control Register (DCAN RIOC)
24 Multichannel Serial Port Interface (McSPI)
24.1 Introduction
24.1.1 McSPI Features
24.1.2 Unsupported McSPI Features
24.2 Integration
24.2.1 McSPI Connectivity Attributes
24.2.2 McSPI Clock and Reset Management
24.2.3 McSPI Pin List
24.3 Functional Description
24.3.1 SPI Transmission
24.3.1.1 Two Data Pins Interface Mode
24.3.1.2 Single Data Pin Interface Mode
24.3.1.2.1 Example With a Receive-Only Slave
24.3.1.2.2 Example With a Transmit-Only Slave
24.3.1.3 Transfer Formats
24.3.1.3.1 Programmable Word Length
24.3.1.3.2 Programmable SPI Enable Generation
24.3.1.3.3 Programmable SPI Enable (SPIEN)
24.3.1.3.4 Programmable SPI Clock (SPICLK)
24.3.1.3.5 Bit Rate
24.3.1.3.6 Polarity and Phase
24.3.1.3.7 Transfer Format With PHA = 0
24.3.1.3.8 Transfer Format With PHA = 1
24.3.2 Master Mode
24.3.2.1 Dedicated Resources Per Channel
24.3.2.2 Interrupt Events in Master Mode
24.3.2.2.1 TX_empty
24.3.2.2.2 TX_underflow
24.3.2.2.3 RX_ full
24.3.2.2.4 End of Word Count
24.3.2.3 Master Transmit and Receive Mode
24.3.2.4 Master Transmit-Only Mode
24.3.2.5 Master Receive-Only Mode
24.3.2.6 Single-Channel Master Mode
24.3.2.6.1 Programming Tips When Switching to Another Channel
24.3.2.6.2 Keep SPIEN Active Mode (Force SPIEN)
24.3.2.6.3 Turbo Mode
24.3.2.7 Start Bit Mode
24.3.2.8 Chip-Select Timing Control
24.3.2.9 Clock Ratio Granularity
24.3.2.10 FIFO Buffer Management (Optional USEFIFO = 1)
24.3.2.10.1 Split FIFO
24.3.2.10.2 Buffer Almost Full
24.3.2.10.3 Buffer Almost Empty
24.3.2.10.4 End of Transfer Management
24.3.2.10.5 Multiple SPI Word Access
24.3.2.11 First SPI Word Delayed
24.3.2.12 3- or 4-Pin Mode
24.3.3 Slave Mode
24.3.3.1 Dedicated Resources
24.3.3.2 Interrupt Events in Slave Mode
24.3.3.2.1 TX_EMPTY
24.3.3.2.2 TX_UNDERFLOW
24.3.3.2.3 RX_FULL
24.3.3.2.4 RX_OVERFLOW
24.3.3.2.5 End of Word Count
24.3.3.3 Slave Transmit-and-Receive Mode
24.3.3.4 Slave Receive-Only Mode
24.3.3.5 Slave Transmit-Only Mode
24.3.4 Interrupts
24.3.4.1 Interrupt-Driven Operation
24.3.4.2 Polling
24.3.5 DMA Requests
24.3.5.1 FIFO Buffer Disabled
24.3.5.2 FIFO Buffer Enabled
24.3.5.3 DMA 256-Bit Aligned Addresses
24.3.6 Emulation Mode
24.3.7 Power Saving Management
24.3.7.1 Normal Mode
24.3.7.2 Idle Mode
24.3.7.2.1 Transitions from Normal Mode to Smart-Idle Mode
24.3.7.2.2 Transition From Smart-Idle Mode to Normal mode
24.3.7.2.3 Force-Idle Mode
24.3.8 System Test Mode
24.3.9 Reset
24.3.9.1 Internal Reset Monitoring
24.3.9.2 Reset Values of Registers
24.3.10 Access to Data Registers
24.3.11 Programming Aid
24.3.11.1 Module Initialization
24.3.11.2 Common Transfer Sequence
24.3.11.3 Main Program
24.3.12 Interrupt and DMA Events
24.4 McSPI Registers
24.4.1 SPI Registers
24.4.1.1 McSPI Revision Register (MCSPI_REVISION)
24.4.1.2 McSPI System Configuration Register (MCSPI_SYSCONFIG)
24.4.1.3 McSPI System Status Register (MCSPI_SYSSTATUS)
24.4.1.4 McSPI Interrupt Status Register (MCSPI_IRQSTATUS)
24.4.1.5 McSPI Interrupt Enable Register (MCSPI_IRQENABLE)
24.4.1.6 McSPI System Register (MCSPI_SYST)
24.4.1.7 McSPI Module Control Register (MCSPI_MODULCTRL)
24.4.1.8 McSPI Channel (i) Configuration Register (MCSPI_CH(i)CONF)
24.4.1.9 McSPI Channel (i) Status Register (MCSPI_CH(i)STAT)
24.4.1.10 McSPI Channel (i) Control Register (MCSPI_CH(I)CTRL)
24.4.1.11 McSPI Channel (i) Transmit Register (MCSPI_TX(i))
24.4.1.12 McSPI Channel (i) Receive Register (MCSPI_RX(i))
24.4.1.13 McSPI Transfer Levels Register (MCSPI_XFERLEVEL)
24.4.1.14 McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX)
24.4.1.15 McSPI DMA Address Aligned FIFO Receiver Register (MCSPI_DAFRX)
25 General-Purpose Input/Output
25.1 Introduction
25.1.1 Purpose of the Peripheral
25.1.2 GPIO Features
25.1.3 Unsupported GPIO Features
25.2 Integration
25.2.1 GPIO Connectivity Attributes
25.2.2 GPIO Clock and Reset Management
25.2.3 GPIO Pin List
25.3 Functional Description
25.3.1 Operating Modes
25.3.2 Clocking and Reset Strategy
25.3.2.1 Clocks
25.3.2.2 Clocks, Gating and Active Edge Definitions
25.3.2.3 Sleep Mode Request and Acknowledge
25.3.2.4 Reset
25.3.3 Interrupt Features
25.3.3.1 Functional Description
25.3.3.2 Synchronous Path: Interrupt Request Generation
25.3.3.3 Interrupt Line Release
25.3.4 General-Purpose Interface Basic Programming Model
25.3.4.1 Power Saving by Grouping the Edge/Level Detection
25.3.4.2 Set and Clear Instructions
25.3.4.2.1 Clear Instruction
25.3.4.2.2 Set Instruction
25.3.4.3 Data Input (Capture)/Output (Drive)
25.3.4.4 Debouncing Time
25.3.4.5 GPIO as a Keyboard Interface
25.4 GPIO Registers
25.4.1 GPIO Registers
25.4.1.1 GPIO_REVISION Register (offset = 0h) [reset = 50600801h]
25.4.1.2 GPIO_SYSCONFIG Register (offset = 10h) [reset = 0h]
25.4.1.3 GPIO_IRQSTATUS_RAW_0 Register (offset = 24h) [reset = 0h]
25.4.1.4 GPIO_IRQSTATUS_RAW_1 Register (offset = 28h) [reset = 0h]
25.4.1.5 GPIO_IRQSTATUS_0 Register (offset = 2Ch) [reset = 0h]
25.4.1.6 GPIO_IRQSTATUS_1 Register (offset = 30h) [reset = 0h]
25.4.1.7 GPIO_IRQSTATUS_SET_0 Register (offset = 34h) [reset = 0h]
25.4.1.8 GPIO_IRQSTATUS_SET_1 Register (offset = 38h) [reset = 0h]
25.4.1.9 GPIO_IRQSTATUS_CLR_0 Register (offset = 3Ch) [reset = 0h]
25.4.1.10 GPIO_IRQSTATUS_CLR_1 Register (offset = 40h) [reset = 0h]
25.4.1.11 GPIO_IRQWAKEN_0 Register (offset = 44h) [reset = 0h]
25.4.1.12 GPIO_IRQWAKEN_1 Register (offset = 48h) [reset = 0h]
25.4.1.13 GPIO_SYSSTATUS Register (offset = 114h) [reset = 0h]
25.4.1.14 GPIO_CTRL Register (offset = 130h) [reset = 0h]
25.4.1.15 GPIO_OE Register (offset = 134h) [reset = FFFFFFFFh]
25.4.1.16 GPIO_DATAIN Register (offset = 138h) [reset = 0h]
25.4.1.17 GPIO_DATAOUT Register (offset = 13Ch) [reset = 0h]
25.4.1.18 GPIO_LEVELDETECT0 Register (offset = 140h) [reset = 0h]
25.4.1.19 GPIO_LEVELDETECT1 Register (offset = 144h) [reset = 0h]
25.4.1.20 GPIO_RISINGDETECT Register (offset = 148h) [reset = 0h]
25.4.1.21 GPIO_FALLINGDETECT Register (offset = 14Ch) [reset = 0h]
25.4.1.22 GPIO_DEBOUNCENABLE Register (offset = 150h) [reset = 0h]
25.4.1.23 GPIO_DEBOUNCINGTIME Register (offset = 154h) [reset = 0h]
25.4.1.24 GPIO_CLEARDATAOUT Register (offset = 190h) [reset = 0h]
25.4.1.25 GPIO_SETDATAOUT Register (offset = 194h) [reset = 0h]
26 Initialization
26.1 Functional Description
26.1.1 Architecture
26.1.2 Functionality
26.1.3 Memory Map
26.1.3.1 Public ROM Memory Map
26.1.3.2 Public RAM Memory Map
26.1.4 Start-up and Configuration
26.1.4.1 ROM Code Start-up
26.1.4.2 CPU State at Public Startup
26.1.4.3 Clocking Configuration
26.1.5 Booting
26.1.5.1 Overview
26.1.5.2 Device List
26.1.5.2.1 SYSBOOT Configuration Pins
26.1.6 Fast External Booting
26.1.6.1 Overview
26.1.6.2 External Booting
26.1.7 Memory Booting
26.1.7.1 Overview
26.1.7.2 XIP Memory
26.1.7.2.1 XIP Initialization and Detection
26.1.7.2.2 Pins Used
26.1.7.2.3 Sysboot Pins
26.1.7.3 Image Shadowing for Non-XIP Memories
26.1.7.3.1 Shadowing on GP Device
26.1.7.4 NAND
26.1.7.4.1 Features
26.1.7.4.2 Initialization and Detection
26.1.7.5 MMC / SD Cards
26.1.7.5.1 Overview
26.1.7.5.2 System Interconnection
26.1.7.5.3 Booting Procedure
26.1.7.5.4 Initialization and Detection
26.1.7.5.5 MMC/SD Read Sector Procedure in Raw mode
26.1.7.5.6 MMC/SD Read Sector Procedure in FAT Mode
26.1.7.5.7 FAT File system
26.1.7.5.8 Pins Used
26.1.7.6 SPI
26.1.7.6.1 Features
26.1.7.6.2 Initialization and Detection
26.1.7.6.3 SPI Read Sector Procedure
26.1.7.6.4 Pins Used
26.1.7.7 Blocks and Sectors Search Summary
26.1.8 Peripheral Booting
26.1.8.1 Overview
26.1.8.2 Boot Image Location and Size
26.1.8.3 Peripheral Boot Procedure Overview
26.1.8.4 EMAC Boot Procedure
26.1.8.4.1 Device Initialization
26.1.8.4.2 BOOTP (RFC 951)
26.1.8.4.3 TFTP (RFC 1350)
26.1.8.4.4 Pins Used
26.1.8.4.5 SYSBOOT Pins
26.1.8.5 UART Boot Procedure
26.1.8.5.1 Device Initialization
26.1.8.5.2 Boot Image Download
26.1.8.5.3 Pins Used
26.1.8.6 USB Boot Procedure
26.1.8.6.1 Device Initialization
26.1.8.6.2 Image Download Procedure
26.1.8.6.3 Pins Used
26.1.8.7 ASIC ID structure
26.1.9 Image Format
26.1.9.1 Overview
26.1.9.2 Image Format for GP Device
26.1.10 Code Execution
26.1.10.1 Overview
26.1.10.2 Execution
26.1.11 Wakeup
26.1.11.1 Overview
26.1.11.2 Wakeup Booting by ROM Code
26.1.12 Tracing
A Revision History
AM335x ARM® Cortex™-A8 Microprocessors
(MPUs)
Technical Reference Manual
Literature Number: SPRUH73F
October 2011–Revised June 2012
Contents
2
3
6
4
5
Preface .................................................................................................................................... 153
Introduction .................................................................................................................... 154
1
AM335x Family ........................................................................................................... 154
1.1
1.1.1 Device Features ................................................................................................. 154
1.1.2 Device Identification ............................................................................................ 155
1.1.3 Feature Identification ........................................................................................... 156
Memory Map ................................................................................................................... 158
ARM Cortex-A8 Memory Map .......................................................................................... 158
2.1
ARM Cortex-M3 Memory Map ......................................................................................... 167
2.2
ARM MPU Subsystem ....................................................................................................... 169
ARM Cortex-A8 MPU Subsystem ...................................................................................... 170
3.1
3.1.1 Features .......................................................................................................... 171
3.1.2 MPU Subsystem Integration ................................................................................... 171
3.1.3 MPU Subsystem Clock and Reset Distribution ............................................................. 172
3.1.4 ARM Subchip .................................................................................................... 175
3.1.5 Interrupt Controller .............................................................................................. 176
3.1.6 Power Management ............................................................................................ 176
3.1.7 ARM Programming Model ..................................................................................... 179
Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) ............. 181
Introduction ............................................................................................................... 182
4.1
Graphics Accelerator (SGX) .............................................................................................. 183
Introduction ............................................................................................................... 184
5.1
5.1.1 POWERVR SGX Main Features .............................................................................. 184
5.1.2 SGX 3D Features ............................................................................................... 184
5.1.3 Universal Scalable Shader Engine (USSE) – Key Features .............................................. 185
5.1.4 Unsupported Features .......................................................................................... 186
Integration ................................................................................................................. 187
5.2.1 SGX530 Connectivity Attributes ............................................................................... 187
5.2.2 SGX530 Clock and Reset Management ..................................................................... 187
5.2.3 SGX530 Pin List ................................................................................................. 188
Functional Description ................................................................................................... 189
5.3.1 SGX Block Diagram ............................................................................................ 189
5.3.2 SGX Elements Description .................................................................................... 189
Interrupts ........................................................................................................................ 191
Functional Description ................................................................................................... 192
6.1
6.1.1 Interrupt Processing ............................................................................................ 193
6.1.2 Register Protection ............................................................................................. 194
6.1.3 Module Power Saving .......................................................................................... 194
6.1.4 Error Han˜dling .................................................................................................. 194
6.1.5 Interrupt Handling ............................................................................................... 194
Basic Programming Model .............................................................................................. 195
6.2.1 Initialization Sequence ......................................................................................... 195
6.2.2 INTC Processing Sequence ................................................................................... 195
6.2.3 INTC Preemptive Processing Sequence ..................................................................... 199
5.2
5.3
6.2
2
Contents
Copyright © 2011–2012, Texas Instruments Incorporated
SPRUH73F– October 2011– Revised June 2012
Submit Documentation Feedback
www.ti.com
7
8
9
7.2
7.3
7.4
6.3
6.4
6.5
6.6
6.2.4 Interrupt Preemption ............................................................................................ 203
6.2.5 ARM A8 INTC Spurious Interrupt Handling ................................................................. 203
ARM Cortex-A8 Interrupts .............................................................................................. 204
ARM Cortex-M3 Interrupts .............................................................................................. 208
PWM Events .............................................................................................................. 210
Interrupt Controller Registers ........................................................................................... 211
6.6.1 INTC Registers .................................................................................................. 211
Memory Subsystem ......................................................................................................... 386
GPMC ..................................................................................................................... 387
7.1
7.1.1 Introduction ...................................................................................................... 387
7.1.2 Integration ........................................................................................................ 390
7.1.3 Functional Description .......................................................................................... 392
7.1.4 Use Cases ....................................................................................................... 491
7.1.5 Registers ......................................................................................................... 502
OCMC-RAM .............................................................................................................. 535
7.2.1 Introduction ...................................................................................................... 535
7.2.2 Integration ........................................................................................................ 536
EMIF ....................................................................................................................... 537
7.3.1 Introduction ...................................................................................................... 537
7.3.2 Integration ........................................................................................................ 539
7.3.3 Functional Description .......................................................................................... 541
7.3.4 Use Cases ....................................................................................................... 559
7.3.5 EMIF4D Registers .............................................................................................. 559
7.3.6 DDR2/3/mDDR PHY Registers ............................................................................... 600
ELM ........................................................................................................................ 609
7.4.1 Introduction ...................................................................................................... 609
7.4.2 Integration ........................................................................................................ 610
7.4.3 Functional Description .......................................................................................... 611
7.4.4 Basic Programming Model ..................................................................................... 614
7.4.5 ELM Registers ................................................................................................... 620
Power, Reset, and Clock Management (PRCM) .................................................................... 632
Power, Reset, and Clock Management ............................................................................... 633
8.1
8.1.1 Introduction ...................................................................................................... 633
8.1.2 Device Power-Management Architecture Building Blocks ................................................. 633
8.1.3 Clock Management ............................................................................................. 633
8.1.4 Power Management ............................................................................................ 639
8.1.5 PRCM Module Overview ....................................................................................... 647
8.1.6 Clock Generation and Management .......................................................................... 648
8.1.7 Reset Management ............................................................................................. 664
8.1.8 Power-Up/Down Sequence .................................................................................... 673
8.1.9 IO State ........................................................................................................... 673
8.1.10 Voltage and Power Domains ................................................................................. 673
8.1.11 Device Modules and Power Management Attributes List ................................................. 674
8.1.12 Clock Module Registers ....................................................................................... 677
8.1.13 Power Management Registers ............................................................................... 834
Control Module ................................................................................................................ 875
Introduction ............................................................................................................... 876
9.1
Functional Description ................................................................................................... 876
9.2
9.2.1 Control Module Initialization ................................................................................... 876
9.2.2 Pad Control Registers .......................................................................................... 876
9.2.3 EDMA Event Multiplexing ...................................................................................... 877
9.2.4 Device Control and Status ..................................................................................... 878
9.2.5 DDR PHY ........................................................................................................ 885
SPRUH73F– October 2011– Revised June 2012
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Copyright © 2011–2012, Texas Instruments Incorporated
Contents
3
9.3
www.ti.com
CONTROL_MODULE Registers ....................................................................................... 886
9.3.1 control_revision Register (offset = 0h) [reset = 0h] ......................................................... 892
9.3.2 device_id Register (offset = 600h) [reset = 0x] ............................................................. 893
9.3.3 control_hwinfo Register (offset = 4h) [reset = 0h] .......................................................... 894
9.3.4 control_sysconfig Register (offset = 10h) [reset = 0h] ..................................................... 895
9.3.5 control_status Register (offset = 40h) [reset = 0h] ......................................................... 896
9.3.6 cortex_vbbldo_ctrl Register (offset = 41Ch) [reset = 0h] .................................................. 897
9.3.7 core_sldo_ctrl Register (offset = 428h) [reset = 0h] ........................................................ 898
9.3.8 mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h] ....................................................... 899
9.3.9 clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h] ................................................... 900
9.3.10 bandgap_ctrl Register (offset = 448h) [reset = 0h] ........................................................ 901
9.3.11 bandgap_trim Register (offset = 44Ch) [reset = 0h] ....................................................... 902
9.3.12 pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h] .................................................. 903
9.3.13 mosc_ctrl Register (offset = 468h) [reset = 0h] ............................................................ 904
9.3.14 rcosc_ctrl Register (offset = 46Ch) [reset = 0h] ............................................................ 905
9.3.15 deepsleep_ctrl Register (offset = 470h) [reset = 0h] ...................................................... 906
9.3.16 dev_feature Register (offset = 604h) [reset = 0h] ......................................................... 907
9.3.17 init_priority_0 Register (offset = 608h) [reset = 0h] ........................................................ 908
9.3.18 init_priority_1 Register (offset = 60Ch) [reset = 0h] ....................................................... 909
9.3.19 mmu_cfg Register (offset = 610h) [reset = 0h] ............................................................. 910
9.3.20 tptc_cfg Register (offset = 614h) [reset = 0h] .............................................................. 911
9.3.21 usb_ctrl0 Register (offset = 620h) [reset = 0h] ............................................................. 912
9.3.22 usb_sts0 Register (offset = 624h) [reset = 0h] ............................................................. 914
9.3.23 usb_ctrl1 Register (offset = 628h) [reset = 0h] ............................................................. 915
9.3.24 usb_sts1 Register (offset = 62Ch) [reset = 0h] ............................................................ 917
9.3.25 mac_id0_lo Register (offset = 630h) [reset = 0h] .......................................................... 918
9.3.26 mac_id0_hi Register (offset = 634h) [reset = 0h] .......................................................... 919
9.3.27 mac_id1_lo Register (offset = 638h) [reset = 0h] .......................................................... 920
9.3.28 mac_id1_hi Register (offset = 63Ch) [reset = 0h] ......................................................... 921
9.3.29 dcan_raminit Register (offset = 644h) [reset = 0h] ........................................................ 922
9.3.30 usb_wkup_ctrl Register (offset = 648h) [reset = 0h] ...................................................... 923
9.3.31 gmii_sel Register (offset = 650h) [reset = 0h] .............................................................. 924
9.3.32 pwmss_ctrl Register (offset = 664h) [reset = 0h] .......................................................... 925
9.3.33 mreqprio_0 Register (offset = 670h) [reset = 0h] .......................................................... 926
9.3.34 mreqprio_1 Register (offset = 674h) [reset = 0h] .......................................................... 927
9.3.35 hw_event_sel_grp1 Register (offset = 690h) [reset = 0h] ................................................ 928
9.3.36 hw_event_sel_grp2 Register (offset = 694h) [reset = 0h] ................................................ 929
9.3.37 hw_event_sel_grp3 Register (offset = 698h) [reset = 0h] ................................................ 930
9.3.38 hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h] ................................................ 931
9.3.39 smrt_ctrl Register (offset = 6A0h) [reset = 0h] ............................................................. 932
9.3.40 mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h] ............................................ 933
9.3.41 mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h] ............................................... 934
9.3.42 vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h] ................................................. 935
9.3.43 vdd_mpu_opp_100 Register (offset = 774h) [reset = 0h] ................................................. 936
9.3.44 vdd_mpu_opp_120 Register (offset = 778h) [reset = 0h] ................................................. 937
9.3.45 vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h] .............................................. 938
9.3.46 vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h] ................................................ 939
9.3.47 vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h] ................................................ 940
9.3.48 bb_scale Register (offset = 7D0h) [reset = 0h] ............................................................ 941
9.3.49 usb_vid_pid Register (offset = 7F4h) [reset = 4516141h] ................................................ 942
9.3.50 conf__ Register (offset = 800h) ........................................................... 943
9.3.51 cqdetect_status Register (offset = E00h) [reset = 0h] .................................................... 944
9.3.52 ddr_io_ctrl Register (offset = E04h) [reset = 0h] ........................................................... 945
4
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9.3.53 vtp_ctrl Register (offset = E0Ch) [reset = 0h] .............................................................. 946
9.3.54 vref_ctrl Register (offset = E14h) [reset = 0h] .............................................................. 947
9.3.55 tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h] ................................................. 948
9.3.56 tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h] ................................................. 949
9.3.57 tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h] ............................................... 950
9.3.58 tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] ............................................. 951
9.3.59 tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h] .............................................. 952
9.3.60 tpcc_evt_mux_20_23 Register (offset = FA4h) [reset = 0h] .............................................. 953
9.3.61 tpcc_evt_mux_24_27 Register (offset = FA8h) [reset = 0h] .............................................. 954
9.3.62 tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h] ............................................. 955
9.3.63 tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h] .............................................. 956
9.3.64 tpcc_evt_mux_36_39 Register (offset = FB4h) [reset = 0h] .............................................. 957
9.3.65 tpcc_evt_mux_40_43 Register (offset = FB8h) [reset = 0h] .............................................. 958
9.3.66 tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h] ............................................. 959
9.3.67 tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h] ............................................. 960
9.3.68 tpcc_evt_mux_52_55 Register (offset = FC4h) [reset = 0h] ............................................. 961
9.3.69 tpcc_evt_mux_56_59 Register (offset = FC8h) [reset = 0h] ............................................. 962
9.3.70 tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h] ............................................. 963
9.3.71 timer_evt_capt Register (offset = FD0h) [reset = 0h] ..................................................... 964
9.3.72 ecap_evt_capt Register (offset = FD4h) [reset = 0h] ..................................................... 965
9.3.73 adc_evt_capt Register (offset = FD8h) [reset = 0h] ....................................................... 966
9.3.74 reset_iso Register (offset = 1000h) [reset = 0h] ........................................................... 967
9.3.75 ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h] ....................................................... 968
9.3.76 sma2 Register (offset = 1320h) [reset = 0h] ................................................................ 969
9.3.77 m3_txev_eoi Register (offset = 1324h) [reset = 0h] ....................................................... 970
9.3.78 ipc_msg_reg0 Register (offset = 1328h) [reset = 0h] ..................................................... 971
9.3.79 ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h] ..................................................... 972
9.3.80 ipc_msg_reg2 Register (offset = 1330h) [reset = 0h] ..................................................... 973
9.3.81 ipc_msg_reg3 Register (offset = 1334h) [reset = 0h] ..................................................... 974
9.3.82 ipc_msg_reg4 Register (offset = 1338h) [reset = 0h] ..................................................... 975
9.3.83 ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h] ..................................................... 976
9.3.84 ipc_msg_reg6 Register (offset = 1340h) [reset = 0h] ..................................................... 977
9.3.85 ipc_msg_reg7 Register (offset = 1344h) [reset = 0h] ..................................................... 978
9.3.86 ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h] ................................................... 979
9.3.87 ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h] ................................................... 981
9.3.88 ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h] .................................................. 983
9.3.89 ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ................................................... 985
9.3.90 ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ................................................... 987
Interconnects .................................................................................................................. 989
Introduction ............................................................................................................... 990
10.1
10.1.1 Terminology ..................................................................................................... 990
10.1.2 L3 Interconnect ................................................................................................. 990
10.1.3 L4 Interconnect ................................................................................................. 993
Enhanced Direct Memory Access (EDMA) ........................................................................... 995
Introduction ............................................................................................................... 996
11.1
11.1.1 EDMA3 Controller Block Diagram ........................................................................... 996
11.1.2 Third-Party Channel Controller (TPCC) Overview ......................................................... 996
11.1.3 Third-Party Transfer Controller (TPTC) Overview ......................................................... 997
Integration ................................................................................................................. 999
11.2.1 Third-Party Channel Controller (TPCC) Integration ....................................................... 999
11.2.2 Third-Party Transfer Controller (TPTC) Integration ...................................................... 1000
Functional Description ................................................................................................. 1002
11.3.1 Functional Overview ......................................................................................... 1002
11.2
11.3
10
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5
11.5
11.4
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11.3.2 Types of EDMA3 Transfers ................................................................................. 1005
11.3.3 Parameter RAM (PaRAM) ................................................................................... 1007
11.3.4 Initiating a DMA Transfer .................................................................................... 1019
11.3.5 Completion of a DMA Transfer ............................................................................. 1022
11.3.6 Event, Channel, and PaRAM Mapping .................................................................... 1023
11.3.7 EDMA3 Channel Controller Regions ....................................................................... 1025
11.3.8 Chaining EDMA3 Channels ................................................................................. 1027
11.3.9 EDMA3 Interrupts ............................................................................................ 1028
11.3.10 Memory Protection .......................................................................................... 1034
11.3.11 Event Queue(s) ............................................................................................. 1038
11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................ 1040
11.3.13 Event Dataflow .............................................................................................. 1043
11.3.14 EDMA3 Prioritization ....................................................................................... 1043
11.3.15 EDMA3 Operating Frequency (Clock Control) .......................................................... 1044
11.3.16 Reset Considerations ....................................................................................... 1044
11.3.17 Power Management ........................................................................................ 1044
11.3.18 Emulation Considerations .................................................................................. 1044
11.3.19 EDMA Transfer Examples ................................................................................. 1046
11.3.20 EDMA Events ................................................................................................ 1062
EDMA3 Registers ...................................................................................................... 1065
11.4.1 EDMA3 Channel Controller Registers ..................................................................... 1065
11.4.2 EDMA3 Transfer Controller Registers ..................................................................... 1119
Appendix A .............................................................................................................. 1143
11.5.1 Debug Checklist .............................................................................................. 1143
11.5.2 Miscellaneous Programming/Debug Tips ................................................................. 1144
11.5.3 Setting Up a Transfer ........................................................................................ 1145
Touchscreen Controller .................................................................................................. 1147
Introduction .............................................................................................................. 1148
12.1
12.1.1 TSC_ADC Features .......................................................................................... 1148
12.1.2 Unsupported TSC_ADC_SS Features .................................................................... 1148
Integration ............................................................................................................... 1149
12.2.1 TSC_ADC Connectivity Attributes .......................................................................... 1149
12.2.2 TSC_ADC Clock and Reset Management ................................................................ 1150
12.2.3 TSC_ADC Pin List ............................................................................................ 1150
Functional Description ................................................................................................. 1151
12.3.1 HW Synchronized or SW Channels ........................................................................ 1151
12.3.2 Open Delay and Sample Delay ............................................................................. 1151
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................ 1151
12.3.4 One-Shot (Single) or Continuous Mode ................................................................... 1151
12.3.5 Interrupts ...................................................................................................... 1151
12.3.6 DMA Requests ................................................................................................ 1151
12.3.7 Analog Front End (AFE) Functional Block Diagram ..................................................... 1152
12.4 Operational Modes ..................................................................................................... 1153
12.4.1 PenCtrl and PenIRQ ......................................................................................... 1154
Touchscreen Controller Registers .................................................................................... 1157
12.5.1 TSC_ADC_SS Registers .................................................................................... 1157
LCD Controller ............................................................................................................... 1221
Introduction .............................................................................................................. 1222
13.1
13.1.1 Purpose of the Peripheral ................................................................................... 1222
13.1.2 Features ....................................................................................................... 1223
Integration ............................................................................................................... 1224
13.2.1 LCD Controller Connectivity Attributes .................................................................... 1224
13.2.2 LCD Controller Clock and Reset Management ........................................................... 1225
12.2
12.3
12.5
13.2
12
13
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13.4
13.5
13.3
13.2.3 LCD Controller Pin List ...................................................................................... 1225
Functional Description ................................................................................................. 1226
13.3.1 Clocking ........................................................................................................ 1226
13.3.2 LCD External I/O Signals .................................................................................... 1228
13.3.3 DMA Engine ................................................................................................... 1229
13.3.4 LIDD Controller ............................................................................................... 1230
13.3.5 Raster Controller ............................................................................................. 1232
13.3.6 Interrupt Conditions .......................................................................................... 1243
13.3.7 DMA ............................................................................................................ 1245
13.3.8 Power Management .......................................................................................... 1245
Programming Model .................................................................................................... 1246
13.4.1 LCD Character Displays ..................................................................................... 1246
13.4.2 Active Matrix Displays ....................................................................................... 1249
13.4.3 System Interaction ........................................................................................... 1249
13.4.4 Palette Lookup ................................................................................................ 1249
13.4.5 Test Logic ..................................................................................................... 1251
13.4.6 Disable and Software Reset Sequence ................................................................... 1251
13.4.7 Precedence Order for Determining Frame Buffer Type ................................................. 1252
LCD Registers .......................................................................................................... 1252
13.5.1 PID Register (offset = 0h) [reset = 0h] ..................................................................... 1254
13.5.2 CTRL Register (offset = 4h) [reset = 0h] .................................................................. 1255
13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h] .......................................................... 1256
13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h] .................................................. 1257
13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h] .................................................. 1258
13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h] .................................................. 1259
13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h] ................................................. 1260
13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h] .................................................. 1261
13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h] .................................................. 1262
13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h] ................................................... 1263
13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h] ............................................. 1266
13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h] ............................................. 1267
13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h] ............................................. 1268
13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h] ........................................... 1270
13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h] ......................................... 1271
13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h] .................................................. 1272
13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h] ............................................ 1274
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h] ........................................ 1275
13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h] ........................................... 1276
13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] ........................................ 1277
13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] ...................................................... 1278
13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h] ............................................... 1280
13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h] ...................................................... 1282
13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h] ................................................ 1284
13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h] ............................................ 1286
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h] .................................................. 1288
13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h] .................................................... 1289
Ethernet Subsystem ....................................................................................................... 1290
Introduction .............................................................................................................. 1291
14.1
14.1.1 Features ....................................................................................................... 1291
14.1.2 Unsupported Features ....................................................................................... 1292
Integration ............................................................................................................... 1293
14.2.1 Ethernet Switch Connectivity Attributes ................................................................... 1293
14.2.2 Ethernet Switch Clock and Reset Management .......................................................... 1295
14.2
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14.5
14.4
14.3
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14.2.3 Ethernet Switch Pin List ..................................................................................... 1296
14.2.4 Ethernet Switch RMII Clocking Details .................................................................... 1296
14.2.5 GMII Interface Signal Connections and Descriptions .................................................... 1297
14.2.6 RMII Signal Connections and Descriptions ............................................................... 1300
14.2.7 RGMII Signal Connections and Descriptions ............................................................. 1301
Functional Description ................................................................................................. 1303
14.3.1 CPSW_3G Subsystem ....................................................................................... 1303
14.3.2 CPSW_3G ..................................................................................................... 1308
14.3.3 Ethernet Mac Sliver (CPGMAC_SL) ....................................................................... 1350
14.3.4 Command IDLE ............................................................................................... 1352
14.3.5 RMII Interface ................................................................................................. 1353
14.3.6 RGMII Interface ............................................................................................... 1353
14.3.7 Common Platform Time Sync (CPTS) ..................................................................... 1356
14.3.8 MDIO ........................................................................................................... 1361
Software Operation ..................................................................................................... 1363
14.4.1 Transmit Operation ........................................................................................... 1363
14.4.2 Receive Operation ........................................................................................... 1365
14.4.3 Initializing the MDIO Module ................................................................................ 1366
14.4.4 Writing Data to a PHY Register ............................................................................ 1366
14.4.5 Reading Data from a PHY Register ........................................................................ 1367
14.4.6 Initialization and Configuration of CPSW .................................................................. 1367
Ethernet Subsystem Registers ....................................................................................... 1368
14.5.1 CPSW_ALE Registers ....................................................................................... 1368
14.5.2 CPSW_CPDMA Registers .................................................................................. 1383
14.5.3 CPSW_CPTS Registers ..................................................................................... 1436
14.5.4 CPSW_STATS Registers ................................................................................... 1449
14.5.5 CPDMA_STATERAM Registers ............................................................................ 1449
14.5.6 CPSW_PORT Registers ..................................................................................... 1483
14.5.7 CPSW_SL Registers ......................................................................................... 1539
14.5.8 CPSW_SS Registers ........................................................................................ 1553
14.5.9 CPSW_WR Registers ........................................................................................ 1566
14.5.10 Management Data Input/Output (MDIO) Registers ..................................................... 1602
Pulse-Width Modulation Subsystem (PWMSS) ................................................................... 1613
Pulse-Width Modulation Subsystem (PWMSS) .................................................................... 1614
15.1
15.1.1 Introduction .................................................................................................... 1614
15.1.2 Integration ..................................................................................................... 1616
15.1.3 PWMSS Registers ........................................................................................... 1617
Enhanced PWM (ePWM) Module .................................................................................... 1623
15.2.1 Introduction .................................................................................................... 1623
15.2.2 Functional Description ....................................................................................... 1627
15.2.3 Use Cases ..................................................................................................... 1686
15.2.4 Registers ...................................................................................................... 1710
Enhanced Capture (eCAP) Module .................................................................................. 1736
15.3.1 Introduction .................................................................................................... 1736
15.3.2 Functional Description ....................................................................................... 1737
15.3.3 Use Cases ..................................................................................................... 1747
15.3.4 Registers ...................................................................................................... 1763
Enhanced Quadrature Encoder Pulse (eQEP) Module ........................................................... 1775
15.4.1 Introduction .................................................................................................... 1775
15.4.2 Functional Description ....................................................................................... 1778
15.4.3 eQEP Registers .............................................................................................. 1796
Universal Serial Bus (USB) .............................................................................................. 1814
Introduction .............................................................................................................. 1815
16.1
15.2
15.3
15.4
15
16
8
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