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AMD主板PCB设计规范.pdf
Contents
List of Figures
List of Tables
Chapter 1 System Overview
Table 1. Feature Compatibility
Figure 1. Block Diagram Example—AM2r2 Processor-Based System
1.1 Pinout Assignment
1.2 Pin List
1.3 Package Information
1.4 Impedance
1.5 Crosstalk
1.6 Plane Splits
Figure 2. Trace Crossing Plane Split with Stitching Capacitors as High-Frequency Return Path
Chapter 2 Schematic and Layout Guidelines for Input Clock
2.1 Input Clock Termination and Layout Recommendation
2.1.1 Termination
Figure 3. Motherboard Clock Termination
Table 2. Clock Termination Values
2.1.2 Layout Requirements
Figure 4. CLKIN Board Stackup
Table 3. CLKIN Board Routing Parameters
Chapter 3 Schematic and Layout Guidelines for HyperTransport™ Link
3.1 HyperTransport™ 1 Link Technology
3.2 HyperTransport™ 3 Technology Design Guidelines
3.2.1 HyperTransport™ Technology Overview
Figure 5. HyperTransport™ Technology Block Diagram
Figure 6. HyperTransport™ Technology Differential Pair
3.2.2 HyperTransport™ Technology Routing Guidelines
Table 4. Examples of Board Routing Parameters for 93-W Target Impedance (Measurements are in Mils)
Figure 7. HyperTransport™ 3 Routing Parameters
Table 5. Differential Pair Matching Rules
Table 6. Length-Matching Rules Within Each Clock Group
Table 7. CAD-to-CAD Length-Matching Rules Across Two Different Clock Groups
Figure 8. VSS Referenced Layout
3.3 HyperTransport™ Technology and Processor Breakout
Figure 9. Topside HyperTransport™ Breakout for the AM2r2 Processor
Figure 10. Bottomside HyperTransport™ Breakout for the AM2r2 Processor
Chapter 4 Design Guidelines for Four Unbuffered DDR2 DIMMs
4.1 DDR2 SDRAM
4.1.1 Signal Names and Descriptions
Table 8. DDR2 Signal Descriptions
Table 9. Clock Connections
4.1.2 Layer Assignments
Figure 11. Board Stackup Overview
Figure 12. Board Stackup Parameters for a Four-Layer Board
Table 10. Parameters for Stackup on a Four-Layer Board
4.2 Overview of DDR2 SDRAM Interface
4.2.1 Interface Overview and Block Diagram
Figure 13. Unbuffered 4-DIMM Block Diagram
4.2.2 Valid DIMM Configurations – Four Unbuffered DIMMs
4.2.3 Frequency
4.3 DIMM Configuration and Population
4.4 Unbuffered Four-DIMM DDR2 Layout Guidelines
Figure 14. Unbuffered 4-DIMM General Layout Picture
Figure 15. Undesirable Net Routing
Figure 16. Lead-In Length for Memory Routing
4.4.1 Address/Command and Control Layout Guidelines
Table 11. Termination Values for Unbuffered DIMM Address/Command Signals
Figure 17. Channel A Command and Address Routing
Figure 18. Channel B Command and Address Routing
Figure 19. CKE Routing and Termination
Figure 20. CS and ODT Routing and Termination
Table 12. Parameters for Address/Command and Control Trace Width and Space
4.4.2 Data Group Guidelines
Table 13. DDR2 Data Groups
Figure 21. Data Group Routing and Termination
Figure 22. Routing for DQS Pair
Table 14. Parameters for DQS Trace Width and Space
Table 15. Parameters for Data and Check Trace Width and Space
4.4.3 Clock Layout Guidelines
Figure 23. Clock Termination and Routing
Table 16. CLK_H and CLK_L Termination
Table 17. Parameters for CLK Trace Width and Space
4.5 Basic Goal for Unbuffered DDR2 Memory Routing
4.5.1 Routing Procedure
4.5.2 Routing Rules
4.5.3 Unbuffered 4-DIMM DDR2 Routing Example
Figure 24. General DDR2 Component Placement and Routing for the AM2r2 Processor
Figure 25. Example of Three Nets Routing Between the Two Processor Pads
Figure 26. Example of an AM2r2 Processor Breakout—Topside
Figure 27. Example of an AM2r2 Processor Breakout—Bottomside
Figure 28. AM2r2 Processor Four DIMM Routing Example—Topside
Figure 29. AM2r2 Processor Four DIMM Routing Example—Bottomside
4.5.4 Unbuffered 4-DIMM DDR2 Routing Examples on a BTX Board
Figure 30. General DDR2 Component Placement and Routing for a BTX Form Factor
Figure 31. Example of an AM2r2 Processor Breakout on a BTX Board—Topside
Figure 32. Example of an AM2r2 Processor Breakout on a BTX Board—Bottomside
Figure 33. AM2r2 Processor Four DIMM Routing Example on a BTX Board—Topside
Figure 34. AM2r2 Processor Four DIMM Routing Example on a BTX Board— Bottomside
Chapter 5 Design Guidelines for Miscellaneous Signals
Table 18. Miscellaneous Signals Quick Reference
5.1 HyperTransport™ I/O Compensation
Table 19. Compensation Resistor Routing Rules for HyperTransport™ Technology
5.1.1 Memory I/O Compensation
Table 20. Compensation Resistor Routing Rules for M_ZP and M_ZN
5.2 Hardware Debug Tool
5.2.1 Single-Processor HDT
Figure 35. HDT Header
Table 21. HDT Header Pin-Out
5.2.2 TMS
5.2.3 TCK
5.2.4 TRST_L
5.2.5 TDI
5.2.6 TDO
5.2.7 DBREQ_L
5.2.8 DBRDY
5.2.9 RESET_L
5.3 Voltage Regulator Signals
5.3.1 SVC, SVD, and PVIEN
5.3.2 VDD_FB_H and VDD_FB_L
5.3.3 VDDNB_FB_H and VDDNB_FB_L
5.3.4 VDDIO_FB_H AND VDDIO_FB_L
5.3.5 VTT_SENSE
5.3.6 CPU_PRESENT_L and CORE_TYPE
Figure 36. Example of CORE_TYPE and CPU_PRESENT Schematic
5.4 Global Signals
5.4.1 PWROK
5.4.2 RESET_L
5.4.3 LDTSTOP_L
5.5 Thermal-Related Miscellaneous Signals
5.5.1 THERMTRIP_L
Figure 37. Thermtrip Circuit
5.5.2 PROCHOT_L
Figure 38. Example PROCHOT_L Schematic
5.5.3 SIC, SID, ALERT_L, and SA[0]
5.5.4 THERMDA and THERMDC
5.6 No Connects
Chapter 6 Processor Power Requirements
6.1 High-Frequency Motherboard Decoupling
Figure 39. High-Frequency Decoupling Routing Comparison
6.2 Power Generation and Distribution Guidelines
Figure 40. General View of the Processor Power Plane Cuts
6.2.1 Single and Dual Power Planes
6.2.2 AM2r2 Processor Power and Ground Overview
6.2.3 VDD Power Requirements
Figure 41. Example of VDD Power Fill on the Top Layer
Table 22. VDD Decoupling Recommendations
Figure 42. VDD Decoupling Placement With Backplate Windows—Bottom Signal Layer
6.2.4 VDDNB Power Requirements
Figure 43. Example of VDDNB Power Delivery
Table 23. VDDNB Decoupling Recommendations
6.2.5 VDDIO, VTT, and M_VREF Routing and Decoupling
Figure 44. VDDIO Decoupling Placement Between Processor and DIMMs
Table 24. VDDIO Decoupling Recommendations
Table 25. VTT Decoupling Recommendations
Figure 45. VTT Delivery on Single Side
Figure 46. VTT Decoupling Placement Between Processor and DIMMs
Table 26. M_VREF-to-Processor Decoupling Recommendations
Figure 47. M_VREF Decoupling Placement
6.2.6 VDDA Power Requirements
Figure 48. VDDA Filtering Circuit
Table 27. VDDA Filter Recommendations
6.2.7 VLDT Power Requirements
Table 28. VLDT Decoupling Recommendations
Chapter 7 EMI Design Guidelines
7.1 Decoupling, Bypass, Stitching, and Filtering Capacitors
7.1.1 Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI)
7.1.2 High-Frequency Bypass and Stitching Capacitors
7.1.3 DDR VDDIO to VSS Stitching Capacitor Requirements
7.1.4 Voltage Filtering Requirements
7.2 Clocks and EMI
7.2.1 Spread Spectrum Clocking
7.2.2 Unused Clock Outputs
7.2.3 Clock Generator Modules
Figure 49. Clock Generator Placed on the Side Nearest a Solid VSS Plane
Figure 50. Clock Traces Referencing a Continuous VSS Plane (Solid Plane)
Figure 51. Clock Traces Referencing Discontinuous Power Planes (Split Plane)
Figure 52. Top Layer VSS Copper Fill Beneath Clock Generator
7.2.4 Clock Circuit Placement and Wiring
7.2.5 Clock Signal Termination
7.3 I/O Signal Partitioning and Separation
7.3.1 I/O Filtering
7.3.2 Processor Heatsink Grounding
7.4 Motherboard Grounding
7.4.1 Motherboard-to-Chassis Grounding
Figure 53. PCB Mounting Hole
Chapter 8 Thermal and Mechanical Motherboard Requirements
8.1 AM2r2 ATX Processor Component Keepout and Height Restrictions
8.2 AM2r2 BTX Processor Component Keepout and Height Restrictions
AMD Confidential—Advance Information
AM2r2 Processor
Motherboard Design Guide
Publication #
Issue Date:
41645
June 2010
Revision:
1.02
AMD Confidential—Advance Information
© 2006—2010 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro Devices,
Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the
accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. The
information contained herein may be of a preliminary or advance nature and is subject to
change without notice. No license, whether express, implied, arising by estoppel or
otherwise, to any intellectual property rights is granted by this publication. Except as set
forth in AMD’s Standard Terms and Conditions of Sale, AMD assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to its products
including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as compo-
nents in systems intended for surgical implant into the body, or in other applications
intended to support or sustain life, or in any other application in which the failure of
AMD’s product could create a situation where personal injury, death, or severe property or
environmental damage may occur. AMD reserves the right to discontinue or make changes
to its products at any time without notice.
Trademarks
AMD, the AMD Arrow logo, and combinations thereof, are trademarks of Advanced Micro Devices, Inc.
HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.
PCI Express and PCI-X are registered trademarks of PCI-Special Interest Group (PCI-SIG).
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
41645 Rev. 1.02
June 2010
AM2r2 Processor Motherboard Design Guide
AMD Confidential—Advance Information
Contents
2.1.1
2.1.2
3.2.1
Chapter 3
3.1
3.2
Revision Historyw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Chapter 1
System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pinout Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.1
Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
1.2
1.3
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.4
1.5
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.6
Schematic and Layout Guidelines for Input Clock . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 2
2.1
Input Clock Termination and Layout Recommendation . . . . . . . . . . . . . . . . . . . . . .17
Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Layout Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Schematic and Layout Guidelines for HyperTransport™ Link . . . . . . . . . . . . .21
HyperTransport 1 Link Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
HyperTransport 3 Technology Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . .21
HyperTransport Technology Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
HyperTransport Link Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
HyperTransport Link Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
HyperTransport Technology Routing Guidelines . . . . . . . . . . . . . . . . . . . . . .24
General Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.2.2.1
HyperTransport Technology Motherboard Impedance . . . . . . . . . . . . . . . . . . . . . .25
3.2.2.2
Signal Trace Width and Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.2.2.3
HyperTransport Technology Signal Length Matching . . . . . . . . . . . . . . . . . . . . . .26
3.2.2.4
Trace Length Mismatch Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.2.2.5
HyperTransport Trace Referencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
3.2.2.6
HyperTransport Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.2.2.7
HyperTransport Technology and Processor Breakout . . . . . . . . . . . . . . . . . . . . . . . .28
Design Guidelines for Four Unbuffered DDR2 DIMMs . . . . . . . . . . . . . . . . . . . .31
DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
Chapter 4
4.1
3.2.1.1
3.2.1.2
3.2.1.3
3.2.1.4
3.2.2
Contents
3
AM2r2 Processor Motherboard Design Guide
41645 Rev. 1.02
June 2010
AMD Confidential—Advance Information
4.2
4.3
4.4
4.5
Chapter 5
5.1
5.2
4.1.1
4.1.2
4.2.1
4.2.2
4.2.3
4.4.1
4.4.2.1
4.4.2.2
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.4
4.4.1.5
Signal Names and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Layer Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Overview of DDR2 SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Interface Overview and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Valid DIMM Configurations – Four Unbuffered DIMMs . . . . . . . . . . . . . . .36
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
DIMM Configuration and Population . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Unbuffered Four-DIMM DDR2 Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .37
Address/Command and Control Layout Guidelines . . . . . . . . . . . . . . . . . . . .40
Address/Command Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Address/Command Group Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . .40
CKE Schematic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
CS and ODT Schematic Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Address/Command and Control Trace Width and Separation . . . . . . . . . . . . . . . . .43
Data Group Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Data Group Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Data Bus Trace Width and Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Clock Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Clock Group Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.4.3.1
Clock Group Trace Width and Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.4.3.2
Basic Goal for Unbuffered DDR2 Memory Routing . . . . . . . . . . . . . . . . . . . . . . . . .49
Routing Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Routing Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
CLK_H and CLK_L Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Data, DQS, Check Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
ADD, BANK, CS, CKE, RAS, CAS, WE, ODT Signals . . . . . . . . . . . . . . . . . . . .51
Unbuffered 4-DIMM DDR2 Routing Example . . . . . . . . . . . . . . . . . . . . . . .52
Unbuffered 4-DIMM DDR2 Routing Examples on a BTX Board . . . . . . . . .58
Design Guidelines for Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
HyperTransport I/O Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Memory I/O Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Hardware Debug Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Single-Processor HDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.5.2.1
4.5.2.2
4.5.2.3
4.4.2
4.4.3
4.5.1
4.5.2
4.5.3
4.5.4
5.1.1
5.2.1
5.2.2
4
Contents
41645 Rev. 1.02
June 2010
AM2r2 Processor Motherboard Design Guide
AMD Confidential—Advance Information
5.3
5.4
5.5
5.6
Chapter 6
6.1
6.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
5.2.9
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4.1
5.4.2
5.4.3
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
TRST_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
DBREQ_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
DBRDY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
RESET_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Voltage Regulator Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
SVC, SVD, and PVIEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
VDD_FB_H and VDD_FB_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
VDDNB_FB_H and VDDNB_FB_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
VDDIO_FB_H AND VDDIO_FB_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
VTT_SENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
CPU_PRESENT_L and CORE_TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PWROK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
RESET_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
LDTSTOP_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Thermal-Related Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
THERMTRIP_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
PROCHOT_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
SIC, SID, ALERT_L, and SA[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
THERMDA and THERMDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
No Connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Processor Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
High-Frequency Motherboard Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Power Generation and Distribution Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Single and Dual Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
AM2r2 Processor Power and Ground Overview . . . . . . . . . . . . . . . . . . . . . .80
VDD Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
VDDNB Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
VDDIO, VTT, and M_VREF Routing and Decoupling . . . . . . . . . . . . . . . . 85
VDDIO Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
6.2.5.1
5.5.1
5.5.2
5.5.3
5.5.4
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
Contents
5
AM2r2 Processor Motherboard Design Guide
41645 Rev. 1.02
June 2010
AMD Confidential—Advance Information
Chapter 7
7.1
6.2.5.2
6.2.5.3
6.2.6
6.2.7
7.1.1
7.1.2
7.1.3
7.1.4
VTT Power Delivery and Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
M_VREF Decoupling and Routing Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
VDDA Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
VLDT Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
EMI Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Decoupling, Bypass, Stitching, and Filtering Capacitors . . . . . . . . . . . . . . . . . . . . . .95
Voltage Plane Decoupling Capacitors (Critical for Minimizing EMI) . . . . . .95
High-Frequency Bypass and Stitching Capacitors . . . . . . . . . . . . . . . . . . . . .95
DDR VDDIO to VSS Stitching Capacitor Requirements . . . . . . . . . . . . . . .96
Voltage Filtering Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Clocks and EMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Unused Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Clock Generators Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Clock Circuit Placement and Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
Clock Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
I/O Signal Partitioning and Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
I/O Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Processor Heatsink Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
7.4 Motherboard Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Motherboard-to-Chassis Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Thermal and Mechanical Motherboard Requirements . . . . . . . . . . . . . . . . . . .105
AM2r2 ATX Processor Component Keepout and Height Restrictions . . . . . . . . . .105
AM2r2 BTX Processor Component Keepout and Height Restrictions . . . . . . . . . .112
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3.1
7.3.2
7.4.1
7.2
7.3
Chapter 8
8.1
8.2
6
Contents
41645 Rev. 1.02
June 2010
AM2r2 Processor Motherboard Design Guide
AMD Confidential—Advance Information
List of Figures
Figure 1.
Figure 2.
Block Diagram Example—AM2r2 Processor-Based System . . . . . . . . . . . . . . . . . . . .14
Trace Crossing Plane Split with Stitching Capacitors as
High-Frequency Return Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 3. Motherboard Clock Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 4.
CLKIN Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
HyperTransport™ Technology Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 5.
Figure 6.
HyperTransport Technology Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
HyperTransport 3 Routing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 7.
VSS Referenced Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Figure 8.
Figure 9.
Topside HyperTransport Breakout for the AM2r2 Processor . . . . . . . . . . . . . . . . . . . .28
Figure 10. Bottomside HyperTransport Breakout for the AM2r2 Processor. . . . . . . . . . . . . . . . . .29
Figure 11. Board Stackup Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Figure 12. Board Stackup Parameters for a Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Figure 13. Unbuffered 4-DIMM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Figure 14. Unbuffered 4-DIMM General Layout Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 15. Undesirable Net Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 16. Lead-In Length for Memory Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Figure 17. Channel A Command and Address Routing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 18. Channel B Command and Address Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Figure 19. CKE Routing and Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Figure 20. CS and ODT Routing and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 21. Data Group Routing and Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 22. Routing for DQS Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 23. Clock Termination and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Figure 24. General DDR2 Component Placement and Routing for the AM2r2 Processor . . . . . . .52
Figure 25. Example of Three Nets Routing Between the Two Processor Pads . . . . . . . . . . . . . . . .53
Figure 26. Example of an AM2r2 Processor Breakout—Topside . . . . . . . . . . . . . . . . . . . . . . . . . .54
Figure 27. Example of an AM2r2 Processor Breakout—Bottomside . . . . . . . . . . . . . . . . . . . . . . .55
Figure 28. AM2r2 Processor Four DIMM Routing Example—Topside . . . . . . . . . . . . . . . . . . . . .56
Figure 29. AM2r2 Processor Four DIMM Routing Example—Bottomside . . . . . . . . . . . . . . . . . .57
List of Figures
7
AM2r2 Processor Motherboard Design Guide
41645 Rev. 1.02
June 2010
AMD Confidential—Advance Information
Figure 30. General DDR2 Component Placement and Routing for a BTX Form Factor . . . . . . . .58
Figure 31. Example of an AM2r2 Processor Breakout on a BTX Board—Topside . . . . . . . . . . . .59
Figure 32. Example of an AM2r2 Processor Breakout on a BTX Board—Bottomside . . . . . . . . .60
Figure 33. AM2r2 Processor Four DIMM Routing Example on a BTX Board—Topside . . . . . . .61
Figure 34. AM2r2 Processor Four DIMM Routing Example on a BTX Board—Bottomside . . . .62
Figure 35. HDT Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Figure 36. Example of CORE_TYPE and CPU_PRESENT Schematic . . . . . . . . . . . . . . . . . . . . .72
Figure 37. Thermtrip Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Figure 38. Example PROCHOT_L Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Figure 39. High-Frequency Decoupling Routing Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 40. General View of the Processor Power Plane Cuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Figure 41. Example of VDD Power Fill on the Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Figure 42. VDD Decoupling Placement With Backplate Windows—Bottom Signal Layer . . . . .82
Figure 43. Example of VDDNB Power Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Figure 44. VDDIO Decoupling Placement Between Processor and DIMMs . . . . . . . . . . . . . . . . .85
Figure 45. VTT Delivery on Single Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Figure 46. VTT Decoupling Placement Between Processor and DIMMs . . . . . . . . . . . . . . . . . . .89
Figure 47. M_VREF Decoupling Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Figure 48. VDDA Filtering Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Figure 49. Clock Generator Placed on the Side Nearest a Solid VSS Plane . . . . . . . . . . . . . . . . . .97
Figure 50. Clock Traces Referencing a Continuous VSS Plane (Solid Plane) . . . . . . . . . . . . . . . .98
Figure 51. Clock Traces Referencing Discontinuous Power Planes (Split Plane). . . . . . . . . . . . . .99
Figure 52. Top Layer VSS Copper Fill Beneath Clock Generator . . . . . . . . . . . . . . . . . . . . . . . .100
PCB Mounting Hole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Figure 53.
8
List of Figures
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