Spartan6 原理图（全）.pdf

发布时间：2022-05-29 发布人：admin 分类：说明书资料大小：1.27M 资料格式：pdf 举报版权申诉

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sp605 Sheet 1

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4 DDR3 Page 9 Differential Clock Clock Socket SMA Clock Page 14 LEDs Page 14 DIP Switches Page 14 Push Buttons Page 14 SFP Module Page 12 D C B A Spartan-6 XC6SLX45T U1 System ACE CF Page 20 Parallel Flash Page 19 SSPI Header Page 18 SPI X4 or External Config Page 18 PCIe Finger Page 12 IIC EEPROM and Header Page 15 MODE DIP Switch USB UART USB JTAG Connector Page 18 Page 15 Page 32 JTAG Chain J19 3.3V 2.5V J4 R D H B S U FMC LPC System ACE CF FPGA BUFFER TDI TDO TSTTDI CFGTDO J2 U17 TSTTDO CFGTDI TDI TDO U1 IIC Addressing U4 J2 0b1010100 EEPROM: 0b1010010 Other Devices: 0bXXXXX10 4 3 2 3 2 1 FMC LPC Expansion Connector Page 10 10/100/1000 Ethernet GMII Page 11 Disclaimer: THE XILINX HARDWARE, FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS")ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED D ON THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. 12V PWR Jack Power Supply Linear Regulator 5.0V@1.5A max Power Controller 1 Switching Module VCCINT@10A max Switching Module 2.5V@10A max Switching Module VCCAUX@10A max Power Controller 2 Switching Module 1.5V@20A max Switching Module 3.3V@20A max Linear Regulator 3.0V@500mA max Linear Regulator 1.8V@500mA max Linear Regulator 1.2V @ 3A max Sink/Source DDR Regulator 0.75V VTT / VREF @ 3A max Title: SP605 Block Diagram SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 Date: Sheet Size: B Sheet 9-25-2009_10:32 of 1 35 1 Ver: Rev: D 04 Drawn By BF C B A

4 3 2 1 D C B A DUT BANK 0 6slx45tfg484 IO_L66N_SCP0_0_C18 IO_L66P_SCP1_0_D17 IO_L65N_SCP2_0_A20 IO_L65P_SCP3_0_B20 IO_L64N_SCP4_0_A19 IO_L64P_SCP5_0_C19 IO_L63N_SCP6_0_A18 IO_L63P_SCP7_0_B18 IO_L62N_VREF_0_D19 IO_L62P_0_D18 IO_L51N_0_F17 IO_L51P_0_G16 IO_L50N_0_A17 IO_L50P_0_C17 IO_L49N_0_G15 IO_L49P_0_H14 IO_L38N_VREF_0_G13 IO_L38P_0_H13 IO_L37N_GCLK12_0_F16 IO_L37P_GCLK13_0_E16 IO_L36N_GCLK14_0_F15 IO_L36P_GCLK15_0_F14 IO_L35N_GCLK16_0_G11 IO_L35P_GCLK17_0_H12 IO_L34N_GCLK18_0_F10 IO_L34P_GCLK19_0_G9 IO_L33N_0_H11 IO_L33P_0_H10 IO_L32N_0_F9 IO_L32P_0_G8 IO_L8N_VREF_0_A5 IO_L8P_0_C5 IO_L7N_0_F8 IO_L7P_0_F7 IO_L6N_0_A4 IO_L6P_0_C4 IO_L5N_0_A3 IO_L5P_0_B3 IO_L4N_0_E6 IO_L4P_0_E5 IO_L3N_0_A2 IO_L3P_0_B2 IO_L2N_0_D5 IO_L2P_0_D4 IO_L1N_VREF_0_D3 IO_L1P_HSWAPEN_0_C3 C18 D17 A20 B20 A19 C19 A18 B18 D19 D18 F17 G16 A17 C17 G15 H14 G13 H13 F16 E16 F15 F14 G11 H12 F10 G9 H11 H10 F9 G8 A5 C5 F8 F7 A4 C4 A3 B3 E6 E5 A2 B2 D5 D4 D3 C3 VCC2V5_FPGA G14 G10 F6 E17 B4 B19 VCCO_0_G14 VCCO_0_G10 VCCO_0_F6 VCCO_0_E17 VCCO_0_B4 VCCO_0_B19 U1 GPIO_SWITCH_0 GPIO_LED_0 FMC_LA08_N FMC_LA08_P FMC_LA04_N FMC_LA04_P FMC_LA03_N FMC_LA03_P FMC_LA15_N FMC_LA15_P FMC_LA13_N FMC_LA13_P FMC_LA14_N FMC_LA14_P FMC_LA11_N FMC_LA11_P FMC_LA12_N FMC_LA12_P FMC_CLK1_M2C_N FMC_CLK1_M2C_P FMC_LA01_CC_N FMC_LA01_CC_P FMC_CLK0_M2C_N FMC_CLK0_M2C_P FMC_LA00_CC_N FMC_LA00_CC_P FMC_LA10_N FMC_LA10_P FMC_LA02_N FMC_LA02_P FMC_LA16_N FMC_LA16_P FMC_LA09_N FMC_LA09_P FMC_LA05_N FMC_LA05_P USER_SMA_GPIO_N USER_SMA_GPIO_P IIC_SDA_SFP IIC_SCL_SFP FMC_LA07_N FMC_LA07_P FMC_LA06_N FMC_LA06_P PMBUS_ALERT FPGA_HSWAPEN 4 3 2 14 14 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 13 13 12 12 10 10 10 10 21,26 D C B 1 2 R125 100 5% 1/16W FPGA Bank 0 Title: FPGA Bank 0 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Date: Sheet Size: B Sheet 9-18-2009_15:04 of 2 35 1 Ver: Rev: D 04 Drawn By PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 A BF

4 3 2 1 DUT BANK 1 6slx45tfg484 D C B A VCC2V5_FPGA W21 U18 R21 N18 L21 L16 J18 G21 E19 C21 VCCO_1_W21 VCCO_1_U18 VCCO_1_R21 VCCO_1_N18 VCCO_1_L21 VCCO_1_L16 VCCO_1_J18 VCCO_1_G21 VCCO_1_E19 VCCO_1_C21 U1 IO_L74N_DOUT_BUSY_1_V20 IO_L74P_AWAKE_1_V19 IO_L73N_1_T18 IO_L73P_1_T19 IO_L72N_1_T17 IO_L72P_1_R17 IO_L71N_1_P18 IO_L71P_1_P17 IO_L70N_1_R16 IO_L70P_1_R15 IO_L61N_1_M18 IO_L61P_1_M17 IO_L60N_1_P16 IO_L60P_1_N16 IO_L59N_1_T20 IO_L59P_1_U19 IO_L58N_1_N15 IO_L58P_1_M16 IO_L53N_VREF_1_R19 IO_L53P_1_P19 IO_L52N_M1DQ15_1_Y22 IO_L52P_M1DQ14_1_Y21 IO_L51N_M1DQ13_1_W22 IO_L51P_M1DQ12_1_W20 IO_L50N_M1UDQSN_1_V22 IO_L50P_M1UDQS_1_V21 IO_L49N_M1DQ11_1_U22 IO_L49P_M1DQ10_1_U20 IO_L48N_M1DQ9_1_T22 IO_L48P_HDC_M1DQ8_1_T21 IO_L47N_LDC_M1DQ1_1_R22 IO_L47P_FWE_B_M1DQ0_1_R20 IO_L46N_FOE_B_M1DQ3_1_P22 IO_L46P_FCS_B_M1DQ2_1_P21 IO_L45N_A0_M1LDQSN_1_N22 IO_L45P_A1_M1LDQS_1_N20 IO_L44N_A2_M1DQ7_1_M22 IO_L44P_A3_M1DQ6_1_M21 IO_L43N_GCLK4_M1DQ5_1_L22 IO_L43P_GCLK5_M1DQ4_1_L20 IO_L42N_GCLK6_M1LDM_1_N19 IO_L42P_GCLK7_M1UDM_1_P20 IO_L41N_GCLK8_M1CASN_1_K22 IO_L41P_GCLK9_M1RASN_1_K21 IO_L40N_GCLK10_M1A6_1_M19 IO_L40P_GCLK11_M1A5_1_M20 IO_L39N_M1ODT_1_J22 IO_L39P_M1A3_1_J20 IO_L38N_A4_M1CLKN_1_L19 IO_L38P_A5_M1CLK_1_K20 IO_L37N_A6_M1A1_1_H22 IO_L37P_A7_M1A0_1_H21 IO_L36N_A8_M1BA1_1_L17 IO_L36P_A9_M1BA0_1_K17 IO_L35N_A10_M1A2_1_G22 IO_L35P_A11_M1A7_1_G20 IO_L34N_A12_M1BA2_1_K18 IO_L34P_A13_M1WE_1_K19 IO_L33N_A14_M1A4_1_H20 IO_L33P_A15_M1A10_1_J19 IO_L32N_A16_M1A9_1_E22 IO_L32P_A17_M1A8_1_E20 IO_L31N_A18_M1A12_1_F22 IO_L31P_A19_M1CKE_1_F21 IO_L30N_A20_M1A11_1_H19 IO_L30P_A21_M1RESET_1_H18 IO_L29N_A22_M1A14_1_F20 IO_L29P_A23_M1A13_1_G19 IO_L28N_VREF_1_D22 IO_L28P_1_D21 IO_L21N_1_K16 IO_L21P_1_L15 IO_L20N_1_C22 IO_L20P_1_C20 IO_L19N_1_J17 IO_L19P_1_J16 IO_L10N_1_B22 IO_L10P_1_B21 IO_L9N_1_H17 IO_L9P_1_H16 IO_L1N_A24_VREF_1_F19 IO_L1P_A25_1_F18 V20 V19 T18 T19 T17 R17 P18 P17 R16 R15 M18 M17 P16 N16 T20 U19 N15 M16 R19 P19 Y22 Y21 W22 W20 V22 V21 U22 U20 T22 T21 R22 R20 P22 P21 N22 N20 M22 M21 L22 L20 N19 P20 K22 K21 M19 M20 J22 J20 L19 K20 H22 H21 L17 K17 G22 G20 K18 K19 H20 J19 E22 E20 F22 F21 H19 H18 F20 G19 D22 D21 K16 L15 C22 C20 J17 J16 B22 B21 H17 H16 F19 F18 PHY_MDIO FPGA_AWAKE FLASH_WAIT FLASH_ADV_B SFP_LOS DVI_D11 DVI_D10 DVI_D9 DVI_D8 DVI_D7 DVI_D6 DVI_D5 DVI_D4 DVI_D3 DVI_D2 DVI_D1 PHY_CRS PHY_COL PHY_MDC PHY_RXD0 PHY_RXD1 PHY_RXD2 PHY_RXD3 PHY_RXD4 PHY_RXD5 PHY_RXD6 PHY_RXD7 PHY_RXER PHY_RXCTL_RXDV IIC_SCL_MAIN IIC_SDA_MAIN FLASH_WE_B FLASH_OE_B FLASH_CE_B FLASH_A0 FLASH_A1 FLASH_A2 FLASH_A3 NC PHY_TXCLK CLK_33MHZ_SYSACE PHY_RXCLK SYSCLK_N SYSCLK_P USER_SMA_CLOCK_N USER_SMA_CLOCK_P PHY_RESET PHY_INT FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 DVI_GPIO1 GPIO_LED_2 DVI_D0 DVI_RESET_B DVI_XCLK_N DVI_XCLK_P DVI_DE DVI_H DVI_V USB_1_RX USB_1_TX PMBUS_CTRL USB_1_RTS USB_1_CTS 11 18 19 19 12 17 17 17 17 17 17 17 17 17 17 17 11 11 11 11 11 11 11 11 11 11 11 11 11 10,15 10,15 19 19 19 19 19 19 19 11 20 11 14 14 13 13 11 11 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 17 14 17 17 17 17 17 17 17 15 15 21,26 15 15 4 3 2 D C B FPGA Bank 1 Title: FPGA Bank 1 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Date: Sheet Size: B Sheet 9-18-2009_15:04 of 3 35 1 Ver: Rev: D 04 Drawn By PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 A BF

4 3 2 1 DUT BANK 2 6slx45tfg484 D C B A VCC2V5_FPGA W5 V8 V16 V12 T9 T13 AB3 AA7 AA19 AA15 AA11 VCCO_2_W5 VCCO_2_V8 VCCO_2_V16 VCCO_2_V12 VCCO_2_T9 VCCO_2_T13 VCCO_2_AB3 VCCO_2_AA7 VCCO_2_AA19 VCCO_2_AA15 VCCO_2_AA11 U1 IO_L65N_CSO_B_2_AA3 IO_L65P_INIT_B_2_Y4 IO_L64N_D9_2_U6 IO_L64P_D8_2_T7 IO_L63N_2_AB4 IO_L63P_2_AA4 IO_L62N_D6_2_AB5 IO_L62P_D5_2_Y5 IO_L60N_2_Y6 IO_L60P_2_W6 IO_L59N_2_R8 IO_L59P_2_R9 IO_L58N_2_W8 IO_L58P_2_V7 IO_L57N_2_U8 IO_L57P_2_T8 IO_L50N_2_V9 IO_L50P_2_U9 IO_L49N_D4_2_AB6 IO_L49P_D3_2_AA6 IO_L48N_RDWR_B_VREF_2_Y8 IO_L48P_D7_2_W9 IO_L47N_2_AB7 IO_L47P_2_Y7 IO_L46N_2_U10 IO_L46P_2_T10 IO_L45N_2_AB8 IO_L45P_2_AA8 IO_L44N_2_Y10 IO_L44P_2_W10 IO_L43N_2_AB9 IO_L43P_2_Y9 IO_L42N_2_W11 IO_L42P_2_V11 IO_L41N_VREF_2_AB10 IO_L41P_2_AA10 IO_L40N_2_Y12 IO_L40P_2_W12 IO_L32N_GCLK28_2_AB11 IO_L32P_GCLK29_2_Y11 IO_L31N_GCLK30_D15_2_AB12 IO_L31P_GCLK31_D14_2_AA12 IO_L30N_GCLK0_USERCCLK_2_AB13 IO_L30P_GCLK1_D13_2_Y13 IO_L29N_GCLK2_2_U12 IO_L29P_GCLK3_2_T12 IO_L23N_2_U15 IO_L23P_2_T15 IO_L22N_2_T11 IO_L22P_2_R11 IO_L21N_2_AB15 IO_L21P_2_Y15 IO_L20N_2_Y14 IO_L20P_2_W14 IO_L19N_2_AB16 IO_L19P_2_AA16 IO_L18N_2_W13 IO_L18P_2_V13 IO_L17N_2_W15 IO_L17P_2_Y16 IO_L16N_VREF_2_U13 IO_L16P_2_U14 IO_L15N_2_AB17 IO_L15P_2_Y17 IO_L14N_D12_2_AB18 IO_L14P_D11_2_AA18 IO_L13N_D10_2_AB19 IO_L13P_M1_2_Y19 IO_L12N_D2_MISO3_2_T14 IO_L12P_D1_MISO2_2_R13 IO_L6N_2_AB14 IO_L6P_2_AA14 IO_L5N_2_Y18 IO_L5P_2_W17 IO_L4N_VREF_2_V15 IO_L4P_2_U16 IO_L3N_MOSI_CSI_B_MISO0_2_AB20 IO_L3P_D0_DIN_MISO1_2_AA20 IO_L2N_CMPMOSI_2_W18 IO_L2P_CMPCLK_2_V17 IO_L1N_M0_CMPMISO_2_AA21 IO_L1P_CCLK_2_Y20 AA3 Y4 U6 T7 AB4 AA4 AB5 Y5 Y6 W6 R8 R9 W8 V7 U8 T8 V9 U9 AB6 AA6 Y8 W9 AB7 Y7 U10 T10 AB8 AA8 Y10 W10 AB9 Y9 W11 V11 AB10 AA10 Y12 W12 AB11 Y11 AB12 AA12 AB13 Y13 U12 T12 U15 T15 T11 R11 AB15 Y15 Y14 W14 AB16 AA16 W13 V13 W15 Y16 U13 U14 AB17 Y17 AB18 AA18 AB19 Y19 T14 R13 AB14 AA14 Y18 W17 V15 U16 AB20 AA20 W18 V17 AA21 Y20 SPI_CS_B FPGA_INIT_B FLASH_D9 FLASH_D8 GPIO_LED_1 IIC_SDA_DVI FLASH_D6 FLASH_D5 GPIO_SWITCH_1 GPIO_SWITCH_2 FMC_LA20_N FMC_LA20_P FMC_LA22_N FMC_LA22_P PHY_TXER PHY_TXCTL_TXEN FMC_LA23_N FMC_LA23_P FLASH_D4 FLASH_D3 SFP_TX_DISABLE_FPGA FLASH_D7 PHY_TXC_GTXCLK NC PHY_TXD0 PHY_TXD1 PHY_TXD2 PHY_TXD3 PMBUS_DATA PMBUS_CLK PHY_TXD4 PHY_TXD5 FMC_LA21_N FMC_LA21_P FMC_LA27_N FMC_LA27_P PHY_TXD6 PHY_TXD7 FMC_LA17_CC_N FMC_LA17_CC_P FLASH_D15 FLASH_D14 USER_CLOCK FLASH_D13 FMC_LA18_CC_N FMC_LA18_CC_P FMC_LA29_N FMC_LA29_P FMC_LA19_N FMC_LA19_P FMC_LA30_N FMC_LA30_P FMC_LA25_N FMC_LA25_P FMC_LA28_N FMC_LA28_P IIC_SCL_DVI 18 14,20 19 19 14 16,17 19 19 14 14 10 10 10 10 11 11 10 10 19 19 12 19 11 11 11 11 11 21,26 21,26 11 11 10 10 10 10 11 11 10 10 19 19 14 19 10 10 10 10 10 10 10 10 10 10 10 10 16,17 7,10,19 14 2 1 VCC2V5 R10 4.7K 5% 1/16W 10 FMC_PWR_GOOD_FLASH_RST_B GPIO_LED_3 FMC_PRSNT_M2C_L FMC_LA26_N FMC_LA26_P FMC_LA33_N FMC_LA33_P FLASH_D12 FLASH_D11 FLASH_D10 FPGA_M1 FPGA_D2_MISO3 FPGA_D1_MISO2 FMC_LA24_N FMC_LA24_P FMC_LA32_N FMC_LA32_P FMC_LA31_N FMC_LA31_P FPGA_MOSI_CSI_B_MISO0 FPGA_D0_DIN_MISO_MISO1 FPGA_CMP_MOSI FPGA_CMP_CLK FPGA_M0_CMP_MISO FPGA_CCLK 10 10 10 10 19 19 19 18 18,19 18,19 10 10 10 10 10 10 18 18,19 18 18 18 18 4 3 2 1 2 R285 140 1% 1/16W 1 C260 NPO 50V 120PF 2 D C B A FPGA Bank 2 Title: FPGA Bank 2 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 Date: Sheet Size: B Sheet 9-18-2009_15:04 of 4 35 1 Ver: Rev: D 04 Drawn By BF

4 3 2 1 D C B A VCC1V5_FPGA W2 U5 R2 N5 L7 L2 J5 G2 F4 C2 VCCO_3_W2 VCCO_3_U5 VCCO_3_R2 VCCO_3_N5 VCCO_3_L7 VCCO_3_L2 VCCO_3_J5 VCCO_3_G2 VCCO_3_F4 VCCO_3_C2 DUT BANK 3 6slx45tfg484 VTTVREF IO_L83N_VREF_3_B1 IO_L83P_3_C1 IO_L82N_3_G6 IO_L82P_3_F5 IO_L81N_3_H8 IO_L81P_3_J7 IO_L80N_3_G7 IO_L80P_3_H6 IO_L60N_3_E4 IO_L60P_3_F3 IO_L59N_3_D1 IO_L59P_3_D2 IO_L58N_3_G4 IO_L58P_3_H4 IO_L57N_VREF_3_K8 IO_L57P_3_K7 IO_L55N_M3A14_3_H5 IO_L55P_M3A13_3_J6 IO_L54N_M3A11_3_E1 IO_L54P_M3RESET_3_E3 IO_L53N_M3A12_3_F1 IO_L53P_M3CKE_3_F2 IO_L52N_M3A9_3_G1 IO_L52P_M3A8_3_G3 IO_L51N_M3A4_3_H3 IO_L51P_M3A10_3_J4 IO_L50N_M3BA2_3_H1 IO_L50P_M3WE_3_H2 IO_L49N_M3A2_3_K5 IO_L49P_M3A7_3_K6 IO_L48N_M3BA1_3_J1 IO_L48P_M3BA0_3_J3 IO_L47N_M3A1_3_K1 IO_L47P_M3A0_3_K2 IO_L46N_M3CLKN_3_K3 IO_L46P_M3CLK_3_K4 IO_L45N_M3ODT_3_L6 IO_L45P_M3A3_3_M6 IO_L44N_GCLK20_M3A6_3_L4 IO_L44P_GCLK21_M3A5_3_M3 IO_L43N_GCLK22_M3CASN_3_M4 IO_L43P_GCLK23_M3RASN_3_M5 IO_L42N_GCLK24_M3LDM_3_N4 IO_L42P_GCLK25_M3UDM_3_P3 IO_L41N_GCLK26_M3DQ5_3_L1 IO_L41P_GCLK27_M3DQ4_3_L3 IO_L40N_M3DQ7_3_M1 IO_L40P_M3DQ6_3_M2 IO_L39N_M3LDQSN_3_N1 IO_L39P_M3LDQS_3_N3 IO_L38N_M3DQ3_3_P1 IO_L38P_M3DQ2_3_P2 IO_L37N_M3DQ1_3_R1 IO_L37P_M3DQ0_3_R3 IO_L36N_M3DQ9_3_T1 IO_L36P_M3DQ8_3_T2 IO_L35N_M3DQ11_3_U1 IO_L35P_M3DQ10_3_U3 IO_L34N_M3UDQSN_3_V1 IO_L34P_M3UDQS_3_V2 IO_L33N_M3DQ13_3_W1 IO_L33P_M3DQ12_3_W3 IO_L32N_M3DQ15_3_Y1 IO_L32P_M3DQ14_3_Y2 IO_L31N_VREF_3_M8 IO_L31P_3_M7 IO_L26N_3_R4 IO_L26P_3_T3 IO_L25N_3_P7 IO_L25P_3_P6 IO_L24N_3_T4 IO_L24P_3_U4 IO_L23N_3_N7 IO_L23P_3_N6 IO_L10N_3_AA1 IO_L10P_3_AA2 IO_L9N_3_P4 IO_L9P_3_P5 IO_L8N_3_V3 IO_L8P_3_V5 IO_L7N_3_T5 IO_L7P_3_T6 IO_L2N_3_Y3 IO_L2P_3_W4 IO_L1N_VREF_3_P8 IO_L1P_3_R7 B1 C1 G6 F5 H8 J7 G7 H6 E4 F3 D1 D2 G4 H4 K8 K7 H5 J6 E1 E3 F1 F2 G1 G3 H3 J4 H1 H2 K5 K6 J1 J3 K1 K2 K3 K4 L6 M6 L4 M3 M4 M5 N4 P3 L1 L3 M1 M2 N1 N3 P1 P2 R1 R3 T1 T2 U1 U3 V1 V2 W1 W3 Y1 Y2 M8 M7 R4 T3 P7 P6 T4 U4 N7 N6 AA1 AA2 P4 P5 V3 V5 T5 T6 Y3 W4 P8 R7 F U 1 . 0 C 1 R 5 X V 0 1 1 2 GPIO_BUTTON3 GPIO_BUTTON1 GPIO_BUTTON2 CPU_RESET PCIE_PERST_B_LS GPIO_HEADER_0_LS GPIO_HEADER_1_LS GPIO_SWITCH_3 GPIO_BUTTON0 GPIO_HEADER_2_LS SYSACE_MPA06_LS SYSACE_MPA05_LS SYSACE_MPA04_LS 35 14 14 14 14 35 35 14 14 35 35 35 35 FPGA_ONCHIP_TERM2 MEM1_A14 MEM1_A13 MEM1_A11 MEM1_RESET_B MEM1_A12 MEM1_CKE MEM1_A9 MEM1_A8 MEM1_A4 MEM1_A10 MEM1_BA2 MEM1_WE_B MEM1_A2 MEM1_A7 MEM1_BA1 MEM1_BA0 MEM1_A1 MEM1_A0 MEM1_CLK_N MEM1_CLK_P MEM1_ODT MEM1_A3 MEM1_A6 MEM1_A5 MEM1_CAS_B MEM1_RAS_B MEM1_LDM MEM1_UDM MEM1_DQ5 MEM1_DQ4 MEM1_DQ7 MEM1_DQ6 MEM1_LDQS_N MEM1_LDQS_P MEM1_DQ3 MEM1_DQ2 MEM1_DQ1 MEM1_DQ0 MEM1_DQ9 MEM1_DQ8 MEM1_DQ11 MEM1_DQ10 MEM1_UDQS_N MEM1_UDQS_P MEM1_DQ13 MEM1_DQ12 MEM1_DQ15 MEM1_DQ14 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 FPGA_ONCHIP_TERM1 SYSACE_D7_LS SYSACE_D6_LS SYSACE_D5_LS SYSACE_D4_LS SYSACE_D3_LS SYSACE_D2_LS SYSACE_D1_LS SYSACE_D0_LS SYSACE_MPBRDY_LS SYSACE_MPIRQ_LS SYSACE_MPA03_LS SYSACE_MPA02_LS SYSACE_MPA01_LS SYSACE_MPA00_LS SYSACE_MPWE_LS SYSACE_MPOE_LS FPGA_VTEMP SYSACE_MPCE_LS 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 GPIO_HEADER_3_LS 35 4 U1 3 2 1 2 R126 100 5% 1/16W D C B 1 2 R124 DNP 1% 1/16W VCC1V5 1 2 R207 150 5% 1/16W FPGA Bank 3 Title: FPGA Bank 3 SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Date: Sheet Size: B Sheet 9-18-2009_15:04 of 5 35 1 Ver: Rev: D 04 Drawn By PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 A BF

4 3 2 1 D C B A U1 U1 4 MGTTXP0_101_B6 MGTTXN0_101_A6 MGTRXP0_101_D7 MGTRXN0_101_C7 MGTTXP1_101_B8 MGTTXN1_101_A8 MGTRXP1_101_D9 MGTRXN1_101_C9 MGTREFCLK0P_101_A10 MGTREFCLK0N_101_B10 MGTREFCLK1P_101_C11 MGTREFCLK1N_101_D11 MGTAVCCPLL0_101_B9 MGTAVCCPLL1_101_D12 MGTAVCC_101_C10 MGTAVTTTX_101_A7 MGTAVTTRX_101_D8 B6 A6 D7 C7 B8 A8 D9 C9 A10 B10 C11 D11 B9 D12 C10 A7 D8 PCIE_TX0_P PCIE_TX0_N PCIE_RX0_P PCIE_RX0_N SMA_TX_P SMA_TX_N SMA_RX_P SMA_RX_N PCIE_250M_P PCIE_250M_N SMA_REFCLK_P SMA_REFCLK_N 12 12 12 12 13 13 13 13 28 28 13 13 MGT_AVCC MGT_AVCC 1 C307 X7R 10V 0.22UF 2 1 2 C308 X7R 10V 0.22UF 1 C309 X7R 10V 0.22UF 2 1 2 C310 X7R 10V 0.22UF 1 C311 X7R 10V 0.22UF 2 1 2 C312 X7R 10V 0.22UF 1 C313 X7R 10V 0.22UF 2 1 2 C314 X7R 10V 0.22UF 1 C315 X7R 10V 0.22UF 2 1 2 C316 X7R 10V 0.22UF 1 C326 X5R 10V 4.7UF 2 1 2 C327 X5R 10V 4.7UF 1 C328 X5R 10V 4.7UF 2 1 2 C329 X5R 10V 4.7UF D C B DUT BANK 101 6slx45tfg484 DUT BANK 123 6slx45tfg484 MGTTXP0_123_B14 MGTTXN0_123_A14 MGTRXP0_123_D13 MGTRXN0_123_C13 MGTTXP1_123_B16 MGTTXN1_123_A16 MGTRXP1_123_D15 MGTRXN1_123_C15 MGTREFCLK0P_123_A12 MGTREFCLK0N_123_B12 MGTREFCLK1P_123_E12 MGTREFCLK1N_123_F12 MGTAVCCPLL0_123_B13 MGTAVCCPLL1_123_E13 MGTAVCC_123_E10 MGTAVTTTX_123_A15 MGTAVTTRX_123_D14 B14 A14 D13 C13 B16 A16 D15 C15 A12 B12 E12 F12 B13 E13 E10 A15 D14 SFP_TX_P SFP_TX_N SFP_RX_P SFP_RX_N FMC_DP0_C2M_P FMC_DP0_C2M_N FMC_DP0_M2C_P FMC_DP0_M2C_N SFPCLK_QO_P SFPCLK_QO_N FMC_GBTCLK0_M2C_C_P FMC_GBTCLK0_M2C_C_N 12 12 12 12 10 10 10 10 28 28 6 6 MGT_AVCC 10 FMC_GBTCLK0_M2C_P 10 FMC_GBTCLK0_M2C_N F U C 1 4 . 0 0 0 V 0 1 R 5 X 21 C 4 0 1 F U 1 . 0 R 5 X V 0 1 1 2 FMC_GBTCLK0_M2C_C_P 6 FMC_GBTCLK0_M2C_C_N 6 3 2 MGT Banks Title: MGT Banks SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Date: Sheet Size: B Sheet 9-18-2009_15:04 of 6 35 1 Ver: Rev: D 04 Drawn By PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 A BF

4 3 2 1 D C B A U1 DUT BANK GND 6slx45tfg484 DUT BANK VCCAUX 6slx45tfg484 VCCAUX_V6 VCCAUX_U11 VCCAUX_R6 VCCAUX_R12 VCCAUX_R10 VCCAUX_N8 VCCAUX_M15 VCCAUX_L8 VCCAUX_K15 VCCAUX_H9 VCCAUX_H15 VCCAUX_G12 VCCAUX_F11 V6 U11 R6 R12 R10 N8 M15 L8 K15 H9 H15 G12 F11 VCCAUX U1 DUT BANK VCCINT 6slx45tfg484 VCCINT_FPGA VCCINT_R14 VCCINT_P9 VCCINT_P13 VCCINT_P11 VCCINT_N14 VCCINT_N12 VCCINT_N10 VCCINT_M9 VCCINT_M13 VCCINT_M11 VCCINT_L14 VCCINT_L12 VCCINT_L10 VCCINT_K9 VCCINT_K13 VCCINT_K11 VCCINT_J8 VCCINT_J14 VCCINT_J12 VCCINT_J10 R14 P9 P13 P11 N14 N12 N10 M9 M13 M11 L14 L12 L10 K9 K13 K11 J8 J14 J12 J10 GND_W7 GND_W19 GND_W16 GND_V4 GND_V14 GND_V10 GND_U7 GND_U21 GND_U2 GND_R5 GND_R18 GND_P14 GND_P12 GND_P10 GND_N9 GND_N21 GND_N2 GND_N17 GND_N13 GND_N11 GND_M14 GND_M12 GND_M10 GND_L9 GND_L5 GND_L18 GND_L13 GND_L11 GND_K14 GND_K12 GND_K10 GND_J9 GND_J21 GND_J2 GND_J15 GND_J13 GND_J11 GND_H7 GND_G5 GND_G18 GND_F13 GND_E7 GND_E21 GND_E2 GND_E15 GND_E14 GND_E11 GND_D6 GND_D16 GND_D10 GND_C8 GND_C6 GND_C16 GND_C14 GND_C12 GND_B7 GND_B5 GND_B17 GND_B15 GND_B11 GND_AB22 GND_AB1 GND_AA9 GND_AA5 GND_AA17 GND_AA13 GND_A9 GND_A22 GND_A13 GND_A11 GND_A1 W7 W19 W16 V4 V14 V10 U7 U21 U2 R5 R18 P14 P12 P10 N9 N21 N2 N17 N13 N11 M14 M12 M10 L9 L5 L18 L13 L11 K14 K12 K10 J9 J21 J2 J15 J13 J11 H7 G5 G18 F13 E7 E21 E2 E15 E14 E11 D6 D16 D10 C8 C6 C16 C14 C12 B7 B5 B17 B15 B11 AB22 AB1 AA9 AA5 AA17 AA13 A9 A22 A13 A11 A1 U1 U1 4 3 2 VCCAUX 1 1 P N D 1 8 8 2 R DUT BANK DED 6slx45tfg484 W 6 1 / 1 2 % 1 Pins not connected in LX45T NC_P15 NC_T16 NC_U17 MGTAVTTRCAL_101_E8 MGTRREF_101_E9 PROGRAM_B_2_AB2 DONE_2_AB21 CMPCS_B_2_V18 SUSPEND_AA22 TDO_G17 TMS_D20 TDI_E18 TCK_A21 P15 T16 U17 E8 E9 AB2 AB21 V18 AA22 G17 D20 E18 A21 P N D 9 5 J 2 X 1 - H 8 5 J FMC_PWR_GOOD_FLASH_RST_B 4,10,19 MGT_AVCC D 1/16W 1% 49.9 R127 2 1 VCC2V5 1 2 R11 4.7K 5% 1/16W FPGA_CMP_CS_B 18 2 2 1 2 R260 DNP 1% 1/16W FPGA_VBATT 15 FPGA_PROG_B FPGA_DONE 14,18,20 14 FPGA_SUSPEND SYSACE_CFGTDI FPGA_TMS FPGA_TDI FPGA_TCK 18 20 20 20 20 Trace length from the resistor pins to the FPGA pins MGTRREF and MGTVTTRCAL must be equal in length. C VCC3V3 VCC3V3 R172 10K 5% 1/16W 1 2 32 32 32 JTAG_TDI JTAG_TMS JTAG_TCK NC NC NC U8 SN74LV541APWR 1 2 3 4 5 6 7 8 9 10 OE1_N A1 A2 A3 A4 A5 A6 A7 A8 GND VCC OE2_N Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 20 19 18 17 16 15 14 13 12 11 C2 1 0.1UF 2 10V X5R FMC_TDI_BUF FMC_TMS_BUF SYSACE_TMS_BUF FMC_TCK_BUF SYSACE_TCK_BUF NC NC NC 10 10 20 10 20 Power, GND, and Dedicated Banks Title: Power, GND, and Dedicated Banks SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 Date: Sheet Size: B Sheet 9-24-2009_14:59 of 7 35 1 Ver: Rev: D 04 Drawn By BF B A

4 3 2 1 D C B A VCCINT_FPGA VCCINT 1.2V 1 2 C255 470UF 6.3V TANT 2 1 10UF 6.3V X5R C179 0805 2 10UF 6.3V X5R 1 C178 0805 2 1 10UF 6.3V X5R C177 0805 2 10UF 6.3V X5R 1 C180 0805 2 10UF 6.3V X5R 1 C176 0805 2 2.2UF 6.3V X5R 1 C115 0402 2 2.2UF 6.3V X5R 1 C108 0402 2 1 2.2UF 6.3V X5R C107 0402 2 2.2UF 6.3V X5R 1 C106 0402 2 1 2.2UF 6.3V X5R C105 0402 2 1 2.2UF 6.3V X5R C103 0402 2 1 2.2UF 6.3V X5R C111 0402 VCC2V5_FPGA VCCO 2.5V 1 2 C254 470UF 6.3V TANT 2 1 10UF 6.3V X5R C183 0805 2 10UF 6.3V X5R 1 C182 0805 2 1 10UF 6.3V X5R C181 0805 2 1 10UF 6.3V X5R C175 0805 2 1 10UF 6.3V X5R C173 0805 2 10UF 6.3V X5R 1 C186 0805 2 10UF 6.3V X5R 1 C174 0805 2 10UF 6.3V X5R 1 C184 0805 2 1 10UF 6.3V X5R C185 0805 2 1 10UF 6.3V X5R C172 0805 2 10UF 6.3V X5R 1 C171 0805 2 2.2UF 6.3V X5R 1 C113 0402 2 2.2UF 6.3V X5R 1 C102 0402 2 1 2.2UF 6.3V X5R C101 0402 2 2.2UF 6.3V X5R 1 C100 0402 2 1 2.2UF 6.3V X5R C99 0402 2 2.2UF 6.3V X5R 1 C129 0402 2 1 2.2UF 6.3V X5R C126 0402 2 1 2.2UF 6.3V X5R C120 0402 2 2.2UF 6.3V X5R 1 C119 0402 2 1 2.2UF 6.3V X5R C112 0402 2 2.2UF 6.3V X5R 1 C110 0402 2 1 2.2UF 6.3V X5R C109 0402 2 2.2UF 6.3V X5R 1 C104 0402 2 2.2UF 6.3V X5R 1 C98 0402 2 1 2.2UF 6.3V X5R C114 0402 VCC1V5_FPGA VCCO Bank 3 1.5V 1 2 C256 470UF 6.3V TANT 2 1 10UF 6.3V X5R C189 0805 2 10UF 6.3V X5R 1 C188 0805 2 1 10UF 6.3V X5R C187 0805 2 1 2.2UF 6.3V X5R C118 0402 2 2.2UF 6.3V X5R 1 C117 0402 2 1 2.2UF 6.3V X5R C116 0402 4 3 2 VCCAUX 2.5V VCCAUX 1 2 C257 470UF 6.3V TANT 2 2.2UF 6.3V X5R 1 C121 0402 2 1 2 1 10UF 6.3V X5R C389 0805 2 10UF 6.3V X5R 1 C390 0805 2.2UF 6.3V X5R C122 0402 2 2.2UF 6.3V X5R 1 C123 0402 2 1 2 1 10UF 6.3V X5R C192 0805 2.2UF 6.3V X5R C124 0402 2 2.2UF 6.3V X5R 1 C125 0402 2 2.2UF 6.3V X5R 1 C127 0402 2 1 2.2UF 6.3V X5R C128 0402 D C B FPGA Decoupling Title: FPGA Decoupling SCHEM, ROHS COMPLIANT SP605 EVALUATION PLATFORM Date: Sheet Size: B Sheet 9-24-2009_15:46 of 8 35 1 Ver: Rev: D 04 Drawn By PCB P/N: 0431534 SCH P/N: 0381305 Test P/N: TSS0123 ART P/N: 1280473 A BF

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