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RTL8211D/DN PDF.pdf
RTL8211D-VB-GR
RTL8211DG-VB-GR
RTL8211DN-VB-GR
INTEGRATED 10/100/1000MBPS ETHERNET
TRANSCEIVER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.2
13 August 2010
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
COPYRIGHT
©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094,
US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision Release Date Summary
1.0
1.1
2010/04/28
2010/08/09
1.2
2010/08/13
First release.
Revised IEEE 802.3az to Draft 3.2.
Added section 3.7 UTP/Fiber Auto-Detection to GMII/RGMII Application Diagram
(RTL8211DN), page 5.
Revised Table 15 MII/MDI Interface Configuration, page 19.
Added section 6.9 Green Ethernet (Gigabit Mode Only), page 20.
Added section 6.10.6 Access to Extension Page (ExtPage), page 22.
Added section 6.10.7 Access to MDIO Manageable Device (MMD), page 22.
Revised Table 21 Page0 Register Mapping and Definitions, page 32.
Added section 7.3 MMD Register Mapping and Definition, page 33.
Added Table 35 MACR (MMD Access Control Register, Address 0x0D), page 40.
Added Table 36 MAADR (MMD Access Address Data Register, Address 0x0E), page 41.
Added Table 45, page 44 to Table 50, page 45.
Revised section 9.6.4 RGMII Timing Modes, page 61.
Revised section 9.6.2 MII Timing Modes, page 58.
Revised section 9.6.5 SGMII Timing Modes, page 64.
Integrated 10/100/1000Mbps Ethernet Transceiver
ii
Track ID: JATR-2265-11 Rev. 1.2
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
Table of Contents
1. GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
2.
3.
4.
5.
6.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
3.1.
3.2.
3.3.
3.4.
3.5.
3.6.
3.7.
SYSTEM APPLICATIONS...............................................................................................................................................3
APPLICATION DIAGRAM (RTL8211D).........................................................................................................................3
APPLICATION DIAGRAM (RTL8211DG) ......................................................................................................................3
FIBER APPLICATION DIAGRAM (RTL8211DN)............................................................................................................4
UTP APPLICATION DIAGRAM (RTL8211DN)..............................................................................................................4
FIBER TO UTP (BRIDGE MODE) APPLICATION DIAGRAM (RTL8211DN)....................................................................4
SGMII TO GMII/RGMII (BRIDGE MODE) APPLICATION DIAGRAM (RTL8211DN)....................................................5
UTP/FIBER AUTO-DETECTION TO GMII/RGMII APPLICATION DIAGRAM (RTL8211DN)..........................................5
PIN ASSIGNMENTS .........................................................................................................................................................6
RTL8211D PIN ASSIGNMENTS (48-PIN QFN) .............................................................................................................6
PACKAGE IDENTIFICATION...........................................................................................................................................6
RTL8211DG PIN ASSIGNMENTS (64-PIN QFN) ..........................................................................................................7
PACKAGE IDENTIFICATION...........................................................................................................................................7
RTL8211DN PIN ASSIGNMENTS (88-PIN QFN) ..........................................................................................................8
PACKAGE IDENTIFICATION...........................................................................................................................................8
PIN DESCRIPTIONS ........................................................................................................................................................9
TRANSCEIVER INTERFACE............................................................................................................................................9
5.1.
CLOCK .........................................................................................................................................................................9
5.2.
GMII/MII (RTL8211DN AND RTL8211DG ONLY)..................................................................................................10
5.3.
RGMII.......................................................................................................................................................................11
5.4.
SGMII (RTL8211DN ONLY) ....................................................................................................................................12
5.5.
MANAGEMENT INTERFACE.........................................................................................................................................12
5.6.
RESET ........................................................................................................................................................................13
5.7.
MODE SELECTION ......................................................................................................................................................13
5.8.
LED INDICATION .......................................................................................................................................................13
5.9.
5.10. REGULATOR AND REFERENCE....................................................................................................................................14
5.11.
POWER AND GROUND ................................................................................................................................................14
5.12. NOT CONNECTED.......................................................................................................................................................14
FUNCTION DESCRIPTION ..........................................................................................................................................15
1000BASE-T TRANSMITTER.......................................................................................................................................15
6.1.
1000BASE-T RECEIVER .............................................................................................................................................15
6.2.
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................15
6.3.
6.4. WAKE-ON-LAN (WOL)............................................................................................................................................16
MDI INTERFACE ........................................................................................................................................................16
6.5.
6.6.
SERDES (SGMII) INTERFACE (RTL8211DN ONLY)..................................................................................................17
6.7.
HARDWARE CONFIGURATION ....................................................................................................................................17
6.8.
LED AND PHY ADDRESS CONFIGURATION ...............................................................................................................19
GREEN ETHERNET (GIGABIT MODE ONLY)................................................................................................................20
6.9.
6.9.1. Cable Length Power Saving.................................................................................................................................20
6.9.2. Register Setting.....................................................................................................................................................20
6.10. MAC/PHY INTERFACE..............................................................................................................................................20
MII ...................................................................................................................................................................20
6.10.1.
GMII ................................................................................................................................................................21
6.10.2.
6.10.3.
RGMII..............................................................................................................................................................21
Track ID: JATR-2265-11 Rev. 1.2
Integrated 10/100/1000Mbps Ethernet Transceiver
iii
7.1.
7.2.
7.3.
7.4.
6.10.4.
6.10.5.
6.10.6.
6.10.7.
6.11.1.
6.11.2.
6.11.3.
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
SGMII ..............................................................................................................................................................21
Management Interface.....................................................................................................................................21
Access to Extension Page (ExtPage) ...............................................................................................................22
Access to MDIO Manageable Device (MMD).................................................................................................22
6.11. AUTO-NEGOTIATION..................................................................................................................................................23
Auto-Negotiation Priority Resolution..............................................................................................................26
Auto-Negotiation Master/Slave Resolution .....................................................................................................26
Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution........................................................................27
6.12. CROSSOVER DETECTION AND AUTO-CORRECTION ....................................................................................................28
LED CONFIGURATION................................................................................................................................................29
6.13.
6.14.
POLARITY CORRECTION.............................................................................................................................................31
6.15.
POWER .......................................................................................................................................................................31
7. REGISTER DESCRIPTIONS.........................................................................................................................................32
PAGE0 REGISTER MAPPING AND DEFINITIONS...........................................................................................................32
EXTENSION PAGE REGISTER MAPPING AND DEFINITION............................................................................................32
MMD REGISTER MAPPING AND DEFINITION..............................................................................................................33
REGISTER TABLE .......................................................................................................................................................33
7.4.1. BMCR (Basic Mode Control Register, Address 0x00) .........................................................................................33
7.4.2. BMSR (Basic Mode Status Register, Address 0x01).............................................................................................35
7.4.3. PHYID1 (PHY Identifier Register 1, Address 0x02) ............................................................................................36
7.4.4. PHYID2 (PHY Identifier Register 2, Address 0x03) ............................................................................................36
7.4.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04) ...........................................................................37
7.4.6. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) .........................................................37
7.4.7. ANER (Auto-Negotiation Expansion Register, Address 0x06).............................................................................38
7.4.8. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07) .........................................................38
7.4.9. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)...........................................................39
GBCR (1000Base-T Control Register, Address 0x09).....................................................................................39
7.4.10.
7.4.11.
GBSR (1000Base-T Status Register, Address 0x0A) .......................................................................................40
7.4.12.
MACR (MMD Access Control Register, Address 0x0D) .................................................................................40
MAADR (MMD Access Address Data Register, Address 0x0E)......................................................................41
7.4.13.
GBESR (1000Base-T Extended Status Register, Address 0x0F) .....................................................................41
7.4.14.
7.4.15.
PHYCR (PHY Specific Control Register, Address 0x10).................................................................................41
7.4.16.
PHYSR (PHY Specific Status Register, Address 0x11)....................................................................................42
7.4.17.
INER (Interrupt Enable Register, Address 0x12) ............................................................................................42
INSR (Interrupt Status Register, Address 0x13) ..............................................................................................43
7.4.18.
7.4.19.
RXERC (Receive Error Counter, Address 0x18).............................................................................................43
7.4.20.
PAGSEL (Page Select Register, Address 0x1F) ..............................................................................................43
7.4.21.
SDSR (SerDes Register, ExtPage 140, Address 0x16) ....................................................................................44
PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) ....................................................................44
7.4.22.
PS1R (PCS Status1 Register, MMD Device 3, Address 0x01) ........................................................................44
7.4.23.
7.4.24.
EEECR (EEE Capability Register, MMD Device 3, Address 0x14)................................................................44
7.4.25.
EEEWER (EEE Wake Error Register, MMD Device 3, Address 0x16) ..........................................................45
EEEAR (EEE Advertisement Register, MMD Device 7, Address 0x3c) ..........................................................45
7.4.26.
7.4.27.
EEELPAR (EEE Link Partner Ability Register, MMD Device 7, Address 0x3d)............................................45
SWITCHING REGULATOR..........................................................................................................................................46
PCB LAYOUT.............................................................................................................................................................46
INDUCTOR AND CAPACITOR PARTS LIST....................................................................................................................47
MEASUREMENT CRITERIA..........................................................................................................................................48
EFFICIENCY MEASUREMENT ......................................................................................................................................52
POWER SEQUENCE .....................................................................................................................................................53
8.
8.1.
8.2.
8.3.
8.4.
8.5.
Integrated 10/100/1000Mbps Ethernet Transceiver
iv
Track ID: JATR-2265-11 Rev. 1.2
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
9. CHARACTERISTICS .....................................................................................................................................................54
ABSOLUTE MAXIMUM RATINGS.................................................................................................................................54
RECOMMENDED OPERATING CONDITIONS .................................................................................................................54
CRYSTAL REQUIREMENTS..........................................................................................................................................55
OSCILLATOR REQUIREMENTS.....................................................................................................................................55
DC CHARACTERISTICS...............................................................................................................................................56
SGMII DC Characteristics...................................................................................................................................56
9.5.1.
AC CHARACTERISTICS...............................................................................................................................................57
9.6.1. MDC/MDIO Timing .............................................................................................................................................57
9.6.2. MII Timing Modes................................................................................................................................................58
9.6.3. GMII Timing Modes .............................................................................................................................................60
9.6.4. RGMII Timing Modes...........................................................................................................................................61
9.6.5.
SGMII Timing Modes ...........................................................................................................................................64
MECHANICAL DIMENSIONS.................................................................................................................................66
10.1. RTL8211D 48-PIN QFN MECHANICAL DIMENSIONS ................................................................................................66
10.2. RTL8211D 48-PIN QFN MECHANICAL DIMENSIONS NOTES.....................................................................................66
10.3. RTL8211DG 64-PIN QFN MECHANICAL DIMENSIONS .............................................................................................67
10.4. RTL8211DG 64-PIN QFN MECHANICAL DIMENSIONS NOTES..................................................................................68
10.5. RTL8211DN 88-PIN QFN MECHANICAL DIMENSIONS .............................................................................................69
10.6. RTL8211DN 88-PIN QFN MECHANICAL DIMENSIONS NOTES..................................................................................70
ORDERING INFORMATION...................................................................................................................................71
10.
11.
Integrated 10/100/1000Mbps Ethernet Transceiver
v
Track ID: JATR-2265-11 Rev. 1.2
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
List of Tables
TABLE 1. TRANSCEIVER INTERFACE .............................................................................................................................................9
TABLE 2. CLOCK...........................................................................................................................................................................9
TABLE 3. GMII/MII (RTL8211DG AND RTL8211DN ONLY) ...................................................................................................10
TABLE 4. RGMII ........................................................................................................................................................................11
TABLE 5. SGMII (RTL8211DN ONLY)......................................................................................................................................12
TABLE 6. MANAGEMENT INTERFACE..........................................................................................................................................12
TABLE 7. RESET..........................................................................................................................................................................13
TABLE 8. MODE SELECTION........................................................................................................................................................13
TABLE 9. LED INDICATION.........................................................................................................................................................13
TABLE 10. REGULATOR AND REFERENCE.....................................................................................................................................14
TABLE 11. POWER AND GROUND .................................................................................................................................................14
TABLE 12. NOT CONNECTED........................................................................................................................................................14
TABLE 13. CONFIG PINS VS. CONFIGURATION REGISTER ...........................................................................................................17
TABLE 14. CONFIGURATION REGISTER DEFINITION (PHY AD AND NWAY)................................................................................18
TABLE 15. MII/MDI INTERFACE CONFIGURATION.......................................................................................................................19
TABLE 16. TYPICAL MDIO FRAME FORMAT................................................................................................................................21
TABLE 17. 1000BASE-T AND NEXT PAGES BIT ASSIGNMENTS.....................................................................................................24
TABLE 18. LED DEFAULT DEFINITIONS.......................................................................................................................................29
TABLE 19. LED REGISTER TABLE................................................................................................................................................29
TABLE 20. LED CONFIGURATION TABLE.....................................................................................................................................30
TABLE 21. PAGE0 REGISTER MAPPING AND DEFINITIONS............................................................................................................32
TABLE 22. EXTENSION PAGE REGISTER MAPPING AND DEFINITION.............................................................................................32
TABLE 23. MMD REGISTER MAPPING AND DEFINITION...............................................................................................................33
TABLE 24. BMCR (BASIC MODE CONTROL REGISTER, ADDRESS 0X00) .....................................................................................33
TABLE 25. BMSR (BASIC MODE STATUS REGISTER, ADDRESS 0X01).........................................................................................35
TABLE 26. PHYID1 (PHY IDENTIFIER REGISTER 1, ADDRESS 0X02) ..........................................................................................36
TABLE 27. PHYID2 (PHY IDENTIFIER REGISTER 2, ADDRESS 0X03) ..........................................................................................36
TABLE 28. ANAR (AUTO-NEGOTIATION ADVERTISING REGISTER, ADDRESS 0X04)...................................................................37
TABLE 29. ANLPAR (AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER, ADDRESS 0X05) ..............................................37
TABLE 30. ANER (AUTO-NEGOTIATION EXPANSION REGISTER, ADDRESS 0X06).......................................................................38
TABLE 31. ANNPTR (AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER, ADDRESS 0X07)................................................38
TABLE 32. ANNPRR (AUTO-NEGOTIATION NEXT PAGE RECEIVE REGISTER, ADDRESS 0X08)...................................................39
TABLE 33. GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) ......................................................................................39
TABLE 34. GBSR (1000BASE-T STATUS REGISTER, ADDRESS 0X0A).........................................................................................40
TABLE 35. MACR (MMD ACCESS CONTROL REGISTER, ADDRESS 0X0D)..................................................................................40
TABLE 36. MAADR (MMD ACCESS ADDRESS DATA REGISTER, ADDRESS 0X0E) .....................................................................41
TABLE 37. GBESR (1000BASE-T EXTENDED STATUS REGISTER, ADDRESS 0X0F) .....................................................................41
TABLE 38. PHYCR (PHY SPECIFIC CONTROL REGISTER, ADDRESS 0X10)..................................................................................41
TABLE 39. PHYSR (PHY SPECIFIC STATUS REGISTER, ADDRESS 0X11) .....................................................................................42
TABLE 40. INER (INTERRUPT ENABLE REGISTER, ADDRESS 0X12) .............................................................................................42
TABLE 41. INSR (INTERRUPT STATUS REGISTER, ADDRESS 0X13)..............................................................................................43
TABLE 42. RXERC (RECEIVE ERROR COUNTER, ADDRESS 0X18)...............................................................................................43
TABLE 43. PAGSEL (PAGE SELECT REGISTER, ADDRESS 0X1F).................................................................................................43
TABLE 44. SDSR (SERDES REGISTER, EXTPAGE 140, ADDRESS 0X16) .......................................................................................44
TABLE 45. PC1R (PCS CONTROL 1 REGISTER, MMD DEVICE 3, ADDRESS 0X00).......................................................................44
TABLE 46. PS1R (PCS STATUS 1 REGISTER, MMD DEVICE 3, ADDRESS 0X01) ..........................................................................44
TABLE 47. EEECR (EEE CAPABILITY REGISTER, MMD DEVICE 3, ADDRESS 0X14) ..................................................................44
TABLE 48. EEEWER (EEE WAKE ERROR REGISTER, MMD DEVICE 3, ADDRESS 0X16)............................................................45
TABLE 49. EEEAR (EEE ADVERTISEMENT REGISTER, MMD DEVICE 7, ADDRESS 0X3C) ..........................................................45
TABLE 50. EEELPAR (EEE LINK PARTNER ABILITY REGISTER, MMD DEVICE 7, ADDRESS 0X3D)...........................................45
TABLE 51. INDUCTOR AND CAPACITOR PARTS LIST.....................................................................................................................47
Track ID: JATR-2265-11 Rev. 1.2
Integrated 10/100/1000Mbps Ethernet Transceiver
vi
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
TABLE 52. POWER SEQUENCE PARAMETER..................................................................................................................................53
TABLE 53. ABSOLUTE MAXIMUM RATINGS..................................................................................................................................54
TABLE 54. RECOMMENDED OPERATING CONDITIONS ..................................................................................................................54
TABLE 55. CRYSTAL REQUIREMENTS...........................................................................................................................................55
TABLE 56. OSCILLATOR REQUIREMENTS......................................................................................................................................55
TABLE 57. DC CHARACTERISTICS................................................................................................................................................56
TABLE 58. DIFFERENTIAL TRANSMITTER OUTPUT DC CHARACTERISTICS...................................................................................56
TABLE 59. DIFFERENTIAL RECEIVER INPUT DC CHARACTERISTICS.............................................................................................56
TABLE 60. MDC/MDIO MANAGEMENT TIMING PARAMETERS....................................................................................................57
TABLE 61. MII TRANSMIT TIMING PARAMETERS .........................................................................................................................58
TABLE 62. MII RECEIVE TIMING PARAMETERS............................................................................................................................59
TABLE 63. GMII TIMING PARAMETERS........................................................................................................................................60
TABLE 64. RGMII TIMING PARAMETERS.....................................................................................................................................63
TABLE 65. DIFFERENTIAL TRANSMITTER OUTPUT AC TIMING ....................................................................................................65
TABLE 66. DIFFERENTIAL RECEIVER INPUT AC TIMING...............................................................................................................65
TABLE 67. ORDERING INFORMATION ...........................................................................................................................................71
Integrated 10/100/1000Mbps Ethernet Transceiver
vii
Track ID: JATR-2265-11 Rev. 1.2
RTL8211D/RTL8211DG/RTL8211DN
Datasheet
List of Figures
FIGURE 1. APPLICATION DIAGRAM (RTL8211D)..........................................................................................................................3
FIGURE 2. APPLICATION DIAGRAM (RTL8211DG) .......................................................................................................................3
FIGURE 3. FIBER APPLICATION DIAGRAM (RTL8211DN).............................................................................................................4
FIGURE 4. UTP APPLICATION DIAGRAM (RTL8211DN)...............................................................................................................4
FIGURE 5. FIBER TO UTP (BRIDGE MODE) APPLICATION DIAGRAM (RTL8211DN).....................................................................4
FIGURE 6. SGMII TO GMII/RGMII (BRIDGE MODE) APPLICATION DIAGRAM (RTL8211DN).....................................................5
FIGURE 7. UTP/FIBER AUTO-DETECTION TO GMII/RGMII APPLICATION DIAGRAM (RTL8211DN)...........................................5
FIGURE 8. RTL8211D PIN ASSIGNMENTS (48-PIN QFN) ..............................................................................................................6
FIGURE 9. RTL8211DG PIN ASSIGNMENTS (64-PIN QFN) ...........................................................................................................7
FIGURE 10. RTL8211DN PIN ASSIGNMENTS (88-PIN QFN)...........................................................................................................8
FIGURE 11. PHY APPLICATION (RTL8211DN) ............................................................................................................................17
FIGURE 12. LED AND PHY ADDRESS CONFIGURATION................................................................................................................19
FIGURE 13. TYPICAL MDC/MDIO READ TIMING .........................................................................................................................22
FIGURE 14. TYPICAL MDC/MDIO WRITE TIMING .......................................................................................................................22
FIGURE 15. SWITCHING REGULATOR.............................................................................................................................................46
FIGURE 16. INPUT VOLTAGE OVERSHOOT <4V (GOOD)................................................................................................................48
FIGURE 17. INPUT VOLTAGE OVERSHOOT >4V (BAD) ..................................................................................................................48
FIGURE 18. CERAMIC 22µF 1210(X5R) (GOOD) ...........................................................................................................................49
FIGURE 19. CERAMIC 22µF 0805(Y5V) (BAD)..............................................................................................................................49
FIGURE 20. ELECTROLYTIC 100µF (RIPPLE TOO HIGH).................................................................................................................50
FIGURE 21. 4R7GTSD32 (GOOD).................................................................................................................................................51
FIGURE 22. 1µH BEAD (BAD)........................................................................................................................................................51
FIGURE 23. SWITCHING REGULATOR EFFICIENCY MEASUREMENT CHECKPOINT..........................................................................52
FIGURE 24. POWER SEQUENCE......................................................................................................................................................53
FIGURE 25. MDC/MDIO MANAGEMENT TIMING PARAMETERS ...................................................................................................57
FIGURE 26. MII TIMING – MII PORT – TRANSMIT .......................................................................................................................58
FIGURE 27. MII TIMING – MII PORT – RECEIVE ..........................................................................................................................59
FIGURE 28. GMII TIMING .............................................................................................................................................................60
FIGURE 29. RGMII TIMING MODES ..............................................................................................................................................62
FIGURE 30. SGMII TIMING MODES...............................................................................................................................................64
Integrated 10/100/1000Mbps Ethernet Transceiver
viii
Track ID: JATR-2265-11 Rev. 1.2
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