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拉扎维模拟集成电路英文版_2016_McGraw_Behzad Razavi-Hill Education (2016).pdf
Cover
Title
Copyright
Preface to the Second Edition
About the Author
Contents
1 Introduction to Analog Design
1.1 Why Analog?
1.1.1 Sensing and Processing Signals
1.1.2 When Digital Signals Become Analog
1.1.3 Analog Design Is in Great Demand
1.1.4 Analog Design Challenges
1.2 Why Integrated?
1.3 Why CMOS?
1.4 Why This Book?
1.5 Levels of Abstraction
2 Basic MOS Device Physics
2.1 General Considerations
2.1.1 MOSFET as a Switch
2.1.2 MOSFET Structure
2.1.3 MOS Symbols
2.2 MOS I/V Characteristics
2.2.1 Threshold Voltage
2.2.2 Derivation of I/V Characteristics
2.2.3 MOS Transconductance
2.3 Second-Order Effects
2.4 MOS Device Models
2.4.1 MOS Device Layout
2.4.2 MOS Device Capacitances
2.4.3 MOS Small-Signal Model
2.4.4 MOS SPICE models
2.4.5 NMOS Versus PMOS Devices
2.4.6 Long-Channel Versus Short-Channel Devices
2.5 Appendix A: FinFETs
2.6 Appendix B: Behavior of a MOS Device as a Capacitor
3 Single-Stage Amplifiers
3.1 Applications
3.2 General Considerations
3.3 Common-Source Stage
3.3.1 Common-Source Stage with Resistive Load
3.3.2 CS Stage with Diode-Connected Load
3.3.3 CS Stage with Current-Source Load
3.3.4 CS Stage with Active Load
3.3.5 CS Stage with Triode Load
3.3.6 CS Stage with Source Degeneration
3.4 Source Follower
3.5 Common-Gate Stage
3.6 Cascode Stage
3.6.1 Folded Cascode
3.7 Choice of Device Models
4 Differential Amplifiers
4.1 Single-Ended and Differential Operation
4.2 Basic Differential Pair
4.2.1 Qualitative Analysis
4.2.2 Quantitative Analysis
4.2.3 Degenerated Differential Pair
4.3 Common-Mode Response
4.4 Differential Pair with MOS Loads
4.5 Gilbert Cell
5 Current Mirrors and Biasing Techniques
5.1 Basic Current Mirrors
5.2 Cascode Current Mirrors
5.3 Active Current Mirrors
5.3.1 Large-Signal Analysis
5.3.2 Small-Signal Analysis
5.3.3 Common-Mode Properties
5.3.4 Other Properties of Five-Transistor OTA
5.4 Biasing Techniques
5.4.1 CS Biasing
5.4.2 CG Biasing
5.4.3 Source Follower Biasing
5.4.4 Differential Pair Biasing
6 Frequency Response of Amplifiers
6.1 General Considerations
6.1.1 Miller Effect
6.1.2 Association of Poles with Nodes
6.2 Common-Source Stage
6.3 Source Followers
6.4 Common-Gate Stage
6.5 Cascode Stage
6.6 Differential Pair
6.6.1 Differential Pair with Passive Loads
6.6.2 Differential Pair with Active Load
6.7 Gain-Bandwidth Trade-Offs
6.7.1 One-Pole Circuits
6.7.2 Multi-Pole Circuits
6.8 Appendix A: Extra Element Theorem
6.9 Appendix B: Zero-Value Time Constant Method
6.10 Appendix C: Dual of Miller's Theorem
7 Noise
7.1 Statistical Characteristics of Noise
7.1.1 Noise Spectrum
7.1.2 Amplitude Distribution
7.1.3 Correlated and Uncorrelated Sources
7.1.4 Signal-to-Noise Ratio
7.1.5 Noise Analysis Procedure
7.2 Types of Noise
7.2.1 Thermal Noise
7.2.2 Flicker Noise
7.3 Representation of Noise in Circuits
7.4 Noise in Single-Stage Amplifiers
7.4.1 Common-Source Stage
7.4.2 Common-Gate Stage
7.4.3 Source Followers
7.4.4 Cascode Stage
7.5 Noise in Current Mirrors
7.6 Noise in Differential Pairs
7.7 Noise-Power Trade-Off
7.8 Noise Bandwidth
7.9 Problem of Input Noise Integration
7.10 Appendix A: Problem of Noise Correlation
8 Feedback
8.1 General Considerations
8.1.1 Properties of Feedback Circuits
8.1.2 Types of Amplifiers
8.1.3 Sense and Return Mechanisms
8.2 Feedback Topologies
8.2.1 Voltage-Voltage Feedback
8.2.2 Current-Voltage Feedback
8.2.3 Voltage-Current Feedback
8.2.4 Current-Current Feedback
8.3 Effect of Feedback on Noise
8.4 Feedback Analysis Difficulties
8.5 Effect of Loading
8.5.1 Two-Port Network Models
8.5.2 Loading in Voltage-Voltage Feedback
8.5.3 Loading in Current-Voltage Feedback
8.5.4 Loading in Voltage-Current Feedback
8.5.5 Loading in Current-Current Feedback
8.5.6 Summary of Loading Effects
8.6 Bode's Analysis of Feedback Circuits
8.6.1 Observations
8.6.2 Interpretation of Coefficients
8.6.3 Bode's Analysis
8.6.4 Blackman's Impedance Theorem
8.7 Middlebrook's Method
8.8 Loop Gain Calculation Issues
8.8.1 Preliminary Concepts
8.8.2 Difficulties with Return Ratio
8.9 Alternative Interpretations of Bode's Method
9 Operational Amplifiers
9.1 General Considerations
9.1.1 Performance Parameters
9.2 One-Stage Op Amps
9.2.1 Basic Topologies
9.2.2 Design Procedure
9.2.3 Linear Scaling
9.2.4 Folded-Cascode Op Amps
9.2.5 Folded-Cascode Properties
9.2.6 Design Procedure
9.3 Two-Stage Op Amps
9.3.1 Design Procedure
9.4 Gain Boosting
9.4.1 Basic Idea
9.4.2 Circuit Implementation
9.4.3 Frequency Response
9.5 Comparison
9.6 Output Swing Calculations
9.7 Common-Mode Feedback
9.7.1 Basic Concepts
9.7.2 CM Sensing Techniques
9.7.3 CM Feedback Techniques
9.7.4 CMFB in Two-Stage Op Amps
9.8 Input Range Limitations
9.9 Slew Rate
9.10 High-Slew-Rate Op Amps
9.10.1 One-Stage Op Amps
9.10.2 Two-Stage Op Amps
9.11 Power Supply Rejection
9.12 Noise in Op Amps
10 Stability and Frequency Compensation
10.1 General Considerations
10.2 Multipole Systems
10.3 Phase Margin
10.4 Basic Frequency Compensation
10.5 Compensation of Two-Stage Op Amps
10.6 Slewing in Two-Stage Op Amps
10.7 Other Compensation Techniques
10.8 Nyquist's Stability Criterion
10.8.1 Motivation
10.8.2 Basic Concepts
10.8.3 Construction of Polar Plots
10.8.4 Cauchy's Principle
10.8.5 Nyquist's Method
10.8.6 Systems with Poles at Origin
10.8.7 Systems with Multiple 180° Crossings
11 Nanometer Design Studies
11.1 Transistor Design Considerations
11.2 Deep-Submicron Effects
11.3 Transconductance Scaling
11.4 Transistor Design
11.4.1 Design for Given I[sub(D)] and V[sub(DS, min)]
11.4.2 Design for Given g[sub(m)] and I[sub(D)]
11.4.3 Design for Given g[sub(m)] and V[sub(DS, min)]
11.4.4 Design for a Given g[sub(m)]
11.4.5 Choice of Channel Length
11.5 Op Amp Design Examples
11.5.1 Telescopic Op Amp
11.5.2 Two-Stage Op Amp
11.6 High-Speed Amplifier
11.6.1 General Considerations
11.6.2 Op Amp Design
11.6.3 Closed-Loop Small-Signal Performance
11.6.4 Op Amp Scaling
11.6.5 Large-Signal Behavior
11.7 Summary
12 Bandgap References
12.1 General Considerations
12.2 Supply-Independent Biasing
12.3 Temperature-Independent References
12.3.1 Negative-TC Voltage
12.3.2 Positive-TC Voltage
12.3.3 Bandgap Reference
12.4 PTAT Current Generation
12.5 Constant-G[sub(m)] Biasing
12.6 Speed and Noise Issues
12.7 Low-Voltage Bandgap References
12.8 Case Study
13 Introduction to Switched-Capacitor Circuits
13.1 General Considerations
13.2 Sampling Switches
13.2.1 MOSFETS as Switches
13.2.2 Speed Considerations
13.2.3 Precision Considerations
13.2.4 Charge Injection Cancellation
13.3 Switched-Capacitor Amplifiers
13.3.1 Unity-Gain Sampler/Buffer
13.3.2 Noninverting Amplifier
13.3.3 Precision Multiply-by-Two Circuit
13.4 Switched-Capacitor Integrator
13.5 Switched-Capacitor Common-Mode Feedback
14 Nonlinearity and Mismatch
14.1 Nonlinearity
14.1.1 General Considerations
14.1.2 Nonlinearity of Differential Circuits
14.1.3 Effect of Negative Feedback on Nonlinearity
14.1.4 Capacitor Nonlinearity
14.1.5 Nonlinearity in Sampling Circuits
14.1.6 Linearization Techniques
14.2 Mismatch
14.2.1 Effect of Mismatch
14.2.2 Offset Cancellation Techniques
14.2.3 Reduction of Noise by Offset Cancellation
14.2.4 Alternative Definition of CMRR
15 Oscillators
15.1 General Considerations
15.2 Ring Oscillators
15.3 LC Oscillators
15.3.1 Basic Concepts
15.3.2 Cross-Coupled Oscillator
15.3.3 Colpitts Oscillator
15.3.4 One-Port Oscillators
15.4 Voltage-Controlled Oscillators
15.4.1 Tuning in Ring Oscillators
15.4.2 Tuning in LC Oscillators
15.5 Mathematical Model of VCOs
16 Phase-Locked Loops
16.1 Simple PLL
16.1.1 Phase Detector
16.1.2 Basic PLL Topology
16.1.3 Dynamics of Simple PLL
16.2 Charge-Pump PLLs
16.2.1 Problem of Lock Acquisition
16.2.2 Phase/Frequency Detector
16.2.3 Charge Pump
16.2.4 Basic Charge-Pump PLL
16.3 Nonideal Effects in PLLs
16.3.1 PFD/CP Nonidealities
16.3.2 Jitter in PLLs
16.4 Delay-Locked Loops
16.5 Applications
16.5.1 Frequency Multiplication and Synthesis
16.5.2 Skew Reduction
16.5.3 Jitter Reduction
17 Short-Channel Effects and Device Models
17.1 Scaling Theory
17.2 Short-Channel Effects
17.2.1 Threshold Voltage Variation
17.2.2 Mobility Degradation with Vertical Field
17.2.3 Velocity Saturation
17.2.4 Hot Carrier Effects
17.2.5 Output Impedance Variation with Drain-Source Voltage
17.3 MOS Device Models
17.3.1 Level 1 Model
17.3.2 Level 2 Model
17.3.3 Level 3 Model
17.3.4 BSIM Series
17.3.5 Other Models
17.3.6 Charge and Capacitance Modeling
17.3.7 Temperature Dependence
17.4 Process Corners
18 CMOS Processing Technology
18.1 General Considerations
18.2 Wafer Processing
18.3 Photolithography
18.4 Oxidation
18.5 Ion Implantation
18.6 Deposition and Etching
18.7 Device Fabrication
18.7.1 Active Devices
18.7.2 Passive Devices
18.7.3 Interconnects
18.8 Latch-Up
19 Layout and Packaging
19.1 General Layout Considerations
19.1.1 Design Rules
19.1.2 Antenna Effect
19.2 Analog Layout Techniques
19.2.1 Multifinger Transistors
19.2.2 Symmetry
19.2.3 Shallow Trench Isolation Issues
19.2.4 Well Proximity Effects
19.2.5 Reference Distribution
19.2.6 Passive Devices
19.2.7 Interconnects
19.2.8 Pads and ESD Protection
19.3 Substrate Coupling
19.4 Packaging
Index
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
T
U
V
W
T
Z
Design of Analog CMOS
Integrated Circuits
Second Edition
Behzad Razavi
Professor of Electrical Engineering
University of California, Los Angeles
DESIGN OF ANALOG CMOS INTEGRATED CIRCUITS, SECOND EDITION
Published by McGraw-Hill Education, 2 Penn Plaza, New York, NY 10121. Copyright c 2017 by McGraw-Hill
Education. All rights reserved. Printed in the United States of America. Previous edition c 2001. No part of
this publication may be reproduced or distributed in any form or by any means, or stored in a database or
retrieval system, without the prior written consent of McGraw-Hill Education, including, but not limited to, in
any network or other electronic storage or transmission, or broadcast for distance learning
Some ancillaries, including electronic and print components, may not be available to customers outside the
United States.
This book is printed on acid-free paper.
1 2 3 4 5 6 7 8 9 0QVS/QVS 1 0 9 8 7 6
ISBN 978-0-07-252493-2
MHID 0-07-252493-6
Senior Vice President, Products & Markets: Kurt L. Strand
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Compositor: MPS Limited
Printer: Quad/Graphics
All credits appearing on page or at the end of the book are considered to be an extension of the copyright page.
Library of Congress Cataloging-in-Publication Data
Razavi, Behzad.
Design of analog CMOS integrated circuits / Behzad Razavi, professor of electrical engineering,
University of California, Los Angeles. – Second edition.
pages cm
Includes bibliographical references and index.
ISBN 978-0-07-252493-2 (alk. paper) – ISBN 0-07-252493-6 (alk. paper) 1.
Analog CMOS integrated circuits. 2. Linear integrated circuits–Design and
construction. 3. Metal oxide semiconductors, Complementary. I. Title.
TK7874.654.R39 2017
621.3815–dc23
2015035303
The Internet addresses listed in the text were accurate at the time of publication. The inclusion of a website does
not indicate an endorsement by the authors or McGraw-Hill Education, and McGraw-Hill Education does not
guarantee the accuracy of the information presented at these sites.
mheducation.com/highered
To the memory of my parents
Preface to the Second Edition
When I submitted proposals to publishers for the first edition of this book, they posed two questions to
me: (1) What is the future demand for analog books in a digital world? and (2) Is it wise to publish a book
dealing solely with CMOS? The words “analog” and “CMOS” in the book’s title were both in question.
Fortunately, the book resonated with students, instructors, and engineers. It has been adopted by
hundreds of universities around the world, translated to five languages, and cited 6,500 times.
While many fundamentals of analog design have not changed since the first edition was introduced,
several factors have called for a second: migration of CMOS technologies to finer geometries and lower
supply voltages, new approaches to analysis and design, and the need for more detailed treatments of
some topics. This edition provides:
falls short in some common systems
• Greater emphasis on modern CMOS technology, culminating in a new chapter, Chapter 11, on
design methodologies and step-by-step op amp design in nanometer processes
• Extensive study of feedback through the approaches by Bode and Middlebrook
• A new section on the analysis of stability using Nyquist’s approach—as the oft-used Bode method
• Study of FinFETs
• Sidebars highlighting important points in nanometer design
• A new section on biasing techniques
• Study of low-voltage bandgap circuits
• More than 100 new examples
Some instructors ask why we begin with square-law devices. This is for two reasons: (1) such a path
serves as an intuitive entry point and provides considerable value in the analysis of amplifiers in terms of
allowable voltage swings, and (2) despite their very short channel lengths, FinFETs—the devices used
in 16-nm nodes and below—exhibit nearly square-law characteristics.
This book is accompanied with a solutions manual and a new set of PowerPoint slides, available at
www.mhhe.com/razavi.
Behzad Razavi
July 2015
iv
Preface to the Second Edition
Preface to the First Edition
v
In the past two decades, CMOS technology has rapidly embraced the field of analog integrated circuits,
providing low-cost, high-performance solutions and rising to dominate the market. While silicon bipolar
and III-V devices still find niche applications, only CMOS processes have emerged as a viable choice for
the integration of today’s complex mixed-signal systems. With channel lengths projected to scale down
to 0.05 μm, CMOS technology will continue to serve circuit design for another two decades.
Analog circuit design itself has evolved with the technology as well. High-voltage, high-power analog
circuits containing a few tens of transistors and processing small, continuous-time signals have gradually
been replaced by low-voltage, low-power systems comprising thousands of devices and processing large,
mostly discrete-time signals. For example, many analog techniques used only ten years ago have been
abandoned because they do not lend themselves to low-voltage operation.
This book deals with the analysis and design of analog CMOS integrated circuits, emphasizing fun-
damentals as well as new paradigms that students and practicing engineers need to master in today’s
industry. Since analog design requires both intuition and rigor, each concept is first introduced from an
intuitive perspective and subsequently treated by careful analysis. The objective is to develop both a solid
foundation and methods of analyzing circuits by inspection so that the reader learns what approximations
can be made in which circuits and how much error to expect in each approximation. This approach also
enables the reader to apply the concepts to bipolar circuits with little additional effort.
I have taught most of the material in this book both at UCLA and in industry, polishing the order, the
format, and the content with every offering. As the reader will see throughout the book, I follow four
“golden rules” in writing (and teaching): (1) I explain why the reader needs to know the concept that is
to be studied; (2) I put myself in the reader’s position and predict the questions that he/she may have
while reading the material for the first time; (3) With Rule 2 in mind, I pretend to know only as much
as the (first-time) reader and try to “grow” with him/her, thereby experiencing the same thought process;
(4) I begin with the “core” concept in a simple (even imprecise) language and gradually add necessary
modifications to arrive at the final (precise) idea. The last rule is particularly important in teaching circuits
because it allows the reader to observe the evolution of a topology and hence learn both analysis and
synthesis.
The text comprises 16 chapters whose contents and order are carefully chosen to provide a natural
flow for both self-study and classroom adoption in quarter or semester systems. Unlike some other books
on analog design, we cover only a bare minimum of MOS device physics at the beginning, leaving more
advanced properties and fabrication details for later chapters. To an expert, the elementary device physics
treatment my appear oversimplified, but my experience suggests that (a) first-time readers simply do
not absorb the high-order device effects and fabrication technology before they study circuits because
they do not see the relevance; (b) if properly presented, even the simple treatment proves adequate for a
substantial coverage of basic circuits; (c) readers learn advanced device phenomena and processing steps
much more readily after they have been exposed to a significant amount of circuit analysis and design.
Chapter 1 provides the reader with motivation for learning the material in this book. Chapter 2 describes
basic physics and operation of MOS devices.
Chapters 3 through 5 deal with single-stage and differential amplifiers and current mirrors, respectively,
developing efficient analytical tools for quantifying the behavior of basic circuits by inspection.
Chapters 6 and 7 introduce two imperfections of circuits, namely, frequency response and noise. Noise
is treated at an early stage so that it “sinks in” as the reader accounts for its effects in subsequent circuit
developments.
Chapters 8 through 10 describe feedback, operational amplifiers, and stability in feedback sys-
tems, respectively. With the useful properties of feedback analyzed, the reader is motivated to design
high-performance, stable op amps and understand the trade-offs between speed, precision, and power
dissipation.
vi
Preface to the Second Edition
Chapters 11 through 13 deal with more advanced topics: bandgap references, elementary switched-
capacitor circuits, and the effect of nonlinearity and mismatch. These three subjects are included here
because they prove essential in most analog and mixed-signal systems today.
Chapter 14 is concerned with high-order MOS device effects and models, emphasizing the circuit
design implications. If preferred, the chapter can directly follow Chapter 2 as well. Chapter 15 describes
CMOS fabrication technology with a brief overview of layout design rules.
Chapter 16 presents the layout and packaging of analog and mixed-signal circuits. Many practical issues
that directly impact the performance of the circuit are described and various techniques are introduced.
The reader is assumed to have a basic knowledge of electronic circuits and devices, e.g., pn junctions,
the concept of small-signal operation, equivalent circuits, and simple biasing. For a senior-level elective
course, Chapters 1 through 8 can be covered in a quarter and Chapters 1 through 10 in a semester. For a
first-year graduate course, Chapters 1 through 11 plus one of Chapters 12, 13, or 14 can be taught in one
quarter, and almost the entire book in one semester.
The problem sets at the end of each chapter are designed to extend the reader’s understanding of the
material and complement it with additional practical considerations. A solutions manual will be available
for instructors.
Behzad Razavi
July 2000
Acknowledgments for the Second Edition
The second edition was enthusiastically and meticulously reviewed by a large number of individuals in
academia and industry. It is my pleasure to acknowldege their contributions:
Saheed Adeolu Tijani (University of Pavia)
Firooz Aflatouni (University of Pennsylvania)
Pietro Andreani (Lund University)
Emily Allstot (University of Washington)
Tejasvi Anand (University of Illinois, Urbana-Champaign)
Afshin Babveyh (Stanford)
Nima Baniasadi (UC Berkeley)
Sun Yong Cho (Seoul National University)
Min Sung Chu (Seoul National University)
Yi-Ying Cheng (UCLA)
Jeny Chu (UCLA)
Milad Darvishi (Qualcomm)
Luis Fei (Intel)
Andrea Ghilioni (University of Pavia)
Chengkai Gu (UCLA)
Payam Heydari (UC Irvine)
Cheng-En Hsieh (National Taiwan University)
Po-Chiun Huang (National Tsing-Hua University)
Deog-Kyoon Jeong (Seoul National University)
Nader Kalantari (Broadcom)
Preface to the Second Edition
vii
Alireza Karimi (UC Irvine)
Ehsan Kargaran (University of Pavia)
Sotirios Limotyrakis (Qualcomm Atheros)
Xiaodong Liu (Lund University)
Nima Maghari (University of Florida)
Shahriar Mirabbasi (University of British Columbia)
Hossein Mohammadnezhad (UC Irvine)
Amir Nikpaik (University of British Columbia)
Aria Samiei (University of Southern California)
Kia Salimi (IMEC)
Alireza Sharif-Bakhtiar (University of Toronto)
Guanghua Shu (University of Illinois, Urbana-Champaign)
David Su (Qualcomm Atheros)
Siyu Tan (Lund University)
Jeffrey Wang (University of Toronto)
Tzu-Chao Yan (National Chiao-Tung University)
Ehzan Zhian Tabasy (University of Texas A&M)
In addition, my colleague Jason Woo explained to me many subtleties of nanometer devices and their
physics. I wish to thank all.
The production of the book has been in the hands of Heather Ervolino and Vincent Bradshaw of
McGraw-Hill, who tirelessly attended to every detail over a six-month period. I would like to thank both.
Finally, I wish to thank my wife, Angelina, for her continual help with typing and organizing the
chapters.
Acknowledgments for the First Edition
Writing a book begins with a great deal of excitement. However, after two years of relentless writing,
drawing, and revising, when the book exceeds 700 pages and it is almost impossible to make the equations
and subscripts and superscripts in the last chapter consisent with those in the first, the author begins to
feel streaks of insanity, realizing that the book will never finish without the support of many other
people.
This book has benefited from the contributions of many individuals. A number of UCLA students read
the first draft and the preview edition sentence by sentence. In particular, Alireza Zolfaghari, Ellie Cijvat,
and Hamid Rafati meticulously read the book and found several hundred errors (some quite subtle).
Also, Emad Hegazi, Dawei Guo, Alireza Razzaghi, Jafar Savoj, and Jing Tian made helpful suggestions
regarding many chapters. I thank all.
Many experts in academia and industry read various parts of the book and provided useful feedback.
Among them are Brian Brandt (National Semiconductor), Matt Corey (National Semiconductor), Terri
Fiez (Oregon State University), Ian Galton (UC San Diego), Ali Hajimiri (Caltech), Stacy Ho (Analog
Devices), Yin Hu (Texas Instruments), Shen-Iuan Liu (National Taiwan University), Joe Lutsky (National
Semiconductor), Amit Mehrotra (University of Illinois, Urbana-Champaign), David Robertson (Analog
Devices), David Su (T-Span), Tao Sun (National Semiconductor), Robert Taft (National Semiconductor),
and Masoud Zargari (T-Span). Jason Woo (UCLA) patiently endured and answered my questions about
device physics. I thank all.
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