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AXI4用户手册中文版.pdf

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    AMBA AXI and ACE Protocol Specification AXI3, AXI4, and AXI4-Lite ACE and ACE-Lite
    Contents
    Preface
    About this specification
    Intended audience
    Using this specification
    Part A, AMBA AXI3 and AXI4 Protocol Specification
    Part B, AMBA AXI4-Lite Interface Specification
    Part C, ACE Protocol Specification
    Part D, Appendices
    Conventions
    Typographic conventions
    Timing diagrams
    Signals
    Numbers
    Additional reading
    ARM publications
    Feedback
    Feedback on this specification
    Part A: AMBA AXI3 and AXI4 Protocol Specification
    A1: Introduction
    A1.1 About the AXI protocol
    A1.2 AXI revisions
    A1.3 AXI Architecture
    A1.3.1 Channel definition
    A1.3.2 Interface and interconnect
    A1.3.3 Register slices
    A1.4 Terminology
    A1.4.1 AXI components and topology
    A1.4.2 AXI transactions, and memory types
    A1.4.3 Caches and cache operation
    A1.4.4 Temporal description
    A2: Signal Descriptions
    A2.1 Global signals
    A2.2 Write address channel signals
    A2.3 Write data channel signals
    A2.4 Write response channel signals
    A2.5 Read address channel signals
    A2.6 Read data channel signals
    A2.7 Low-power interface signals
    A3: Single Interface Requirements
    A3.1 Clock and reset
    A3.1.1 Clock
    A3.1.2 Reset
    A3.2 Basic read and write transactions
    A3.2.1 Handshake process
    A3.2.2 Channel signaling requirements
    A3.3 Relationships between the channels
    A3.3.1 Dependencies between channel handshake signals
    A3.3.2 Legacy considerations
    A3.4 Transaction structure
    A3.4.1 Address structure
    A3.4.2 Pseudocode description of the transfers
    A3.4.3 Data read and write structure
    A3.4.4 Read and write response structure
    A4: Transaction Attributes
    A4.1 Transaction types and attributes
    A4.2 AXI3 memory attribute signaling
    A4.3 AXI4 changes to memory attribute signaling
    A4.3.1 AxCACHE[1], Modifiable
    A4.3.2 Ordering requirements for Non-modifiable transactions
    A4.3.3 Updated meaning of Read-allocate and Write-allocate
    A4.4 Memory types
    A4.4.1 Memory type requirements
    A4.5 Mismatched memory attributes
    A4.5.1 Changing memory attributes
    A4.6 Transaction buffering
    A4.7 Access permissions
    A4.8 Legacy considerations
    A4.9 Usage examples
    A4.9.1 Use of Device memory types
    A5: Multiple Transactions
    A5.1 AXI transaction identifiers
    A5.2 Transaction ID
    A5.3 Transaction ordering
    A5.3.1 Read ordering
    A5.3.2 Normal write ordering
    A5.3.3 AXI3 write data interleaving
    A5.3.4 Read and write interaction
    A5.3.5 Interconnect use of transaction identifiers
    A5.3.6 Width of transaction ID fields
    A5.4 Removal of write interleaving support
    A5.4.1 Removal of WID
    A5.4.2 Legacy considerations
    A6: AXI4 Ordering Model
    A6.1 Definition of the ordering model
    A6.2 Master ordering
    A6.3 Interconnect ordering
    A6.4 Slave ordering
    A6.5 Response before final destination
    A7: Atomic Accesses
    A7.1 Single-copy atomicity size
    A7.2 Exclusive accesses
    A7.2.1 Exclusive access process
    A7.2.2 Exclusive access from the perspective of the master
    A7.2.3 Exclusive access from the perspective of the slave
    A7.2.4 Exclusive access restrictions
    A7.2.5 Slaves that do not support exclusive access
    A7.3 Locked accesses
    A7.4 Atomic access signaling
    A7.4.1 Legacy considerations
    A8: AXI4 Additional Signaling
    A8.1 QoS signaling
    A8.1.1 QoS interface signals
    A8.1.2 Master considerations
    A8.1.3 System considerations
    A8.2 Multiple region signaling
    A8.2.1 Additional interface signals
    A8.3 User-defined signaling
    A8.3.1 Signal naming
    A8.3.2 Usage considerations
    A9: Low-power Interface
    A9.1 About the low-power interface
    A9.2 Low-power clock control
    A9.2.1 Peripheral clock required
    A9.2.2 Power-down or power-up handshake
    A9.2.3 Acceptance of low-power request
    A9.2.4 Denial of a low-power request
    A9.2.5 Exiting a low-power state
    A9.2.6 Clock control sequence summary
    A9.2.7 Combining peripherals in a low-power domain
    A10: Default Signaling and Interoperability
    A10.1 Interoperability principles
    A10.2 Major interface categories
    A10.2.1 Read/write interface
    A10.2.2 Read-only interface
    A10.2.3 Write-only interface
    A10.2.4 Memory slaves and peripheral slaves
    A10.3 Default signal values
    A10.3.1 Master addresses
    A10.3.2 Slave addresses
    A10.3.3 Memory slaves
    A10.3.4 Write transactions
    A10.3.5 Read transactions
    A10.3.6 Response signaling
    A10.3.7 Non-secure and secure accesses
    Part B: AMBA AXI4-Lite Interface Specification
    B1: AMBA AXI4-Lite
    B1.1 Definition of AXI4-Lite
    B1.1.1 Signal list
    B1.1.2 Bus width
    B1.1.3 Write strobes
    B1.1.4 Optional signaling
    B1.2 Interoperability
    B1.2.1 Bridge requirements of AXI4-Lite slaves
    B1.2.2 Direct connection requirements of AXI4-Lite slaves
    B1.3 Defined conversion mechanism
    B1.3.1 Conversion rules
    B1.4 Conversion, protection, and detection
    B1.4.1 Conversion and protection levels
    B1.4.2 Implementation considerations
    Part C: ACE Protocol Specification
    C1: About ACE
    C1.1 Coherency overview
    C1.1.1 Usage cases
    C1.1.2 ACE terminology
    C1.2 Protocol overview
    C1.2.1 About the ACE protocol
    C1.2.2 Coherency model
    C1.2.3 Cache state model
    C1.3 Channel overview
    C1.3.1 Changes to existing AXI4 channels
    C1.3.2 Additional channels defined by ACE
    C1.3.3 Acknowledge signaling
    C1.3.4 Channel usage examples
    C1.4 Transaction overview
    C1.4.1 Non-snooping transactions
    C1.4.2 Coherent transactions
    C1.4.3 Memory update transactions
    C1.4.4 Cache maintenance transactions
    C1.4.5 Snoop transactions
    C1.4.6 Barrier transactions
    C1.4.7 Distributed virtual memory transactions
    C1.5 Transaction processing
    C1.6 Concepts required for the ACE specification
    C1.6.1 Domains
    C1.6.2 Barriers
    C1.6.3 Distributed Virtual Memory
    C1.7 Protocol errors
    C1.7.1 Software protocol error
    C1.7.2 Hardware protocol error
    C2: Signal Descriptions
    C2.1 Changes to existing AXI4 channels
    C2.1.1 Read address channel (AR) signals
    C2.1.2 Write address channel (AW) signals
    C2.1.3 Read data channel (R) signals
    C2.2 Additional channels defined by ACE
    C2.2.1 Snoop address channel (AC) signals
    C2.2.2 Snoop response channel (CR) signals
    C2.2.3 Snoop data channel (CD) signals
    C2.3 Additional response signals and signaling requirements defined by ACE
    C2.3.1 Read acknowledge signal
    C2.3.2 Write acknowledge signal
    C2.3.3 Additional reset requirements
    C3: Channel Signaling
    C3.1 Read and write address channel signaling
    C3.1.1 Shareability domain types
    C3.1.2 Read and write barrier transactions
    C3.1.3 Read and write shareable transaction types
    C3.1.4 Cache line size restrictions
    C3.1.5 Transaction constraints
    C3.2 Read data channel signaling
    C3.2.1 Read response signaling
    C3.3 Read acknowledge signaling
    C3.4 Write response channel signaling
    C3.5 Write Acknowledge signaling
    C3.6 Snoop address channel signaling
    C3.6.1 About the snoop address channel
    C3.6.2 Snoop address channel signaling
    C3.7 Snoop response channel signaling
    C3.8 Snoop data channel signaling
    C3.9 Snoop channel dependencies
    C4: Coherency Transactions on the Read Address and Write Address Channels
    C4.1 About an initiating master
    C4.1.1 Transaction groups
    C4.2 About snoop filtering
    C4.3 State changes on different transactions
    C4.3.1 State changes associated with a load
    C4.3.2 State changes associated with a coherent store
    C4.3.3 State changes associated with a main memory update
    C4.3.4 State changes associated with cache maintenance operations
    C4.4 State change descriptions
    C4.5 Read transactions
    C4.5.1 ReadNoSnoop
    C4.5.2 ReadOnce
    C4.5.3 ReadClean
    C4.5.4 ReadNotSharedDirty
    C4.5.5 ReadShared
    C4.5.6 ReadUnique
    C4.6 Clean transactions
    C4.6.1 CleanUnique
    C4.6.2 CleanShared
    C4.6.3 CleanInvalid
    C4.7 Make transactions
    C4.7.1 MakeUnique
    C4.7.2 MakeInvalid
    C4.8 Write transactions
    C4.8.1 WriteNoSnoop
    C4.8.2 WriteUnique
    C4.8.3 WriteLineUnique
    C4.8.4 WriteBack
    C4.8.5 WriteClean
    C4.8.6 Restrictions on WriteUnique and WriteLineUnique Usage
    C4.9 Evict transactions
    C4.9.1 Evict
    C4.10 Handling overlapping write transactions
    C4.10.1 Overlapping ReadUnique
    C4.10.2 Overlapping MakeUnique
    C4.10.3 Overlapping CleanUnique
    C5: Snoop Transactions
    C5.1 Mapping coherency operations to snoop operations
    C5.1.1 Permitted snoop transactions
    C5.1.2 Transactions not permitted as snoop transactions
    C5.1.3 Alternative snoop transactions
    C5.2 General requirements for snoop transactions
    C5.2.1 Channel activity
    C5.2.2 Snoop data transfers
    C5.2.3 Memory update in progress
    C5.2.4 WasUnique snoop response
    C5.2.5 Non-blocking requirements for a snooped master
    C5.3 Snoop transactions
    C5.3.1 ReadOnce
    C5.3.2 ReadClean, ReadShared, and ReadNotSharedDirty
    C5.3.3 ReadUnique
    C5.3.4 CleanInvalid
    C5.3.5 MakeInvalid
    C5.3.6 CleanShared
    C6: Interconnect Requirements
    C6.1 About the interconnect requirements
    C6.2 Sequencing transactions
    C6.2.1 Read and Write Acknowledge
    C6.3 Issuing snoop transactions
    C6.4 Transaction responses from the interconnect
    C6.5 Interactions with main memory
    C6.5.1 Interconnect read from main memory or peripheral device
    C6.5.2 Main memory update generated by the interconnect
    C6.5.3 Permission to update main memory
    C6.6 Other requirements
    C6.6.1 Non-blocking requirements
    C6.6.2 Permitted transaction modifications
    C6.6.3 Speculative reads
    C6.7 Interoperability considerations
    C6.7.1 Cache Line size conversions
    C6.7.2 Additional Cache Line conversion considerations
    C6.7.3 Address space size
    C7: Cache Maintenance
    C7.1 ARCACHE and ARDOMAIN requirements
    C7.2 Other cache maintenance considerations
    C7.2.1 Broadcast cache maintenance requirements
    C7.2.2 Requirements for a snooped master
    C7.2.3 Processor cache maintenance instructions
    C7.2.4 Unpredictable behavior with software cache maintenance
    C7.2.5 Mismatched shareability and cacheability
    C8: Barrier Transactions
    C8.1 About barrier transactions
    C8.2 Barrier transaction signaling
    C8.2.1 AxBAR signaling
    C8.2.2 AxDOMAIN signaling
    C8.2.3 Response signaling
    C8.3 Barrier responses and domain boundaries
    C8.4 Barrier requirements
    C8.4.1 Master requirements
    C8.4.2 Slave requirements
    C8.4.3 Interconnect requirements
    C8.4.4 Barriers and Device transaction ordering
    C8.4.5 Multi-copy atomicity requirements for shareable locations
    C9: Exclusive Accesses
    C9.1 About Exclusive accesses
    C9.2 Role of the master
    C9.2.1 Exclusive Load
    C9.2.2 Exclusive Load to Exclusive Store
    C9.2.3 Exclusive Store
    C9.3 Role of the interconnect
    C9.3.1 Minimum PoS Exclusive Monitor
    C9.3.2 Additional address comparison
    C9.3.3 Multiple interconnect PoS monitors
    C9.3.4 PoS Exclusive Monitor behavior
    C9.4 Multiple Exclusive Threads
    C9.5 Exclusive Accesses from AXI components
    C9.6 Transaction requirements
    C10: Optional External Snoop Filtering
    C10.1 About external snoop filtering
    C10.2 Master requirements to support snoop filters
    C10.3 External snoop filter requirements
    C11: ACE-Lite
    C11.1 About ACE-Lite
    C11.2 ACE-Lite signal requirements
    C12: Distributed Virtual Memory Transactions
    C12.1 About DVM transactions
    C12.2 Synchronization message
    C12.3 DVM transaction process and rules
    C12.3.1 DVM Operation process
    C12.3.2 DVM Sync and DVM Complete transactions
    C12.3.3 Multi-part DVM Operation transactions
    C12.3.4 Transaction response
    C12.3.5 Message ID
    C12.3.6 Instruction cache invalidation alternatives
    C12.4 Physical and virtual address space size
    C12.4.1 Physical address space size matches virtual address space size
    C12.4.2 Physical address space size exceeds virtual address space size
    C12.4.3 Virtual address space exceeds physical address space
    C12.5 DVM transactions format
    C12.6 DVM transaction restrictions
    C12.7 DVM Operations
    C12.7.1 TLB Invalidate
    C12.7.2 Branch Predictor Invalidate
    C12.7.3 Physical Instruction Cache Invalidate
    C12.7.4 Virtual Instruction Cache Invalidate
    C12.7.5 Synchronization
    C12.7.6 Hint
    C13: Interface Control
    C13.1 About the interface control signals
    Part D: Appendices
    A: Revisions
    Glossary
    AMBA ® AXI ™ 和ACE ™ 协议 AMBA ® AXI ™ 和ACE ™ 协议 AMBA ® AXI ™ 和ACE ™ 协议 AMBA ® AXI ™ 和ACE ™ 协议 AMBA ® AXI ™ 和ACE ™ 协议 AMBA ® AXI ™ 和ACE ™ 协议 AMBA ® AXI ™ 和ACE ™ 协议 规格 AXI3 ™， AXI4 ™， 和AXI4-精简版 ™ AXI3 ™， AXI4 ™， 和AXI4-精简版 ™ AXI3 ™， AXI4 ™， 和AXI4-精简版 ™ AXI3 ™， AXI4 ™， 和AXI4-精简版 ™ AXI3 ™， AXI4 ™， 和AXI4-精简版 ™ AXI3 ™， AXI4 ™， 和AXI4-精简版 ™ ACE和ACE-精简版 ™ ACE和ACE-精简版 ™ 版权所有©2003，2004，2010，2011 ARM。版权所有。 ARM IHI 0022D（ID102711）
    AMBA AXI和ACE协议规范 AXI3，AXI4和AXI4-精简版ACE和ACE- 精简版 版权所有©2003，2004，2010，2011 ARM。版权所有。 发布信息 以下更改已对此做出规范。 更改历史记录 日期 保密问题 2003 6月16日 一个 非机密 2004年3月19日 2010 03月03日 乙 C 非机密 非机密 更改 首次发行 AXI规范V1.0首次发布 AXI规范v2.0首次发布 2011 6月3日 d-2C 非机密 AMBA AXI和ACE协议规范的公开测试版草案 2011年10月28 d 非机密 AMBA AXI和ACE协议规范的第一个版本 问题B和本文件的Ç包括一个AXI规范版本，v1.0和V2.0。这些版本号已经停产，与AXI的版本，AXI3和AXI4删除混乱。 所有权声明 字和标识标注或已在欧盟和其他国家的商标或ARM的商标，另有规定的本所有权声明在下面说明。此处提及的其他品牌和名称可能是其各自所有者的商标。 无论是整体还是包含在信息，或描述在产品任何部分，这个文件可以被适配或除与版权持有者的书面许可的任何材料形式再现。本文档中描述的产品进行不断的开发和改 进。本文档中包含的产品及其使用的所有特性真诚ARM给出。然而，所有的保证明示或暗示，包括但不限于适销性或适用性的默示担保，被排除在外。 本文仅用于帮助读者在使用该产品。ARM不得用于任何损失或损害本文档中从使用的任何信息而产生的，或在此类信息的任何错误或遗漏，或者任何不正确使用产品的责 任。当使用ARM一词时它表示“ARM或其任何相应的子公司”。ARM AMBA规范许可 本最终用户许可协议（“许可证”）是相关AMBA规范规定本许可证所附的利用你（无论是对个人或单一法律实体）与ARM有限公司（“ARM”）之间的法律协议。ARM只愿 意许可有关AMBA规范TO YOU条件是你接受所有术语将在许可。点击“我同意”或以其他方式使用或复制相关AMBA规范即表示您同意遵守本许可的所有条款。如果您不同 意本许可协议的条款，ARM不愿许可有关AMBA规范您，您不得使用或复制有关AMBA规范您应及时返回相关的AMBA规范的手臂。“方”是指你和你的子公司。 “附属”的意思，如果你是一个单一的实体，任何公司，其表决权股份时，现在或将来拥有或控制的，直接或间接的大部分，由你。公司应当只对在此期间，这种控制存在 的期间是一个子公司。 1.除第2，3和4的规定，ARM此授予被许可永久的，非排他性的，不可转让的，免费使用费，全球许可： （I）使用，复制有关AMBA规范发展，并具有开发的产品，与相关AMBA规范遵守的目的; 二 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 ARM IHI 0022D ID102711
    （ⅱ）制造并且已经制造其中或者产品：（a）已通过或根据在第1条（ⅰ）授予的许可许可人创建的; 或（b）包含已经通过下由ARM在此类第三方的ARM AMBA规格许可条 款1（ⅰ）授予许可证第三方（一个或多个）创建的产物（S）; 和 （ⅲ）提供销售，销售，供应或以其他方式分发的产品，其要么被（a）由下条款1（ⅰ）授予的许可许可人创建的; 或（b）由或为被许可下在第1项目授予的许可制造的 （ⅱ）。 2.许可方同意，在第1项目授予的许可受以下限制：（i）在一个产品根据第1（ⅰ）创建的是集成电路，其包括CPU，那么：（a）该CPU仅须从ARM许可来制造; 或（b） 这样的CPU既不具有基本上符合也不市售为符合由ARM授权不时ARM指令集; （ⅱ）在第1项目授予的许可（ⅲ）不应当延伸到本身不是符合相关AMBA规范的一部分的产物的任何部分或功能; 和 （三）没有权利授予给被许可再许可授予本协议项下向被许可的权利。 3.除按照第1专门许可，许可方获得在任何ARM技术或在其中体现的任何知识产权没有权利，所有权或利益。在任何情况下，按照第1授予的许可被解释为授予被许可人， 明示或暗示，禁止或以其它方式，许可证以使用任何ARM技术除外相关AMBA规范。 4.相关AMBA规范是“按原样”，没有任何明示，暗示或法定的，包括但不限于质量满意，适销性或适用性的担保适用于特定用途。 5.没有许可，明示，暗示或其他，被授予被许可人，根据第1条的规定，使用ARM商品名，或AMBA商标与有关AMBA规格或基于其上的任何产品的连接。在第1条的任何 规定不得解释为授权许可方，使代表ARM的任何陈述就有关AMBA规范。 6.本牌照须继续有效，直至由您或ARM终止。在不损害任何其他权利如果被许可人是在违反任何本协议的条款和条件，那么ARM可以立刻在书面通知您终止本许可证。您 可以随时终止本许可证。在由您或ARM领有许可证到期或本许可证的终止，应当停止使用相关的AMBA规范，并与所有的文件和相关材料一起销毁有关AMBA规范的所有 副本在你的身上。一旦期满或本许可证终止时，第6和第7的规定生存。 7.本协议的效力，解释和履行应受英国法律的管辖。ARM合同引用：LEC-PRE-00490-V4.0 ARM AMBA规范许可。 保密状态 本文档的内容是非保密。使用，复制和公开本文档内容的权利可能会受到按照协议由ARM签订的条款与ARM将本文档交付当事人许可限制。 产品状态 本文档中的信息是最终的，这是开发的产品。 网址 http://www.arm.com ARM IHI 0022D ID102711 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 三
    IV 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 ARM IHI 0022D ID102711
    内容 AMBA AXI和ACE协议规范AXI3，AXI4和AXI4-精简版ACE和ACE-精简 版 A部分 A1章 章A2 前言 有关此规范............................................... ................................................. X 前言 有关此规范............................................... ................................................. X 使用这个规范............................................... ................................................喜约定............................................. ..... .................................................. ..........十三补充阅读..................................... .............................................. .... ............... XV反馈................................. .................................................. ...............................十六 AMBA AXI3和AXI4协议规范 介绍 A1.1 关于AXI协议.............................................. ........................................... A1-20 A1.2 AXI修订................................................ .................................................. ...... A1-21 A1.3 AXI架构................................................ .................................................. 。A1-22 A1.4 术语................................................. .................................................. ...... A1-25 信号说明 A2.1全球信号............................................. .................................................. ....... A2-28 A2.2写地址信道信号..................... ............ ............................................ A2-29 A2.3写数据通道信号.............................................. ..................................... A2 -30 A2.4写响应信道信号... .................................................. ...................... A2-31 A2.5读地址信道信号.................. ............ ...................................... ......... A2-32 A2.6读数据信道信号............................... .................................................. .. A2-33 A 2.7 低功耗接口信号............................................. ................................... A2-34 ARM IHI 0022D ID102711 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 v
    内容 章A3 章A4 章A5 章A6 章A7 章A8 A9章 章A10 B部分 章B1 单接口要求 A3.1时钟和复位............................................ .................................................. ..... A3-36 A3.2 基本的读写交易.............................................在信道之间.......................... A3-37 A3.3关系.............. .................. ................................ ... A3-40 A3.4 交易结构................................................ ........................................... A3-44 事务属性 A4.1 交易类型和属性.............................................. ........................... A4-58 A4.2 AXI3存储属性信号.............................................. ........................... A4-59 A4.3 AXI4更改存储属性信号............................................ ........... A4-60 A4.4存储器类型............................... ........... ....................................... ..................... A4-65 A4.5不匹配的存储属性.................... .................................................. ..... A4 -69 A4.6 交易缓冲................................................ ........................................... A4-70 A4.7 访问权限................................................ ............................................. A4-71 A4。 8 传统的考虑................................................ ......................................... A4-72 A4.9用法的例子。 ....................... ........................... ............................................... A4-73 多笔交易 A5.1 AXI事务标识符............................................... ..................................... A5-76 A5.2 交易ID ................................................ .................................................. ... A5-77 A5.3 交易订货................................................ ........................................... A5-78 A5.4去除的写入交错支持............... ............................... ................... A5-81 AXI4订货模型 排序模型的定义A6.1 .......................................... ................................ A6-84 A6.2主排序.......... ......................................... ......... ....................................... A6-85 A6.3 互连订货................................................ .......................................... A6-86 A6.4 从订货................................................ .................................................. ... A6-87最终目的地之前A6.5响应......... ............................ .................................. A6-88 原子是否访问 A7.1 单拷贝的原子尺寸............................................. ...................................... A7-90 A7.2 独家访问................................................ ............................................. A7-92 A7。 3 锁定访问................................................ ................................................. A7 -95 A7.4 原子接入信令............................................... ....................................... A7-96 AXI4附加信令 A8.1 QoS信令............................................. .................................................. ....... A8-98 A8.2多个区域信号....................... ........... .................................................. .. A8-99 A8.3用户定义的信令...................................... .......................................... ....... A8 -100 低功耗接口 A9.1 关于低功率接口............................................ ............................... A9-102 A9.2 低功耗时钟控制............................................. ....................................... A9-103 默认信令和互操作性 互操作性原则................................................ ................................. A10-110 A10.2主要接口类型........ .............. A10.1 .................................... ..................... A10-111 A10.3缺省信号值.................... .................................................. ................. A10-112 AMBA AXI4-精简版接口规范 AMBA AXI4-精简版 AXI4-精简版的B1.1定义.......................................... .............................................. B1-122 B1 0.2 互操作性................................................. .................................................. B1-124 B1.3定义的转换机制............ ............................. ............................... B1-125 六 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 ARM IHI 0022D ID102711
    C部分 章C1 章C2 章C3 内容 B1.4转换，保护和检测......................................... ...................... B1-127 ACE协议规范 关于ACE C1.1一致性概述............................................. ............................................. C1-132 C1。 2协议概述................................... ............ ................................................ C1- 134 C1.3通道概述............................................ ................................................ .. C1-137 C1.4 交易概述................................................ ......................................... C1-142 C1.5 事务处理 ................................................ ......................................为ACE规范所需C1-146 C1.6概念.................. ................................ ... C1-147 C 1-7协议错误....................................... .................................................. .......... C1-150 信号说明 C2.1更改现有AXI4渠道.......................................... ......................... C2-152 C2.2额外的通道由ACE定义.............. ............. ..................................... .. C2-153 C2.3附加的响应信号和由ACE定义信令要求......... C2-155 信道信令 C3.1读写地址信道信令......................................... ............... C3-158 C3.2读数据信道信令......................... ......................... ......................... ... C3-167 C3.3读取确认信号...................................... ....................................... C3-170 C3.4写响应信道信 令。 .................................................. ................... C3-171 C3.5写入确认信号...................... .............................................. .... ..... C3-172 C 3-6探听地址信道信令................................... ................................... C3-173 C 3-7探听响应信道信令..... . ................................................. ............. C3-176 C 3-8探听的数据信道信令................................................................... ..... .... C3-180 C 3-9探听信道的依赖关系................................ ............................................ C3-182 章C4 在读一致性事务及写入通道 C4.1关于发起主........................................... ....................................... C4-184 C4.2关于探听过滤.. .................................... .............. ......................................在不同的交易C4-187 C4.3状态变化。 .................................................. .......... C4-188 C 4.4状态变化的描述............................... .................................................. 。C4-190 C4.5阅读交易....................................... .. .................................................. ... C4-191 C4.6洁净交易....................................... .................................................. .... C 4-197 C4.7进行交易...................................... .................................................. ...... C4-200 C4。8个写入事务..................... .......................... ............................................... C4-202 C4.9逐出交易............................................. ................................... ............... C4-206 C4.10处理重叠写入交易........................................ .................... C4-207 章C5 章C6 监听事务 C5.1映射一致性操作的窥探操作.........................................对于监听事务C5-210 C5.2一般要求....................................... ... .......... C5-213 C5.3监听事务............................. .................................................. ............. C5-219 互连需求 C6.1关于互联要求........................................... ...................... C6-226 C6.2测序交易.................... ....................................... ........... .............. C6-227 C6.3 发行监听事务............................................... ................................. C6-229 C6.4 从互连事务响应............................................. ....... C6-232 C6.5 与主内存的交互.............................................. ............................ C6-234 C6.6其他要求.............. ...................... ............................ ............................ C6-237 C6.7 互用性考虑................................................ ........................... C6-239 ARM IHI 0022D ID102711 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 七
    内容 章C7 章C8 章C9 章C10 章C11 章C12 章C13 部分d 附录A 高速缓存维护 C7.1 ARCACHE和ARDOMAIN要求........................................... ............ C7-242 C7.2其他高速缓存维护注意事项.............. .............. ............................. C7-243 交易障碍 C8.1关于屏障交易............................................ ..................................... C8-248 C8.2屏障交易信令.... ................................ .................. ........................ C8-249 C8.3壁垒应对和域边界............... ........................................ C8-251 C8.4屏障的要求.. .................................................. ...................................... C8-254 独家是否访问 C9.1关于独家访问............................................ .....................................主的C9-260 C9.2作用... ......................................... ......... ........................................互连的C9-261 C9.3作用.................................................. .................................. C9-263 C9 .4多线程独家....... .................................................. ....................... C9-266 C9.5独家从AXI组件访问................ .................. ..................... C9-267 C9.6 交易要求................................................ .................................. C9-268 可选外部探听过滤 C10.1关于外部探听过滤........................................... ............................... C10-270 C10.2主需求，以支持探听过滤器....... . .......................................... C10-272 C10 3外部探听过滤器要求............................................... .................... C10-273 ACE-精简版 C11.1关于ACE-精简版........................................... .................................................. ... C11-276 C11.2 ACE-精简版信号要 求.................................... ...................................... C11-277 分布式虚拟内存事务 C12.1关于DVM交易............................................ ...................................... C12-280 C12.2同步消息.... ............................... ................... ......................... C12-281 C12.3 DVM交易流程和规则.............. .................................................. C12-282 C12 .4物理和虚拟地址空间的大小...................................... .................... C12-284 C12.5 DVM交易格式..................... ............... ................................... .......... C12-286 C12.6 DVM交易限制............................... ............................................ C12-287 C1 2.7 DVM业务................................................ .............................................. C12-288 接口控制 C13.1关于接口控制信号.......................................... ........................ C13-296 附录 修订词汇表 八 版权所有©2003，2004，2010，2011 ARM。版权所有。 非机密 ARM IHI 0022D ID102711
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