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RTL8367N-CG-DataSheet-1.0.pdf
General Description
Features
System Applications
Application Example
5-Port 1000Base-T Switch
Block Diagram
Pin Assignments
Package Identification
Pin Assignments Table
Pin Descriptions
Media Dependent Interface Pins
LED Pins
Configuration Strapping Pins
Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_
Test Pins
Miscellaneous Pins
Power and GND Pins
Physical Layer Functional Overview
MDI Interface
1000Base-T Transmit Function
1000Base-T Receive Function
100Base-TX Transmit Function
100Base-TX Receive Function
10Base-T Transmit Function
10Base-T Receive Function
Auto-Negotiation for UTP
Crossover Detection and Auto Correction
Polarity Correction
General Function Description
Reset
Hardware Reset
Software Reset
CHIP_RESET
SOFT_RESET
IEEE 802.3x Full Duplex Flow Control
Half Duplex Flow Control
Back-Pressure Mode
Search and Learning
SVL and IVL/SVL
Illegal Frame Filtering
IEEE 802.3 Reserved Group Addresses Filtering Control
Broadcast/Multicast/Unknown DA Storm Control
Port Security Function
MIB Counters
Port Mirroring
VLAN Function
Port-Based VLAN
IEEE 802.1Q Tag-Based VLAN
Protocol-Based VLAN
Port VID
QoS Function
Input Bandwidth Control
Priority Assignment
Priority Queue Scheduling
IEEE 802.1p/Q and DSCP Remarking
ACL-Based Priority
IGMP & MLD Snooping Function
IEEE 802.1x Function
Port-Based Access Control
Authorized Port-Based Access Control
Port-Based Access Control Direction
MAC-Based Access Control
MAC-Based Access Control Direction
Optional Unauthorized Behavior
Guest VLAN
IEEE 802.1D Function
Embedded 8051
Realtek Cable Test (RTCT)
LED Indicators
Green Ethernet
Link-On and Cable Length Power Saving
Link-Down Power Saving
IEEE 802.3az Energy Efficient Ethernet (EEE) Function
Interface Descriptions
EEPROM SMI Host to EEPROM
EEPROM SMI Slave for External CPU
Register Descriptions
PCS Register (PHY 0~4)
Register 0: Control
Register 1: Status
Register 2: PHY Identifier 1
Register 3: PHY Identifier 2
Register 4: Auto-Negotiation Advertisement
Register 5: Auto-Negotiation Link Partner Ability
Register 6: Auto-Negotiation Expansion
Register 7: Auto-Negotiation Page Transmit Register
Register 8: Auto-Negotiation Link Partner Next Page Register
Register 9: 1000Base-T Control Register
Register 10: 1000Base-T Status Register
Register 15: Extended Status
Electrical Characteristics
Absolute Maximum Ratings
Recommended Operating Range
Thermal Characteristics
Assembly Description
Material Properties
Simulation Conditions
Thermal Performance of QFN-88 on PCB Under Still Air Convect
Thermal Performance of QFN-88 on PCB Under Forced Convection
DC Characteristics
AC Characteristics
EEPROM SMI Host Mode Timing Characteristics
EEPROM SMI Slave Mode Timing Characteristics
MDIO Slave Mode Timing Characteristics
Power and Reset Characteristics
Mechanical Dimensions
Mechanical Dimensions Notes
Ordering Information
RTL8367N-CG
SINGLE-CHIP 5-PORT 10/100/1000M
SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.0
05 February 2013
Track ID: JATR-8275-15
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8367N
Datasheet
COPYRIGHT
©2013 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8367N IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
Release Date
2013/02/05
Summary
First release.
Single-Chip 5-Port 10/100/1000M Switch Controller
ii
Track ID: JATR-8275-15 Rev. 1.0
Table of Contents
RTL8367N
Datasheet
4.1.
6.1.
6.2.
8.
9.1.
5.
6.
7.
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
1. GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................3
2.
3.
SYSTEM APPLICATIONS...............................................................................................................................................4
4. APPLICATION EXAMPLE .............................................................................................................................................5
5-PORT 1000BASE-T SWITCH ......................................................................................................................................5
BLOCK DIAGRAM...........................................................................................................................................................6
PIN ASSIGNMENTS .........................................................................................................................................................7
PACKAGE IDENTIFICATION...........................................................................................................................................7
PIN ASSIGNMENTS TABLE............................................................................................................................................8
PIN DESCRIPTIONS.......................................................................................................................................................10
MEDIA DEPENDENT INTERFACE PINS.........................................................................................................................10
LED PINS...................................................................................................................................................................11
CONFIGURATION STRAPPING PINS .............................................................................................................................12
CONFIGURATION STRAPPING PINS (DISAUTOLOAD, DIS_8051, AND EN_SPIF)...................................................13
TEST PINS ..................................................................................................................................................................13
MISCELLANEOUS PINS ...............................................................................................................................................13
POWER AND GND PINS..............................................................................................................................................14
PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................15
MDI INTERFACE ........................................................................................................................................................15
1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................15
1000BASE-T RECEIVE FUNCTION ..............................................................................................................................15
100BASE-TX TRANSMIT FUNCTION...........................................................................................................................15
100BASE-TX RECEIVE FUNCTION .............................................................................................................................16
10BASE-T TRANSMIT FUNCTION ...............................................................................................................................16
10BASE-T RECEIVE FUNCTION ..................................................................................................................................16
AUTO-NEGOTIATION FOR UTP ..................................................................................................................................16
CROSSOVER DETECTION AND AUTO CORRECTION.....................................................................................................17
POLARITY CORRECTION.............................................................................................................................................17
9. GENERAL FUNCTION DESCRIPTION......................................................................................................................18
RESET ........................................................................................................................................................................18
9.1.1. Hardware Reset....................................................................................................................................................18
Software Reset ......................................................................................................................................................18
9.1.2.
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................19
9.2.
HALF DUPLEX FLOW CONTROL .................................................................................................................................19
9.3.
9.3.1. Back-Pressure Mode ............................................................................................................................................19
SEARCH AND LEARNING ............................................................................................................................................20
9.4.
SVL AND IVL/SVL ...................................................................................................................................................20
9.5.
ILLEGAL FRAME FILTERING .......................................................................................................................................20
9.6.
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL.............................................................................21
9.7.
9.8.
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................22
PORT SECURITY FUNCTION........................................................................................................................................22
9.9.
9.10. MIB COUNTERS.........................................................................................................................................................22
9.11.
PORT MIRRORING ......................................................................................................................................................22
9.12. VLAN FUNCTION ......................................................................................................................................................23
Port-Based VLAN ............................................................................................................................................23
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
9.12.1.
Single-Chip 5-Port 10/100/1000M Switch Controller
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Track ID: JATR-8275-15 Rev. 1.0
RTL8367N
Datasheet
9.14.
9.15.
12.
9.20.1.
9.20.2.
9.15.1.
9.15.2.
9.15.3.
9.15.4.
9.15.5.
9.15.6.
9.15.7.
9.12.2.
9.12.3.
9.12.4.
9.13.1.
9.13.2.
9.13.3.
9.13.4.
9.13.5.
IEEE 802.1Q Tag-Based VLAN.......................................................................................................................23
Protocol-Based VLAN .....................................................................................................................................24
Port VID ..........................................................................................................................................................24
9.13. QOS FUNCTION..........................................................................................................................................................25
Input Bandwidth Control .................................................................................................................................25
Priority Assignment .........................................................................................................................................25
Priority Queue Scheduling...............................................................................................................................25
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................26
ACL-Based Priority .........................................................................................................................................26
IGMP & MLD SNOOPING FUNCTION.........................................................................................................................27
IEEE 802.1X FUNCTION.............................................................................................................................................28
Port-Based Access Control..............................................................................................................................28
Authorized Port-Based Access Control ...........................................................................................................28
Port-Based Access Control Direction..............................................................................................................28
MAC-Based Access Control.............................................................................................................................28
MAC-Based Access Control Direction ............................................................................................................28
Optional Unauthorized Behavior.....................................................................................................................29
Guest VLAN .....................................................................................................................................................29
9.16.
IEEE 802.1D FUNCTION ............................................................................................................................................29
EMBEDDED 8051........................................................................................................................................................29
9.17.
9.18. REALTEK CABLE TEST (RTCT) .................................................................................................................................30
9.19.
LED INDICATORS.......................................................................................................................................................30
9.20. GREEN ETHERNET......................................................................................................................................................32
Link-On and Cable Length Power Saving .......................................................................................................32
Link-Down Power Saving ................................................................................................................................32
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ...............................................................................32
INTERFACE DESCRIPTIONS .................................................................................................................................33
EEPROM SMI HOST TO EEPROM ...........................................................................................................................33
EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................34
REGISTER DESCRIPTIONS ....................................................................................................................................35
11.1.
PCS REGISTER (PHY 0~4).........................................................................................................................................35
11.2. REGISTER 0: CONTROL...............................................................................................................................................36
11.3. REGISTER 1: STATUS..................................................................................................................................................37
11.4. REGISTER 2: PHY IDENTIFIER 1.................................................................................................................................38
11.5. REGISTER 3: PHY IDENTIFIER 2.................................................................................................................................38
11.6. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................38
11.7. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................39
11.8. REGISTER 6: AUTO-NEGOTIATION EXPANSION..........................................................................................................40
11.9. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER..................................................................................40
11.10.
REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................41
11.11.
REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................41
11.12.
REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................42
REGISTER 15: EXTENDED STATUS.........................................................................................................................42
11.13.
ELECTRICAL CHARACTERISTICS......................................................................................................................43
12.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................43
12.2. RECOMMENDED OPERATING RANGE..........................................................................................................................43
THERMAL CHARACTERISTICS.....................................................................................................................................44
12.3.
Assembly Description ......................................................................................................................................44
Material Properties .........................................................................................................................................44
Simulation Conditions .....................................................................................................................................44
Thermal Performance of QFN-88 on PCB Under Still Air Convection ..........................................................44
Thermal Performance of QFN-88 on PCB Under Forced Convection............................................................45
12.3.1.
12.3.2.
12.3.3.
12.3.4.
12.3.5.
9.21.
10.1.
10.2.
10.
11.
Single-Chip 5-Port 10/100/1000M Switch Controller
iv
Track ID: JATR-8275-15 Rev. 1.0
RTL8367N
Datasheet
13.
14.
12.5.1.
12.5.2.
12.5.3.
12.4. DC CHARACTERISTICS...............................................................................................................................................45
12.5. AC CHARACTERISTICS...............................................................................................................................................46
EEPROM SMI Host Mode Timing Characteristics .........................................................................................46
EEPROM SMI Slave Mode Timing Characteristics ........................................................................................47
MDIO Slave Mode Timing Characteristics .....................................................................................................48
POWER AND RESET CHARACTERISTICS ......................................................................................................................49
MECHANICAL DIMENSIONS.................................................................................................................................50
13.1. MECHANICAL DIMENSIONS NOTES ............................................................................................................................51
ORDERING INFORMATION...................................................................................................................................51
12.6.
Single-Chip 5-Port 10/100/1000M Switch Controller
v
Track ID: JATR-8275-15 Rev. 1.0
List of Tables
RTL8367N
Datasheet
TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................8
TABLE 2. MEDIA DEPENDENT INTERFACE PINS...........................................................................................................................10
TABLE 3. LED PINS.....................................................................................................................................................................11
TABLE 4. CONFIGURATION STRAPPING PINS................................................................................................................................12
TABLE 5. CONFIGURATION STRAPPING PINS (DISAUTOLOAD, DIS_8051, AND EN_SPIF).....................................................13
TABLE 6. TEST PINS.....................................................................................................................................................................13
TABLE 7. MISCELLANEOUS PINS .................................................................................................................................................13
TABLE 8. POWER AND GND PINS ................................................................................................................................................14
TABLE 9. MEDIA DEPENDENT INTERFACE PIN MAPPING.............................................................................................................17
TABLE 10. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE.........................................................................................21
TABLE 11. IPV4/IPV6 MULTICAST ROUTING PROTOCOLS.............................................................................................................27
TABLE 12. LED DEFINITIONS........................................................................................................................................................30
TABLE 13. PCS REGISTER (PHY 0~4)...........................................................................................................................................35
TABLE 14. REGISTER 0: CONTROL ................................................................................................................................................36
TABLE 15. REGISTER 1: STATUS....................................................................................................................................................37
TABLE 16. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................38
TABLE 17. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................38
TABLE 18. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT...................................................................................................38
TABLE 19. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................39
TABLE 20. REGISTER 6: AUTO-NEGOTIATION EXPANSION............................................................................................................40
TABLE 21. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER....................................................................................40
TABLE 22. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER...................................................................41
TABLE 23. REGISTER 9: 1000BASE-T CONTROL REGISTER...........................................................................................................41
TABLE 24. REGISTER 10: 1000BASE-T STATUS REGISTER............................................................................................................42
TABLE 25. REGISTER 15: EXTENDED STATUS ...............................................................................................................................42
TABLE 26. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................43
TABLE 27. RECOMMENDED OPERATING RANGE ...........................................................................................................................43
TABLE 28. ASSEMBLY DESCRIPTION.............................................................................................................................................44
TABLE 29. MATERIAL PROPERTIES ...............................................................................................................................................44
TABLE 30. SIMULATION CONDITIONS ...........................................................................................................................................44
TABLE 31. THERMAL PERFORMANCE OF QN-88 ON PCB UNDER STILL AIR CONVECTION...........................................................44
TABLE 32. THERMAL PERFORMANCE OF QFN-88 ON PCB UNDER FORCED CONVECTION ...........................................................45
TABLE 33. DC CHARACTERISTICS.................................................................................................................................................45
TABLE 34. EEPROM SMI HOST MODE TIMING CHARACTERISTICS.............................................................................................47
TABLE 35. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ...........................................................................................47
TABLE 36. MDIO TIMING CHARACTERISTICS AND REQUIREMENTS .............................................................................................48
TABLE 37. POWER AND RESET CHARACTERISTICS........................................................................................................................49
TABLE 38. ORDERING INFORMATION ............................................................................................................................................51
Single-Chip 5-Port 10/100/1000M Switch Controller
vi
Track ID: JATR-8275-15 Rev. 1.0
List of Figures
RTL8367N
Datasheet
FIGURE 1. 5-PORT 1000BASE-T SWITCH .......................................................................................................................................5
FIGURE 2. BLOCK DIAGRAM..........................................................................................................................................................6
FIGURE 3. PIN ASSIGNMENTS ........................................................................................................................................................7
FIGURE 4. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION ..................................................................................................17
FIGURE 5. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART..................................................................................24
FIGURE 6. MAX-MIN SCHEDULING DIAGRAM ...........................................................................................................................26
FIGURE 7. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED...........................................................................31
FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED...................................................................................31
FIGURE 9. SMI START AND STOP COMMAND ..............................................................................................................................33
FIGURE 10. EEPROM SMI HOST TO EEPROM............................................................................................................................33
FIGURE 11. EEPROM SMI HOST MODE FRAME...........................................................................................................................33
FIGURE 12. EEPROM SMI WRITE COMMAND FOR SLAVE MODE ................................................................................................34
FIGURE 13. EEPROM SMI READ COMMAND FOR SLAVE MODE..................................................................................................34
FIGURE 14. EEPROM SMI HOST MODE TIMING CHARACTERISTICS............................................................................................46
FIGURE 15. SCK/SDA POWER ON TIMING....................................................................................................................................46
FIGURE 16. EEPROM AUTO-LOAD TIMING..................................................................................................................................46
FIGURE 17. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS..........................................................................................47
FIGURE 18. MDIO SOURCED BY MASTER (RTL8367N LINK PARTNER CPU) ..............................................................................48
FIGURE 19. MDIO SOURCED BY SLAVE (RTL8367N) ..................................................................................................................48
FIGURE 20. POWER AND RESET CHARACTERISTICS.......................................................................................................................49
Single-Chip 5-Port 10/100/1000M Switch Controller
vii
Track ID: JATR-8275-15 Rev. 1.0
RTL8367N
Datasheet
1. General Description
The RTL8367N-CG is a QFN88, high-performance 5-port 10/100/1000M Ethernet switch with an
integrated low-power 5-port Giga-PHY that supports 1000Base-T, 100Base-TX, and 10Base-T.
The RTL8367N integrates all the functions of a high-speed switch system; including SRAM for packet
buffering, non-blocking switch fabric, and internal register management into a single CMOS device. Only
a 25MHz crystal is required; an optional EEPROM is offered for internal register configuration.
The embedded packet storage SRAM in the RTL8367N features superior memory management
technology to efficiently utilize memory space. The RTL8367N integrates a 2K-entry look-up table with a
4-way XOR Hashing algorithm for address searching and learning. The table provides read/write access
from the EEPROM Serial Management Interface (SMI), and each of the entries can be configured as a
static entry. The entry aging time is between 200 and 400 seconds. Eight Filtering Databases are used to
provide Independent VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The RTL8367N supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress.
When using this function, VID information carried in the VLAN tag will be changed to PVID.
The RTL8367N supports standard 802.3x flow control frames for full duplex, and optional backpressure
for half duplex. It determines when to invoke the flow control mechanism by checking the availability of
system resources, including the packet buffers and transmitting queues. The RTL8367N supports
broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-blocked ports
only. For IP multicast applications, the RTL8367N supports IPv4 IGMPv1/v2 and IPv6 MLDv1
snooping.
In order to support flexible traffic classification, the RTL8367N supports 64-entry ACL rule check and
multiple action options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, and rate policing. The rate policing mechanism supports from 8Kbps to 1Gbps (in 8Kbps
steps).
In Bridge operation the RTL8367N supports 16 sets of port configurations: disable, block, learning, and
forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and
management application requirements, the RTL8367N supports IEEE 802.1x Port-based/MAC-based
Access Control. For those ports that do not pass IEEE 802.1x authentication, the RTL8367N provides a
Port-based/MAC-based Guest VLAN function for them to access limited network resources. A 1-set Port
Mirroring function is configured to mirror traffic (RX, TX, or both) appearing on one of the switch’s
ports. Support is provided on each port for multiple RFC MIB Counters, for easy debug and diagnostics.
To improve real-time or multimedia networking applications, the RTL8367N supports eight priority
assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q VLAN tag
priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port supports a
weighted ratio of eight priority queues to fit bandwidth requirements in different applications. The input
bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for average
packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority (SP) or
Weighted Fair Queue (WFQ) or mixed.
Single-Chip 5-Port 10/100/1000M Switch Controller
1
Track ID: JATR-8275-15 Rev. 1.0
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