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Constraining.Designs.for.Synthesis.and.Timing.Analysis.pdf
Foreword
Preface
Book Organization
Conventions Used in This Book
Additional Resources
Feedback
Acknowledgements
Contents
List of Figures
List of Tables
Chapter 1: Introduction
1.1 ASIC Design Flow
1.2 FPGA Design Flow
1.3 Timing Constraints in ASIC and FPGA Flow
1.4 Timing Constraint Issues in Nanometer Design
1.5 Conclusion
Chapter 2: Synthesis Basics
2.1 Synthesis Explained
2.2 Role of Timing Constraints in Synthesis
2.2.1 Optimization
2.2.2 Input Reordering
2.2.3 Input Buffering
2.2.4 Output Buffering
2.3 Commonly Faced Issues During Synthesis
2.3.1 Design Partitioning
2.3.2 Updating Constraints
2.3.3 Multi-clock Designs
2.4 Conclusion
Chapter 3: Timing Analysis and Constraints
3.1 Static Timing Analysis
3.2 Role of Timing Constraints in STA
3.2.1 Constraints as Statements
3.2.2 Constraints as Assertions
3.2.3 Constraints as Directives
3.2.4 Constraints as Exceptions
3.2.5 Changing Role of Constraints
3.3 Common Issues in STA
3.3.1 No Functionality Check
3.3.2 No Check on Statements
3.3.3 Requirements to be Just Right
3.3.4 Common Errors in Constraints
3.3.5 Characteristics of Good Constraints
3.4 Delay Calculation Versus STA
3.5 Timing Paths
3.5.1 Start and End Points
3.5.2 Path Breaking
3.5.3 Functional Versus Timing Paths
3.5.4 Clock and Data Paths
3.6 Setup and Hold
3.6.1 Setup Analysis
3.6.2 Hold Analysis
3.6.3 Other Analysis
3.7 Slack
3.8 On-Chip Variation
3.9 Conclusion
Chapter 4: SDC Extensions Through Tcl
4.1 History of Timing Constraints
4.2 Tcl Basics
4.2.1 Tcl Variables
4.2.2 Tcl Lists
4.2.3 Tcl Expression and Operators
4.2.4 Tcl Control Flow Statements
4.2.4.1 Iterating over Lists
4.2.4.2 Decision Making
4.2.4.3 Tcl Loops
4.2.4.4 Tcl Procedures
4.2.5 Miscellaneous Tcl Commands
4.3 SDC Overview
4.3.1 Constraints for Timing
4.3.2 Constraints for Area and Power
4.3.3 Constraints for Design Rules
4.3.4 Constraints for Interfaces
4.3.5 Constraints for Specific Modes and Configurations
4.3.6 Exceptions to Design Constraints
4.3.7 Miscellaneous Commands
4.4 Design Query in SDC
4.5 SDC as a Standard
4.6 Conclusion
Chapter 5: Clocks
5.1 Clock Period and Frequency
5.2 Clock Edge and Duty Cycle
5.3 create_clock
5.3.1 Specifying Clock Period
5.3.2 Identifying the Clock Source
5.3.3 Naming the Clock
5.3.4 Specifying the Duty Cycle
5.3.5 More than One Clock on the Same Source
5.3.6 Commenting the Clocks
5.4 Virtual Clocks
5.5 Other Clock Characteristics
5.6 Importance of Clock Specification
5.7 Conclusion
Chapter 6: Generated Clocks
6.1 Clock Divider
6.2 Clock Multiplier
6.3 Clock Gating
6.4 create_generated_clock
6.4.1 Defining the Generated Clock Object
6.4.2 Defining the Source of Generated Clock
6.4.3 Naming the Clock
6.4.4 Specifying the Generated Clock Characteristic
6.4.5 Shifting the Edges
6.4.6 More than One Clock on the Same Source
6.4.7 Enabling Combinational Path
6.5 Generated Clock Gotchas
6.6 Conclusion
Chapter 7: Clock Groups
7.1 Setup and Hold Timing Check
7.1.1 Fast to Slow Clocks
7.1.2 Slow to Fast Clocks
7.1.3 Multiple Clocks Where Periods Synchronize in More than Two Cycles
7.1.4 Asynchronous Clocks
7.2 Logically and Physically Exclusive Clocks
7.3 Crosstalk
7.4 set_clock_group
7.5 Clock Group Gotchas
7.6 Conclusion
Chapter 8: Other Clock Characteristics
8.1 Transition Time
8.2 set_clock_transition
8.3 Skew and Jitter
8.4 set_clock_uncertainty
8.4.1 Intraclock Uncertainty
8.4.2 Interclock Uncertainty
8.5 Clock Latency
8.6 set_clock_latency
8.7 Clock Path Unateness
8.8 set_clock_sense
8.9 Ideal Network
8.10 Conclusion
Chapter 9: Port Delays
9.1 Input Availability
9.1.1 Min and Max Availability Time
9.1.2 Multiple Clocks
9.1.3 Understanding Input Arrival Time
9.2 Output Requirement
9.2.1 Min and Max Required Time
9.2.2 Multiple Reference Events
9.2.3 Understanding Output Required Time
9.3 set_input_delay
9.3.1 Clock Specification
9.3.2 -level_sensitive
9.3.3 Rise/Fall Qualifiers
9.3.4 Min/Max Qualifiers
9.3.5 -add_delay
9.3.6 Clock Latency
9.3.7 Completing Input Delay Constraints
9.4 set_output_delay
9.4.1 Clock Specification
9.4.2 -level_sensitive
9.4.3 Rise/Fall Qualifiers
9.4.4 Min/Max Qualifiers
9.4.5 -add_delay
9.4.6 Clock Latency
9.4.7 Completing Output Delay Constraints
9.5 Relationship Among Input and Output Delay
9.6 Example Timing Analysis
9.6.1 Input Delay: Max
9.6.2 Input Delay: Min
9.6.3 Output Delay: Max
9.6.4 Output Delay: Min
9.7 Negative Delays
9.8 Conclusion
Chapter 10: Completing Port Constraints
10.1 Drive Strength
10.1.1 set_drive
10.2 Driving Cell
10.2.1 set_driving_cell
10.2.1.1 Driver Cell Name
10.2.1.2 Min/Max, Rise/Fall
10.2.1.3 Library
10.2.1.4 Pin
10.2.1.5 Timing Arc
10.2.1.6 Multiplication
10.2.1.7 Scaling
10.2.1.8 Design Rules
10.2.1.9 Clock Association
10.2.1.10 Input Transition
10.2.1.11 Ports
10.3 Input Transition
10.3.1 Input Transition Versus Clock Transition
10.4 Fanout Number
10.5 Fanout Load
10.6 Load
10.6.1 Net Capacitance
10.6.2 Pin Load Adjustments
10.6.3 Load Type
10.6.4 Load Versus Fanout Load
10.6.5 Load at Input
10.7 Conclusion
Chapter 11: False Paths
11.1 Introduction
11.2 set_false_path
11.3 Path Specification
11.4 Transition Specification
11.5 Setup/Hold Specification
11.6 Types of False Paths
11.6.1 Combinational False Path
11.6.2 Sequential False Path
11.6.3 Dynamically Sensitized False Path
11.6.4 Timing False Path
11.6.5 False Path Due to Bus Protocol
11.6.6 False Path Between Virtual and Real Clocks
11.7 set_disable_timing
11.8 False Path Gotchas
11.9 Conclusion
Chapter 12: Multi Cycle Paths
12.1 SDC Command for Multi Cycle Paths
12.2 Path and Transition Specification
12.3 Setup/Hold Specification
12.4 Shift Amount
12.5 Example Multi Cycle Specification
12.5.1 FSM-Based Data Transfer
12.5.2 Source Synchronous Interface
12.5.3 Reset
12.5.4 Asynchronous Clocks
12.5.5 Large Data Path Macros
12.5.6 Multimode
12.6 Conclusion
Chapter 13: Combinational Paths
13.1 set_max_delay
13.2 set_min_delay
13.3 Input/Output Delay
13.3.1 Constraining with Unrelated Clock
13.3.2 Constraining with Virtual Clock
13.3.3 Constraining with Related Clock
13.4 Min/Max Delay Versus Input/Output Delay
13.5 Feedthroughs
13.5.1 Feedthroughs Constrained Imperfectly
13.6 Point-to-Point Exception
13.7 Path Breaking
13.8 Conclusion
Chapter 14: Modal Analysis
14.1 Usage Modes
14.2 Multiple Modes
14.3 Single Mode Versus Merged Mode
14.4 Setting Mode
14.5 Other Constraints
14.6 Mode Analysis Challenges
14.6.1 Timing Closure Iterations
14.6.2 Missed Timing Paths
14.7 Conflicting Modes
14.8 Mode Names
14.9 Conclusion
Chapter 15: Managing Your Constraints
15.1 Top-Down Methodology
15.2 Bottom-Up Methodology
15.3 Bottom-Up Top-Down (Hybrid) Methodology
15.4 Multimode Merge
15.4.1 Picking Pessimistic Clock
15.4.2 Mutually Exclusive Clocks
15.4.3 Partially Exclusive Clocks
15.4.4 Merging Functional and Test Mode
15.4.5 Merging I/O Delays for Same Clock
15.4.6 Merging I/O Delays with Different Clocks
15.5 Challenges in Managing the Constraints
15.6 Conclusion
Chapter 16: Miscellaneous SDC Commands
16.1 Operating Condition
16.1.1 Multiple Analysis Conditions
16.1.2 set_operating_conditions
16.1.3 Derating
16.2 Units
16.3 Hierarchy Separator
16.3.1 set_hierarchy_separator
16.3.2 -hsc
16.4 Scope of Design
16.4.1 current_instance
16.5 Wire Load Models
16.5.1 Minimal Size for Wire Load
16.5.2 Wire Load Mode
16.5.3 Wire Load Selection Group
16.6 Area Constraints
16.7 Power Constraints
16.7.1 Voltage Island
16.7.2 Level Shifters
16.7.3 Power Targets
16.8 Conclusion
Chapter 17: XDC: Xilinx Extensions to SDC
17.1 Clocks
17.1.1 Primary and Virtual Clocks
17.1.2 Generated Clocks
17.1.2.1 Tool-Created Generated Clocks
17.1.2.2 Generated Clocks with Nonintegral Ratio
17.1.3 Querying Clocks
17.1.3.1 -of_objects
17.1.3.2 -include_generated_clocks
17.1.4 Clock Groups
17.1.5 Propagated Clocks and Latency
17.1.6 Clock Uncertainty
17.2 Timing Exceptions
17.3 Placement Constraints
17.4 SDC Integration in Xilinx Tcl Shell
17.5 Conclusion
Bibliography
Index
Constraining Designs for Synthesis and Timing Analysis
Sridhar Gangadharan ● Sanjay Churiwala Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC)with Chapter 17 contributed byFrederic Revenu
ISBN 978-1-4614-3268-5 ISBN 978-1-4614-3269-2 (eBook) DOI 10.1007/978-1-4614-3269-2 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2013932651 © Springer Science+Business Media New York 2013 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifi cally the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfi lms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifi cally for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher's location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specifi c statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Sridhar Gangadharan Atrenta, Inc. San Jose , CA , USA Sanjay Churiwala Xilinx Hyderabad, India
v Foreword It has been said that “timing is everything.” While that is certainly true if you’re in show business, the same holds true if you’re designing a system-on-a-chip (SoC). SoCs are powering the hand-held consumer electronics revolution going on all around us. They make things like smart phones and tablets possible. Correct defi ni-tion and management of timing constraints for an SoC are critical tasks. How well these tasks are done will impact the success of the chip project. An SoC is typically a collection of many complex building blocks sourced from multiple suppliers. It is the designer’s job to stitch all these blocks together and achieve the sometimes competing goals of power, performance, and cost for the chip. And all of this happens while the whole team is under tremendous schedule pressure. The fact that so many SoC devices work the fi rst time is nothing short of a miracle. There are many challenges associated with SoC design and many signifi -cant technologies that help make them possible. In the chapters that follow, Sridhar Gangadharan and Sanjay Churiwala take an in-depth look at timing constraints. The broad impact that timing constraints have on the success of an SoC design project is discussed. Many examples are presented for both ASIC and FPGA design paradigms. On the surface, defi ning timing constraints appears to be a straightforward process. It is, in fact, a complex process with many important nuances and interrelationships. Sridhar and Sanjay do an excellent job explaining the process with many relevant examples and detailed “how to” explanations. As designs have grown in complexity, much effort has gone into initiatives focused on improving design effi ciency and managing risk. What is not fully understood is the impact that timing constraints have on both. Poorly managed or incorrect constraints can have signifi cant negative impact on design effort and can lead to a chip failure. The chances of this occurring are growing with every new technology
vinode. I believe that timing constraints are coming upon us as a major area of design challenge, and I congratulate Sridhar and Sanjay for developing such a complete guide for this important topic. I hope you fi nd it useful as well. Dr. Ajoy Bose Chairman, President and CEO, Atrenta Inc. San Jose, CA, USA Foreword
vii Preface Dear Friends, In today’s world of deep submicron, Timing has become a critical challenge for designers developing Application Specifi c Integrated Circuits (ASIC ) or System on a chip (SoC). Design engineers spend many cycles iterating between different stages of the design fl ow to meet the timing requirements. Timing is not merely a response time of a chip, but an integral part of the chip functionality that ensures that it can communicate with other components on a system seamlessly. That begs the ques-tion, what is timing? How do you specify it? This book serves as a hands-on guide to writing and understanding timing con-straints in integrated circuit design. Readers will learn to write their constraints effectively and correctly, in order to achieve the desired performance of their IC or FPGA designs, including considerations around reuse of the constraints. Coverage includes key aspects of the design fl ow impacted by timing constraints, including synthesis, static timing analysis, and placement and routing. Concepts needed for specifying timing requirements are explained in detail and then applied to specifi c stages in the design fl ow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. We have often heard from many design engineers that there are several books explain-ing concepts like Synthesis and Static Timing Analysis which do cover timing constraints, but never in detail. This book is our attempt at explaining the concepts needed for specify-ing timing requirements based on many years of work in the areas of timing characteriza-tion, delay calculation, timing analysis, and constraints creation and verifi cation. Book Organization Here’s how the book is laid out: Chapters 1 , 2 , and 3 introduce the subject of Timing Analysis – including its need in the context of design cycle. The descriptions in these chapters are vendor, language, and format-independent.
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