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Low-Power Design and Power-Aware Verification.pdf

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    Dedication
    Preface
    Acknowledgement
    Contents
    Author Bios
    Chapter 1: Introduction
    Chapter 2: Background
    2.1 The Power Intent
    2.2 The Abstraction of UPF
    Chapter 3: Modeling UPF
    3.1 Fundamental Constructs of UPF
    3.1.1 UPF Power Domain and Domain Boundary
    3.1.2 UPF Power Supply and Supply Networks
    3.1.3 UPF Power States
    3.1.4 UPF Power Strategies
    3.2 Successively Refinable UPF
    3.3 Incrementally Refinable UPF
    3.4 Hierarchical UPF
    Chapter 4: Power Aware Standardization of Library
    4.1 Liberty Power Management Attributes
    4.2 Power Aware Verification Model Libraries
    4.2.1 Non-PA Simulation Model Library
    4.2.2 PA-Simulation Model Library
    4.2.3 Extended-PA-Simulation Model Library
    Chapter 5: UPF Based Power Aware Dynamic Simulation
    5.1 PA Dynamic Verification Techniques
    5.2 PA Dynamic Simulation: Fundamentals
    5.3 PA Dynamic Simulation: Verification Features
    5.4 PA Dynamic Simulation: Verification Practices
    5.5 PA Dynamic Simulation: Library Processing
    5.6 PA Dynamic Simulation: Testbench Requirements
    5.7 PA Dynamic Simulation: Custom PA Checkers and Monitors
    5.8 PA Dynamic Simulation: Post-Synthesis Gate-Level Simulation
    5.9 PA Dynamic Simulation: Simulation Results and Debugging Techniques
    Chapter 6: Power Aware Dynamic Simulation Coverage
    6.1 PA Dynamic Simulation: Coverage Fundamentals
    6.2 PA Dynamic Simulation: Coverage Features
    6.3 PA Dynamic Simulation: Coverage Practices
    6.3.1 Coverage Computation Model: For PA Dynamic Checks
    6.3.2 Coverage Computation Model: For Power States and Power State Transitions
    6.3.3 Autotestplan Generation: From PA Dynamic Checks and Power State Transitions
    6.3.4 Coverage Computation Model: For Cross-Coverage
    Chapter 7: UPF Based Power Aware Static Verification
    7.1 PA Static Checks: Fundamental Techniques
    7.2 PA Static Checks: Verification Features
    7.3 PA Static Checks: Library Processing
    7.4 PA Static Checks: Verification Practices
    7.5 PA Static Checks: Static Checker Results and Debugging Techniques
    Bibliography
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    ProgynaKhondkar Low-Power Design and Power-Aware Veri cation
    Low-Power Design and Power-Aware Verification
    Progyna Khondkar Low-Power Design and Power-Aware Verification
    Progyna Khondkar Design Verification Specialist Mentor Graphics - A Siemens Business Fremont, CA, USA ISBN 978-3-319-66618-1 DOI 10.1007/978-3-319-66619-8 ISBN 978-3-319-66619-8 (eBook) Library of Congress Control Number: 2017951845 © Springer International Publishing AG 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
    “The existence of God is attested by everything that appeals to our imagination. And if our eye cannot reach Him it is because He has not permitted our intelligence to go so far.” Napoleon Bonaparte.
    This Book is Dedicated to My and all Families of the World-
    Preface Low-power (LP) design, power-aware (PA) verification, and Unified Power Format (UPF) or IEEE-1801 power standards are no longer special features. These tech- nologies and methodologies are now part of standard design, verification, and implementation flows (DVIFs). Almost every chip design today incorporates some kind of low-power technique through power management on chip–by dividing the design into different voltage areas and controlling the voltages, through UPF and testbench. Then, the PA dynamic and PA static verification or their combination comes into the play. The entire LP design and PA verification process involves thousands of tech- niques, tools, and methodologies, employed from the register transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of han- dling that complexity by engineers, researchers, and corporate engineering policy makers. However, the industry is missing a complete knowledge base to fully compre- hend LP design and PA verification techniques and methodologies. And deploy them all together in a real design verification and implementation projects. This book, “The Concepts and Fundamentals of Power Aware Verification”, is the first approach to establishing a comprehensive PA knowledge base. Writing an engineering reference book is never an easy task, especially when the perspective is wide, encompassing academic thought and the pragmatic objective of making a reference engineering handbook. The entire effort seeks to bring the com- plex LP design and PA verification process to a complete and one-stop platform – one where engineers will find real examples and results, corporate engineering policy makers will discover ideas for appropriate methodologies to adopt for their next design-verification project, researchers will find topics for new and innovative ideas, and EDA verification experts will be able to enhance and fine tune their tools for the best industry practices. This book is written in a ground up manner with the objective to appeal to a wide range of readers – from beginners to experts in the low power design and power ix
    x Preface aware verification world. However, it is highly recommended that the reader have a solid grasp of HDL (Verilog, SystemVerilog, and VHDL etc.) fundamentals before jumping into this book. This is because UPF directly inherit ports, nets, elements, instances, modules, interfaces, boundaries, hierarchical constructs, scopes, and more from HDL. And obviously, the PA verification artifacts – tools and techniques are founded on the combination of UPF and HDL constructs. San Jose, CA, USA Progyna Khondkar
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