Table of Contents
1 Overview
2 Block Diagram
3 Pin Configuration
3.1 Pin Assignment - PG-VQFN-48
3.2 Pin Definitions and Functions - PG-VQFN-48
3.3 Pin Assignment - PG-LQFP-64
3.4 Pin Definitions and Functions - PG-LQFP-64
4 General Product Characteristics
4.1 Absolute Maximum Ratings
4.2 Functional Range
4.3 Thermal Resistance
4.4 Quiescent Current Consumption
4.4.1 Typical Performance Characteristics
5 Wake Function
5.1 Introduction
5.2 Electrical Characteristics Enable Signal
5.3 Electrical Characteristics Wake Signal
5.4 Typical Performance Characteristics
6 Pre Regulators
6.1 Introduction
6.2 Step Up Regulator
6.2.1 Functional description
6.2.2 Electrical characteristics
6.3 Step Down Regulator
6.3.1 Functional description
6.3.2 Electrical characteristics
6.3.3 Typical Performance Characteristics
6.4 Frequency setting
6.4.1 Introduction
6.4.2 Electrical characteristics frequency setting
6.4.3 Typical Performance Characteristics
7 Post Regulators
7.1 Introduction
7.2 µ-Processor Supply
7.2.1 Functional description
7.2.2 Electrical characteristics
7.2.3 Typical Performance Characteristics
7.3 Communication Supply
7.3.1 Functional description
7.3.2 Electrical characteristics
7.3.3 Typical Performance Characteristics
7.4 Voltage Reference
7.4.1 Functional description
7.4.2 Electrical characteristics
7.4.3 Typical Performance Characteristics
7.5 Tracker 1 & 2
7.5.1 Functional description
7.5.2 Electrical characteristics
7.5.3 Typical Performance Characteristics
7.6 External Post Regulator for Core Supply (optional)
7.7 Power Sequencing
7.7.1 Power sequencing from POR to INIT state
7.7.2 Power sequencing STANDBY to INIT state
7.7.3 Power sequencing SLEEP to WAKE state
8 Monitoring Function
8.1 Introduction
8.2 Shutdown Function
8.3 Reset Function
8.4 Interrupt Function
8.5 Electrical Characteristics Voltage Monitoring and Reset Function
9 Standby LDO and Internal Supplies
9.1 Standby LDO:
9.1.1 Functional description
9.1.2 Electrical characteristics
9.1.3 Typical Performance Characteristics
9.2 Internal Supplies
10 Wake Up Timer
10.1 Description
10.2 Electrical Characteristics
11 State Machine
11.1 Introduction
11.2 Description of States
11.2.1 POWERDOWN-state
11.2.2 INIT-state
11.2.3 NORMAL -state
11.2.4 STANDBY-state
11.2.5 SLEEP-state
11.2.6 WAKE-state
11.2.7 FAILSAFE-state
11.3 Transition Between States
11.3.1 POWERDOWN -> INIT-state
11.3.2 INIT -> NORMAL-state
11.3.3 Movements between NORMAL and SLEEP state
11.3.3.1 NORMAL -> SLEEP-state
11.3.3.2 SLEEP -> WAKE-state
11.3.3.3 WAKE -> SLEEP state
11.3.4 Movements between NORMAL and STANDBY state
11.3.4.1 NORMAL -> STANDBY-state
11.3.4.2 STANDBY -> INIT state
11.3.4.3 INIT -> NORMAL state
11.3.5 NORMAL -> WAKE state
11.3.6 WAKE -> NORMAL-state
11.3.7 WAKE -> STANDBY state
11.3.8 FAILSAFE -> INIT state
11.4 Reaction on detected faults
11.4.1 Stay in current State
11.4.2 Transition into INIT State
11.4.2.1 INIT -> INIT state due to detected fault
11.4.2.2 NORMAL -> INIT state due to detected fault
11.4.2.3 STANDBY -> INIT state due to detected fault
11.4.2.4 SLEEP -> INIT state due to detected fault
11.4.2.5 WAKE -> INIT state due to detected fault
11.4.3 Transition into FAILSAFE State
11.4.3.1 INIT -> FAILSAFE state due to detected fault
11.4.3.2 XXXX -> INIT -> FAILSAFE state due to detected fault
11.4.3.3 NORMAL -> FAILSAFE state due to detected fault
11.4.3.4 STANDBY -> FAILSAFE state due to detected fault
11.4.3.5 SLEEP -> FAILSAFE state due to Fault
11.4.3.6 WAKE -> FAILSAFE state due to detected fault
11.4.3.7 Transition into FAILSAFE state due to thermal shutdown
11.4.4 Transition into POWERDOWN-state
11.5 Electrical Characteristics
11.6 Built In Self Test (BIST) Features
11.6.1 Analog Built In Self Test (ABIST)
11.6.1.1 How to run the ABIST
11.6.1.2 Testing the comparator logic only
11.6.1.3 Testing the comparator logic and the corresponding deglitching logic
11.6.1.4 Testing the complete monitoring chain (comparators, deglitching and output)
11.6.1.5 Abort conditions for ABIST operation
11.6.2 Logic Built In Self Test
11.7 Microcontroller Programming Support
12 Safe State Control Function
12.1 Introduction
12.2 Electrical Characteristics
12.3 Reaction On Microprocessor Safety Management Unit (SMU - Pin ERR):
12.3.1 Immediate reaction on ERR monitoring failure
12.3.2 Recovery delay reaction on ERR monitoring failure
12.4 Reaction On Error Triggered State Transitions
12.5 Reaction On Window Watchdog Output (WWO)
12.6 Reaction On Functional Watchdog Output (FWO)
12.7 Reaction On Thermal Shutdown (TSD)
13 SPI - Serial Peripheral Interface
13.1 Introduction
13.2 SPI Write Access To Protected Registers
13.3 SPI Write Initiated State Transition Request And Regulator Configuration
13.4 Registers Description
13.4.1 Device registers
13.4.2 Buck registers
13.5 Electrical Characteristics
14 Interrupt Generation
15 Window Watchdog And Functional Watchdog
15.1 Introduction
15.2 Window Watchdog
15.2.1 Timing Diagrams
15.2.1.1 Normal operation: Correct triggering
15.2.1.2 Fault operation: No trigger in open window after initialization
15.2.1.3 Fault operation: No trigger in Open Window in steady state
15.2.1.4 Fault operation: False trigger in Closed Window after initialization
15.2.1.5 Fault operation: False trigger in Closed Window in steady state
15.2.2 Electrical characteristics
15.3 Functional Watchdog
15.3.1 Timing Diagrams
15.3.1.1 Normal operation: Correct triggering
15.3.1.2 Fault operation: Synchronization is missing
15.3.1.3 Fault operation: Answer is wrong
15.3.1.4 Fault operation: Missing response
16 Application Information
17 Package Outlines
18 Revision History