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FPGA原型验证方法学.pdf
FPMM eBook Edition
Foreword
The aim of this book
A note from the publisher
The book’s organization
Table of Contents
Chapter 1 Introduction: the challenge of system verification
1.1. Moore was right!
1.1.1. SoC: A definition . . . for this book at least
1.2. The economics of SoC design
1.2.1. Case study: a typical SoC development project
1.3. Virtual platforms: prototyping without hardware
1.3.1. SDK: a very common prototyping environment
1.3.2. FPGA: prototyping in silicon . . . but pre-silicon
1.3.3. Emulators: prototyping or verification?
1.3.4. First silicon as a prototype platform
1.4. Prototyping use models
1.4.1. Prototyping for architecture exploration
1.4.2. Prototyping for software development
1.4.3. Prototyping for verification
1.5. User priorities in prototyping
1.6. Chip design trends
1.6.1. Miniaturization towards smaller technology nodes
1.6.2. Decrease in overall design starts
1.6.3. Increased programmability and software
1.6.4. Intellectual property block reuse
1.6.5. Application specificity and mixed-signal design
1.6.6. Multicore architectures and low power
1.7. Summary
Chapter 2 What can FPGA-based prototyping do for us?
2.1. FPGA-based prototyping for different aims
2.1.1. High performance and accuracy
2.1.2. Real-time dataflow
2.1.3. Hardware-software integration
2.1.4. Modeling an SoC for software development
2.1.5. Example prototype usage for software validation
2.2. Interfacing benefit: test real-world data effects
2.2.1. Example: prototype immersion in real-world data
2.3. Benefits for feasibility lab experiments
2.4. Prototype usage out of the lab
2.4.1. Example: A prototype in the real world
2.5. What can’t FPGA-based prototyping do for us?
2.5.1. An FPGA-based prototype is not a simulator
2.5.2. An FPGA-based prototype is not ESL
2.5.3. Continuity is the key
2.6. Summary: So why use FPGA-based prototyping?
Chapter 3 FPGA technology today: chips and tools
3.1. FPGA device technology today
3.1.1. The Virtex®-6 family: an example of latest FPGAs
3.1.2. FPGA logic blocks
3.1.3. FPGA memory: LUT memory and block memory
3.1.4. FPGA DSP resources
3.1.5. FPGA clocking resources
3.1.5.1. FPGA clock generation
3.1.5.2. FPGA clock distribution
3.1.6. FPGA input and output
3.1.7. Gigabit transceivers
3.1.8. Built-in IP (Ethernet, PCI Express®, CPU etc.)
3.1.9. System monitor
3.1.10. Summary of all FPGA resource types
3.2. FPGA–based Prototyping process overview
3.3. Implementation tools needed during prototyping
3.3.1. Synthesis tools
3.3.2. Mapping SoC design elements into FPGA
3.3.2.1. Logic mapping
3.3.2.2. Memory block mapping
3.3.2.3. DSP block mapping
3.3.3. Synthesis and the three “laws” of prototyping
3.3.4. Gated clock mapping
3.4. Design partitioning flows
3.4.1. Pre-synthesis partitioning flow
3.4.2. Post-synthesis partitioning flow
3.4.3. Alternative netlist-based partitioning flow
3.5. FPGA back-end (place & route) flow
3.5.1. Controlling the back-end
3.5.2. Additional back-end tools
3.6. Debugging tools
3.6.2. Real-time signal probing: test points
3.6.7. Summarizing debugging tool options
Chapter 4 Getting started
4.1. A getting-started checklist
4.2. Estimating the required resources: FPGAs
4.2.3. Design blocks that map outside of the FPGA
4.2.4. How big is an FPGA?
4.2.5. How big is the whole SoC design in FPGA terms?
4.2.6. FPGA resource estimation
4.2.6.1. Size estimates for some familiar SoC blocks
4.2.7. How fast will the prototype run?
4.3. How many FPGAs can be used in one prototype?
4.5. How long will it take to process the design?
4.5.1. Really, how long will it take to process the design?
4.5.2. A note on partitioning runtime
4.6.1. Initial implementation effort
4.6.2. Subsequent implementation effort
4.6.3. A note on engineering resources
Chapter 5 Which platform? (1) build-your-own
5.1. What is the best shape for the platform?
5.1.1. Size and form factor
5.1.2.1. Mother and daughter cards vs. “all-on-board”
5.1.2. Modularity
5.1.3. Interconnect
5.1.4. Flexibility
5.2. Testability
5.3. On-board clock resources
5.3.1. Matching clock delays on and off board
5.3.2. Phase-locked loops (PLL
5.3.3. System clock generation
5.4. Clock control and configuration
5.5. On-board Voltage Domains
5.6. Power supply and distribution
5.6.1. Board-level power distribution
5.6.2. Power distribution physical design considerations
5.7. System reliability management
5.7.1. Power supply monitoring
5.7.2. Temperature monitoring and management
5.7.3. PGA cooling
5.8. FPGA configuration
5.9. Signal integrity
5.10. Global start-up and reset
5.11. Robustness
5.12. Adopting a standard in-house platform
Chapter 6 Which platform? (2) ready-made
6.1. What do you need the board to do?
6.2. Choosing the board(s) to meet your goals
6.3. Flexibility: modularity
6.4. Flexibility: interconnect
6.5. What is the ideal interconnect topology?
6.6. Speed: the effect of interconnect delay
6.6.1. How important is interconnect flight time?
6.7. Speed: quality of design and layout
6.8. On-board support for signal multiplexing
6.9. Cost and robustness
6.9.1. Supply of FPGAs governs delivery of boards
6.10. Capacity
6.11. Summary
Chapter 7 Getting the design ready for the prototype
7.1. Why “get the design ready to prototype?”
7.1.1. RTL modifications for prototyping
7.2. Adapting the design’s top level
7.2.1. Handling the IO pads
7.2.2. Handling top-level chip support elements
Clock gating
7.3.1. Problems of clock gating in FPGA
7.3.2. Converting gated clocks
7.4. Automatic gated-clock conversion
7.4.1. Handling non-convertible gating logic
Clock gating summary
7.5. Selecting a subset of the design for prototyping
7.5.1. SoC block removal and its effect
7.5.2. SoC element tie-off with stubs
7.5.3. Minimizing and localizing RTL changes
7.5.3.1. Note: netlist editing instead of RTL changes
7.5.4. SoC element replacement with equivalent RTL
7.5.5. SoC element replacement by inference
7.5.6. SoC element replacement by instantiation
7.5.7. Controlling inference using directives
7.6. Handling RAMs
7.7. Handling instantiated SoC RAM in FPGA
7.7.1. Note: RAMs in Virtex®-6 FPGAs
7.7.2. Using memory wrappers
7.7.2.1. Wrappers to instantiate equivalent FPGA RAMs
7.7.2.2. Tools for generating replacement memories
7.7.2.3. Wrappers to infer equivalent RAMs
7.7.3. Advanced self-checking wrappers
7.8. Implementing more complex RAMs
7.8.1. Example: implementing multiport RAMs
7.8.2. Example: bit-enabled RAMs
7.8.3. NOTE: using BlockRAM as ROMs
7.9. Design implementation: synthesis
7.9.1. Note: using existing constraints for the SoC design
7.9.2. Tuning constraints
7.10. Prototyping power-saving features
7.11. Design implementation: place & route
7.12. Revision control during prototyping
7.13. Summary
Chapter 8 Partitioning and reconnecting
8.1. Do we always need to partition across FPGAs?
8.1.1. Do we always need EDA partitioning tools?
8.2. General partitioning overview
8.2.1. Recommended approach to partitioning
8.2.2. Describing board resources to the partitioner
8.2.3. Estimate area of each sub-block
8.2.4. Assign SoC top-level IO
8.2.4.1. Note: take care over FPGA IO voltage regions
8.2.5. Assign highly connected blocks
8.2.6. Assign largest blocks
8.2.6.1. Note: help assigning blocks
8.2.7. Assign remaining blocks
8.2.8. Replicate blocks to save IO
8.2.9. Multiplex excessive FPGA interconnect
8.2.10. Assign traces
8.2.10.1. Note: automatic trace assignment
8.2.10.2. Note: trace assignment without EDA tools
8.2.11. Iterate partitioning to improve speed and fit
8.2.11.1. Note: explore non-obvious partitions
8.3. Automated partitioning
8.4. Improving prototype performance
8.4.1. Time budgeting at sequential boundaries
8.4.2. Time budgeting at combinatorial boundaries
8.5. Design synchronization across multiple FPGAs
8.5.1. Multi-FPGA clock synchronization
8.5.2. Multi-FPGA reset synchronization
8.5.3. Multi FPGA start-up synchronization
8.6. More about multiplexing
8.6.1. What do we need for inter-FPGA multiplexing?
8.7. Multiplexing schemes
8.7.1. Schemes based on multiplexer
8.7.2. Note: qualification criteria for multiplexing nets
8.7.3. Schemes based on shift-registers
8.7.4. Worked example of multiplexing
8.7.5. Scheme based on LVDS and IOSERDES
8.7.6. Which multiplexing scheme is best for our design?
8.8. Timing constraints for multiplexing schemes
8.9. Partitioning and reconnection: summary
Chapter 9 Design-for-prototyping
9.1. What is Design-for-Prototyping?
9.1.1. What’s good for FPGA is usually good for SoC
9.2. Procedural guidelines
9.2.1. Integrate RTL team and prototypers
9.2.1.1. Note: FPGA education for SoC RTL team
9.2.2. Define list of deliverables for prototyping team
Reuse file-lists and scripts
9.2.3. Prototypers work with software team
9.3. Integrate the prototype with the verification plan
9.3.1.1. Optimize scheduling of prototype development
9.3.1.2. Keep simulation scripts for prototypers to use
9.3.2. Documentation well and use revision control
9.3.3. Adopt company-wide standard for hardware
9.3.4. Include Design-for-Prototyping in RTL standards
9.4. Design guidelines
9.4.1. Follow modular design principles
9.4.1.1. Create simple modules
9.4.2. Pre-empt RTL changes with ‘define and macros
9.4.3. Avoid latches
9.4.4. Avoid long combinatorial paths
9.4.5. Avoid combinatorial loops
9.4.6. Provide facility to override FFs with constants
9.5. Guidelines for isolating target specificity
9.5.1. Write pure RTL code
9.5.2. Make source changes as low-impact as possible
9.5.3. Maintain memory compatibility
9.5.4. Isolation of RAM and other macros
9.5.4.1. Note: handling RAM in formal verification
9.5.5. Use only IP that has an FPGA version or test chip
9.5.5.1. Note: PHY compatibility
9.6. Clocking and architectural guidelines
9.6.1. Keep clock logic in its own top-level block
9.6.2. Simplify clock networks for FPGA
9.6.3. Design synchronously
9.6.4. Synchronize resets
9.6.5. Synchronize block boundaries
9.6.6. Think how the design might run if clocked slowly
9.6.7. Enable bottom-up design flows
9.7. Summary
Chapter 10 IP and high-speed interfaces
10.1. IP and prototyping
10.2. IP in many forms
10.2.1. IP as RTL source code
10.2.2. What if the RTL is not available?
10.2.3. IP as encrypted source code
10.2.4. Encrypted FPGA netlists
10.2.5. Encrypted FPGA bitstreams
10.2.6. Test chips
10.2.7. Extra FPGA pins needed to link to test chips
10.3. Soft IP
10.3.1. Replacing instantiated soft IP
10.3.2. Replacing inferred soft IP
10.3.3. Replacing synthetic soft IP
10.3.4. Other FPGA replacements for SoC soft IP
10.4. Peripheral IP
10.4.1. Use mode 1: prototype the IP itself
10.4.2. Use mode 2: prototype the IP as part of an SoC
10.4.2.1. Rate adapting between core and peripheral IO
10.4.3. Use mode 3: prototype IP for software validation
10.5. Use of external hard IP during prototyping
10.6. Replacing IP or omitted structures with FPGA IP
10.6.1. External peripheral IP example: PCIe and SATA
10.6.2. Note: speed issues, min-speed
10.7. Summary
Chapter 11 Bring up and debug: the prototype in the lab
11.1. Bring-up and debug–two separate steps?
11.2. Starting point: a fault-free board
11.3. Running test designs
11.3.1. Filter test design for multiple FPGAs
11.3.2. Building a library of bring-up test designs
11.4. Ready to go on board?
11.4.1. Reuse the SoC verification environment
11.4.2. Common FPGA implementation issues
11.4.3. Timing violations
11.4.4. Improper inter-FPGA connectivity
11.4.5. Improper connectivity to the outside world
11.4.6. Incorrect FPGA IO pad configuration
11.5.1. Note: incorrect startup state for multiple FPGAs
11.6. Debugging on-board issues
11.6.1. Sources of faults
11.6.2. Logical design issues
11.6.3. Logic debug visibility
11.6.4. Bus-based design access and instrumentation
11.6.5. Benefits of a bus-based access system
11.6.6. Custom debug using an embedded CPU
11.7. Note: use different techniques during debug
11.8. Other general tips for debug
11.9. Quick turn-around after fixing bugs
11.9.1. Incremental synthesis flow
11.9.2. Automation and parallel synthesis
11.9.3. Incremental place & route flow
11.9.4. Combined incremental synthesis and P&R flow
11.10. A bring-up and debug checklist
11.11. Summary
Chapter 12 Breaking out of the lab: the prototype in the field
12.1. The uses and benefits of a portable prototype
12.2. Planning for portability
12.2.1. Main board physical stiffness
12.2.2. Daughter board mounting
12.2.4. Main board connectors
12.2.5. Enclosure
12.2.6. Cooling
12.2.7. Look and feel
12.2.8. Summary
Chapter 13 Prototyping + Verirfication = The Best of Both Worlds
13.1. System prototypes
13.2. Required effort
13.3. Hybrid verification scenarios
13.4. Verification interfaces
13.4.1. Interfaces for co-simulation
13.4.1.1. Example: HDL Bridge
13.4.2. Interfaces for transaction-based verification
13.4.3. TLMs and transactors
13.4.4. SCE-MI
13.4.5. SCE-MI 2.0 implementation example
13.4.6. VMM HAL
13.4.7. Physical interfaces for co-verification
13.5. Comparing verification interface technologies
13.6. Use models – more detail
13.6.1. Virtual platform re-using existing RTL
13.7. Virtual platform for software
13.7.1. Virtual platform as a testbench
13.7.2. Virtual and physical IO (system IO)
13.7.3. Virtual ICE
13.8. System partitioning
13.9. Case study: USB OTG
13.9.1. USB OTG System overview
13.9.2. Integration use models
13.9.3. Innovator and VCS
13.9.4. Innovator and CHIPit or HAPS
13.9.5. Virtual platform
Chapter 14 The future of prototyping
14.1. If prediction were easy. . .
14.2. Application specificity
14.3. Prototyping future: mobile wireless and consumer
14.4. Prototyping future: networking
14.5. Prototyping future: automotive
14.6. Summary: software-driven hardware development
14.7. Future semiconductor trends
14.8. The FPGA’s future as a prototyping platform
14.9. Summary
Chapter 15 Conclusions
15.1. The FPMM approach to FPGA-based prototyping
15.2. SoCs are larger than FPGAs
15.3. SoCs are faster than FPGAs
15.4. SoCs designs are FPGA-hostile
15.5. Design-for-Prototyping beats the three laws
15.6. So, what did we learn?
APPENDIX A Worked example: Texas Instruments
A1. Design background: packet processing sub-system
A2. Why does Texas Instruments do prototyping?
A3. Testing the design using an FPGA-based prototype
A4. Implementation details
A5. High-speed scenario
A6. Low-speed scenario
A7. Interesting challenges
Summary of results
APPENDIX B Economics of making prototype boards
B1. Prototyping hardware: should we make or buy?
B2. Cost: what is the total cost of a prototyping board?
B3. Direct cost: personnel
B4. Direct cost: equipment and expertise
B5. Direct cost: material and components
B6. Direct cost: yield and wastage
B7. Direct cost: support and documentation
B8. Business cost: time
B9. Business cost: risk
B10. Business cost: opportunity
B11. CCS worked example results
B12. Summary
References and Bibliography
Acknowledgements
Figure Sources
Glossary of key terms
Index
About the authors
About Synopsys Press
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EBOOK EDITION OF THE FPMM
This copy of the electronic edition of the FPGA-Based
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FPGA-Based
Prototyping
Methodology
Manual
Best Practices in Design-for-Prototyping
Doug Amos
Synopsys, Inc.
Austin Lesea
Xilinx, Inc.
René Richter
Synopsys, Inc.
Registered Copy - Do Not DistributeRegistered eBook Copy
Austin Lesea
Xilinx, Inc.
San Jose, CA
USA
Doug Amos
Synopsys, Inc.
Reading
United Kingdom
René Richter
Synopsys, Inc.
Erfurt
Germany
Library of Congress Control Number: 2011920198
Hardcover ISBN 978-1-61730-003-5
Paperback ISBN 978-1-61730-004-2
eBook ISBN 978-1-61730-005-9
Copyright © 2011 Synopsys, Inc. All rights reserved.
Portions Copyright© 2009-2011 Xilinx, Inc. Used by permission.
Portions Copyright© 2011 ARM Limited. Used by permission.
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Published by Synopsys, Inc., Mountain View, CA, USA
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HapsTrak, Identify, Synplicity, Synplify, Synplify Pro, and VCS are registered trademarks or
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