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IEEE Std 802.3cd-2018.pdf
IEEE Std 802.3cd™-2018 front cover
Title page
Important Notices and Disclaimers Concerning IEEE Standards Documents
Participants
Introduction
Contents
1. Introduction
1.1 Overview
1.1.3 Architectural perspectives
1.1.3.2 Compatibility interfaces
1.3 Normative references
1.4 Definitions
1.5 Abbreviations
4. Media Access Control
4.4 Specific implementations
4.4.2 MAC parameters
30. Management
30.3 Layer management for DTEs
30.3.2 PHY device managed object class
30.3.2.1 PHY device attributes
30.3.2.1.2 aPhyType
30.3.2.1.3 aPhyTypeList
30.3.2.1.5 aSymbolErrorDuringCarrier
30.5 Layer management for medium attachment units (MAUs)
30.5.1 MAU managed object class
30.5.1.1 MAU attributes
30.5.1.1.2 aMAUType
30.5.1.1.4 aMediaAvailable
30.5.1.1.11 aBIPErrorCount
30.5.1.1.12 aLaneMapping
30.5.1.1.17 aFECCorrectedBlocks
30.5.1.1.18 aFECUncorrectableBlocks
30.5.1.1.26 aRSFECBIPErrorCount
30.5.1.1.27 aRSFECLaneMapping
30.5.1.1.29 aRSFECBypassIndicationAbility
30.5.1.1.31 aRSFECBypassIndicationEnable
30.6 Management for link Auto-Negotiation
30.6.1 Auto-Negotiation managed object class
30.6.1.1 Auto-Negotiation attributes
30.6.1.1.5 aAutoNegLocalTechnologyAbility
45. Management Data Input/Output (MDIO) Interface
45.2 MDIO Interface Registers
45.2.1 PMA/PMD registers
45.2.1.1 PMA/PMD control 1 register (Register 1.0)
45.2.1.1.3 Speed selection (1.0.13, 1.0.6, 1.0.5:2)
45.2.1.2 PMA/PMD status 1 register (Register 1.1)
45.2.1.2.3 Fault (1.1.7)
45.2.1.4 PMA/PMD speed ability (Register 1.4)
45.2.1.4.12a 50G capable (1.4.3)
45.2.1.6 PMA/PMD control 2 register (Register 1.7)
45.2.1.6.3 PMA/PMD type selection (1.7.6:0)
45.2.1.7 PMA/PMD status 2 register (Register 1.8)
45.2.1.7.4 Transmit fault (1.8.11)
45.2.1.7.5 Receive fault (1.8.10)
45.2.1.8 PMD transmit disable register (Register 1.9)
45.2.1.17a 50G PMA/PMD extended ability (Register 1.20)
45.2.1.17a.1 50G PMA remote loopback ability (1.20.15)
45.2.1.17a.2 50GBASE-LR ability (1.20.4)
45.2.1.17a.3 50GBASE-FR ability (1.20.3)
45.2.1.17a.4 50GBASE-SR ability (1.20.2)
45.2.1.17a.5 50GBASE-CR ability (1.20.1)
45.2.1.17a.6 50GBASE-KR ability (1.20.0)
45.2.1.21a PMA/PMD extended ability 2 (Register 1.25)
45.2.1.21a.1 50G extended abilities (1.25.0)
45.2.1.89 BASE-R PMD control register (Register 1.150)
45.2.1.90 BASE-R PMD status register (Register 1.151)
45.2.1.90.1 Receiver status 0 (1.151.0)
45.2.1.90.2 Frame lock 0 (1.151.1)
45.2.1.90.3 Start-up protocol status 0 (1.151.2)
45.2.1.90.4 Training failure 0 (1.151.3)
45.2.1.110 RS-FEC control register (Register 1.200)
45.2.1.110.a FEC degraded SER enable (1.200.4)
45.2.1.110.b Four-lane PMD (1.200.3)
45.2.1.110.2 FEC bypass indication enable (1.200.1)
45.2.1.111 RS-FEC status register (Register 1.201)
45.2.1.111.1 PCS align status (1.201.15)
45.2.1.111.2 RS-FEC align status (1.201.14)
45.2.1.111.5 FEC AM lock 1 (1.201.9)
45.2.1.111.6 FEC AM lock 0 (1.201.8)
45.2.1.111.7a FEC degraded SER (1.201.4)
45.2.1.111.7b FEC degraded SER ability (1.201.3)
45.2.1.111.8 RS-FEC high SER (1.201.2)
45.2.1.111.9 FEC bypass indication ability (1.201.1)
45.2.1.117 RS-FEC BIP error counter lane 0 (Register 1.230)
45.2.1.129 50GAUI-n, 100GAUI-2, 200GAUI-n, and 400GAUI-n chip-to-chip transmitter equalization, receive direction, lane 0 register (Register 1.500)
45.2.1.129.1 Request flag (1.500.15)
45.2.1.129.2 Post-cursor request (1.500.14:12)
45.2.1.129.3 Pre-cursor request (1.500.11:10)
45.2.1.129.4 Post-cursor remote setting (1.500.9:7)
45.2.1.129.5 Pre-cursor remote setting (1.500.6:5)
45.2.1.129.6 Post-cursor local setting (1.500.4:2)
45.2.1.129.7 Pre-cursor local setting (1.500.1:0)
45.2.1.130 50GAUI-n, 100GAUI-2, 200GAUI-n, and 400GAUI-n chip-to-chip transmitter equalization, receive direction, lane 1 through lane 15 registers (Registers 1.501 through 1.515)
45.2.1.131 50GAUI-n, 100GAUI-2, 200GAUI-n, and 400GAUI-n chip-to-chip transmitter equalization, transmit direction, lane 0 register (Register 1.516)
45.2.1.131.1 Request flag (1.516.15)
45.2.1.131.2 Post-cursor request (1.516.14:12)
45.2.1.131.3 Pre-cursor request (1.516.11:10)
45.2.1.131.4 Post-cursor remote setting (1.516.9:7)
45.2.1.131.5 Pre-cursor remote setting (1.516.6:5)
45.2.1.131.6 Post-cursor local setting (1.516.4:2)
45.2.1.131.7 Pre-cursor local setting (1.516.1:0)
45.2.1.132 50GAUI-n, 100GAUI-2, 200GAUI-n, and 400GAUI-n chip-to-chip transmitter equalization, transmit direction, lane 1 through lane 15 registers (Registers 1.517 through 1.531)
45.2.1.132a PMA precoder control Tx output (Register 1.600)
45.2.1.132a.1 Lane 3 Tx output precoder enable (1.600.3)
45.2.1.132a.2 Lane 2 Tx output precoder enable (1.600.2)
45.2.1.132a.3 Lane 1 Tx output precoder enable (1.600.1)
45.2.1.132a.4 Lane 0 Tx output precoder enable (1.600.0)
45.2.1.132b PMA precoder control Rx input (Register 1.601)
45.2.1.132b.1 Lane 3 Rx input precoder enable (1.601.3)
45.2.1.132b.2 Lane 2 Rx input precoder enable (1.601.2)
45.2.1.132b.3 Lane 1 Rx input precoder enable (1.601.1)
45.2.1.132b.4 Lane 0 Rx input precoder enable (1.601.0)
45.2.1.132c PMA precoder control Rx output (Register 1.602)
45.2.1.132c.1 Lane 1 Rx output precoder enable (1.602.1)
45.2.1.132c.2 Lane 0 Rx output precoder enable (1.602.0)
45.2.1.132d PMA precoder control Tx input (Register 1.603)
45.2.1.132d.1 Lane 1 Tx input precoder enable (1.603.1)
45.2.1.132d.2 Lane 0 Tx input precoder enable (1.603.0)
45.2.1.132e PMA precoder request flag (Register 1.604)
45.2.1.132e.1 Tx input precoder request flag (1.604.1)
45.2.1.132e.2 Rx input precoder request flag (1.604.0)
45.2.1.132f PMA precoder request Rx input status (Register 1.605)
45.2.1.132f.1 Lane 1 Rx input precoder request status (1.605.1)
45.2.1.132f.2 Lane 0 Rx input precoder request status (1.605.0)
45.2.1.132g PMA precoder request Tx input status (Register 1.606)
45.2.1.132g.1 Lane 1 Tx input precoder request status(1.606.1)
45.2.1.132g.2 Lane 0 Tx input precoder request status (1.606.0)
45.2.1.132h RS-FEC degraded SER activate threshold register (Register 1.650, 1.651)
45.2.1.132i RS-FEC degraded SER deactivate threshold register (Register 1.652, 1.653)
45.2.1.132j RS-FEC degraded SER interval register (Register 1.654, 1.655)
45.2.1.135a BASE-R PAM4 PMD training LP control, lane 0 through lane 3 registers (Register 1.1120 through 1.1123)
45.2.1.136a BASE-R PAM4 PMD training LP status, lane 0 through lane 3 registers (Register 1.1220 through 1.1223)
45.2.1.137a BASE-R PAM4 PMD training LD control, lane 0 through lane 3 registers (Register 1.1320 through 1.1323)
45.2.1.138a BASE-R PAM4 PMD training LD status, lane 0 through lane 3 registers (Register 1.1420 through 1.1423)
45.2.1.139 PMD training pattern lanes 0 through 3 (Register 1.1450 through 1.1453)
45.2.1.141 PRBS pattern testing control (Register 1.1501)
45.2.3 PCS registers
45.2.3.1 PCS control 1 register (Register 3.0)
45.2.3.2 PCS status 1 register (Register 3.1)
45.2.3.2.7 PCS receive link status (3.1.2)
45.2.3.4 PCS speed ability (Register 3.4)
45.2.3.4.5a 50G capable (3.4.5)
45.2.3.6 PCS control 2 register (Register 3.7)
45.2.3.7 PCS status 2 register (Register 3.8)
45.2.3.7.6a 50GBASE-R capable (3.8.8)
45.2.3.10 EEE control and capability 1 (Register 3.20)
45.2.3.10.a 50GBASE-R EEE fast wake supported (3.20.14)
45.2.3.15 BASE-R and MultiGBASE-T PCS status 1 register (Register 3.32)
45.2.3.15.1 BASE-R and MultiGBASE-T receive link status (3.32.12)
45.2.3.15.4 BASE-R and MultiGBASE-T PCS high BER (3.32.1)
45.2.3.15.5 BASE-R and MultiGBASE-T PCS block lock (3.32.0)
45.2.3.16 BASE-R and MultiGBASE-T PCS status 2 register (Register 3.33)
45.2.3.16.1 Latched block lock (3.33.15)
45.2.3.16.2 Latched high BER (3.33.14)
45.2.3.16.3 BER (3.33.13:8)
45.2.3.16.4 Errored blocks (3.33.7:0)
45.2.3.19 BASE-R PCS test-pattern control register (Register 3.42)
45.2.7 Auto-Negotiation registers
45.2.7.12 Backplane Ethernet, BASE-R copper status (Register 7.48)
45.2.7.12.3 Negotiated Port Type (7.48.1, 7.48.2, 7.48.3, 7.48.5, 7.48.6, 7.48.8, 7.48.9, 7.48.10, 7.48.11, 7.48.12, 7.48.13, 7.48.14, 7.48.15, 7.49.0, 7.49.1, 7.49.2)
45.2.7.12a Backplane Ethernet, BASE-R copper status 2 (Register 7.49)
45.2.7.12a.1 Negotiated Port Type
69. Introduction to Ethernet operation over electrical backplanes
69.1 Overview
69.1.1 Scope
69.1.2 Relationship of Backplane Ethernet to the ISO OSI reference model
69.2 Summary of Backplane Ethernet Sublayers
69.2.1 Reconciliation sublayer and media independent interfaces
69.2.3 Physical Layer signaling systems
69.3 Delay constraints
69.5 Protocol implementation conformance statement (PICS) proforma
73. Auto-Negotiation for backplane and copper cable assembly
73.2 Relationship to the ISO/IEC Open Systems Interconnection (OSI) reference model
73.5 DME transmission
73.5.1 DME electrical specifications
73.6 Link codeword encoding
73.6.4 Technology Ability Field
73.7 Receive function requirements
73.7.6 Priority Resolution function
73.10 State diagrams and variable definitions
73.10.1 State diagram variables
73.10.2 State diagram timers
78. Energy-Efficient Ethernet (EEE)
78.1 Overview
78.1.4 PHY types optionally supporting EEE
78.5 Communication link access latency
80. Introduction to 40 Gb/s and 100 Gb/s networks
80.1 Overview
80.1.3 Relationship of 40 Gigabit and 100 Gigabit Ethernet to the ISO OSI reference model
80.1.4 Nomenclature
80.1.5 Physical Layer signaling systems
80.2 Summary of 40 Gigabit and 100 Gigabit Ethernet sublayers
80.2.2 Physical Coding Sublayer (PCS)
80.2.3 Forward Error Correction (FEC) sublayers
80.2.4 Physical Medium Attachment (PMA) sublayer
80.2.5 Physical Medium Dependent (PMD) sublayer
80.2.6 Auto-Negotiation
80.4 Delay constraints
80.5 Skew constraints
80.7 Protocol implementation conformance statement (PICS) proforma
82. Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R
82.6 Auto-Negotiation
82.7 Protocol implementation conformance statement (PICS) proforma for Clause 82, Physical Coding Sublayer (PCS) for 64B/66B, type 40GBASE-R and 100GBASE-R
82.7.4 PICS proforma tables for PCS, type 40GBASE-R and 100GBASE-R
82.7.4.11 Auto-Negotiation for Backplane Ethernet functions
90. Ethernet support for time synchronization protocols
90.1 Introduction
91. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.3 PMA compatibility
91.5 Functions within the RS-FEC sublayer
91.5.2 Transmit function
91.5.2.6 Alignment marker mapping and insertion
91.5.2.7 Reed-Solomon encoder
91.5.3 Receive function
91.5.3.3 Reed-Solomon decoder
91.5.3.3.1 FEC Degraded SER (optional)
91.6 RS-FEC MDIO function mapping
91.6.2a four_lane_pmd
91.6.2b FEC_degraded_SER_enable
91.6.2c FEC_degraded_SER_activate_threshold
91.6.2d FEC_degraded_SER_deactivate_threshold
91.6.2e FEC_degraded_SER_interval
91.6.5a FEC_degraded_SER_ability
91.6.5b FEC_degraded_SER
91.7 Protocol implementation conformance statement (PICS) proforma for Clause 91, Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.7.3 Major capabilities/options
91.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 100GBASE-R PHYs
91.7.4.1 Transmit function
91.7.4.2 Receive function
116. Introduction to 200 Gb/s and 400 Gb/s networks
116.1 Overview
116.1.2 Relationship of 200 Gigabit and 400 Gigabit Ethernet to the ISO OSI reference model
116.1.3 Nomenclature
116.1.4 Physical Layer signaling systems
116.2 Summary of 200 Gigabit and 400 Gigabit Ethernet sublayers
116.2.5 Physical Medium Dependent (PMD) sublayer
116.4 Delay constraints
119. Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R
119.5a Auto-Negotiation
119.6 Protocol implementation conformance statement (PICS) proforma for Clause 119, Physical Coding Sublayer (PCS) for 64B/66B, type 200GBASE-R and 400GBASE-R
119.6.4 PICS proforma tables for Physical Coding Sublayer (PCS) 64B/66B, type 200GBASE-R and 400GBASE-R
119.6.4.12 Auto-Negotiation for Backplane Ethernet functions
120. Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R
120.5 Functions within the PMA
120.5.7 PAM4 Encoding Gray mapping for PAM4 encoded lanes
120.5.7.1 Gray mapping for PAM4 encoded lanes
120.5.7.2 Precoding for PAM4 encoded lanes
120.6 PMA MDIO function mapping
120.7 Protocol implementation conformance statement (PICS) proforma for Clause 120, Physical Medium Attachment (PMA) sublayer, type 200GBASE-R and 400GBASE-R
120.7.7 Encoding
131. Introduction to 50 Gb/s networks
131.1 Overview
131.1.1 Scope
131.1.2 Relationship of 50 Gigabit Ethernet to the ISO OSI reference model
131.1.3 Nomenclature
131.1.4 Physical Layer signaling systems
131.2 Summary of 50 Gigabit Ethernet sublayers
131.2.1 Reconciliation Sublayer (RS) and Media Independent Interface (50GMII)
131.2.2 Physical Coding Sublayer (PCS)
131.2.3 Forward Error Correction (FEC) sublayer
131.2.4 Physical Medium Attachment (PMA) sublayer
131.2.5 Physical Medium Dependent (PMD) sublayer
131.2.6 Management interface (MDIO/MDC)
131.2.7 Management
131.3 Service interface specification method and notation
131.3.1 Inter-sublayer service interface
131.3.2 Instances of the Inter-sublayer service interface
131.3.3 Semantics of inter-sublayer service interface primitives
131.4 Delay constraints
131.5 Skew constraints
131.6 State diagrams
131.7 Protocol implementation conformance statement (PICS) proforma
132. Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s operation
132.1 Overview
132.1.1 Summary of major concepts
132.1.2 Application
132.1.3 Rate of operation
132.1.4 Delay constraints
132.1.5 Allocation of functions
132.1.6 50GMII structure
132.1.7 Mapping of 50GMII signals to PLS service primitives
132.2 50GMII data stream
132.3 50GMII functional specifications
132.4 LPI assertion and detection
132.5 Protocol implementation conformance statement (PICS) proforma for Clause 132, Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s operation
132.5.1 Introduction
132.5.2 Identification
132.5.2.1 Implementation identification
132.5.2.2 Protocol summary
132.5.2.3 Major capabilities/options
132.5.3 PICS proforma tables for Reconciliation Sublayer (RS) and Media Independent Interface (50GMII) for 50 Gb/s operation
132.5.3.1 General
132.5.3.2 Mapping of PLS service primitives
133. Physical Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R
133.1 Overview
133.1.1 Scope
133.1.2 Relationship of 50GBASE-R to other standards
133.1.3 Summary of 50GBASE-R sublayers
133.1.3.1 Physical Coding Sublayer (PCS)
133.1.4 Inter-sublayer interfaces
133.1.4.1 PCS service interface (50GMII)
133.1.4.2 Forward Error Correction (FEC) or Physical Medium Attachment (PMA) service interface
133.1.5 Functional block diagram
133.2 Physical Coding Sublayer (PCS)
133.2.1 Functions within the PCS
133.2.2 Alignment marker insertion
133.2.3 PCS lane deskew
133.2.4 Detailed functions and state diagrams
133.3 Delay constraints
133.4 Auto-Negotiation
133.5 Protocol implementation conformance statement (PICS) proforma for Clause 133, Physical Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R
133.5.1 Introduction
133.5.2 Identification
133.5.2.1 Implementation identification
133.5.2.2 Protocol summary
133.5.3 Major capabilities/options
133.5.4 PICS proforma tables for Physical Coding Sublayer (PCS) for 64B/66B, type 50GBASE-R
133.5.4.1 Coding rules
133.5.4.2 Scrambler and Descrambler
133.5.4.3 Deskew and Reordering
133.5.4.4 Alignment Markers
133.5.4.5 Test-pattern modes
133.5.4.6 Bit order
133.5.4.7 Management
133.5.4.8 State diagrams
133.5.4.9 Loopback
133.5.4.10 Delay constraints
133.5.4.11 Auto-Negotiation for Backplane Ethernet functions
134. Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 50GBASE-R PHYs
134.1 Overview
134.1.1 Scope
134.1.2 Position of RS-FEC in the 50GBASE-R sublayers
134.2 FEC service interface
134.3 PMA compatibility
134.4 Delay constraints
134.5 Functions within the RS-FEC sublayer
134.5.1 Functional block diagram
134.5.2 Transmit function
134.5.2.1 PCS Lane block synchronization
134.5.2.2 PCS Alignment lock and deskew
134.5.2.3 PCS Lane reorder
134.5.2.4 Alignment marker removal
134.5.2.5 64B/66B to 256B/257B transcoder
134.5.2.6 Alignment marker mapping and insertion
134.5.2.7 Reed-Solomon encoder
134.5.2.8 Symbol distribution
134.5.2.9 Transmit bit ordering
134.5.3 Receive function
134.5.3.1 Alignment lock and deskew
134.5.3.2 FEC Lane reorder
134.5.3.3 Reed-Solomon decoder
134.5.3.3.1 FEC Error indication bypass (optional)
134.5.3.3.2 FEC Degraded SER (optional)
134.5.3.4 Alignment marker removal
134.5.3.5 256B/257B to 64B/66B transcoder
134.5.3.6 Block distribution
134.5.3.7 Alignment marker mapping and insertion
134.5.3.8 Receive bit ordering
134.5.4 Detailed functions and state diagrams
134.5.4.1 State diagram conventions
134.5.4.2 State variables
134.5.4.2.1 Variables
134.5.4.2.2 Functions
134.5.4.2.3 Counters
134.5.4.3 State diagrams
134.6 RS-FEC MDIO function mapping
134.6.1 FEC_bypass_indication_enable
134.6.2 FEC_degraded_SER_enable
134.6.3 FEC_degraded_SER_activate_threshold
134.6.4 FEC_degraded_SER_deactivate_threshold
134.6.5 FEC_degraded_SER_interval
134.6.6 FEC_bypass_indication_ability
134.6.7 hi_ser
134.6.8 FEC_degraded_SER_ability
134.6.9 FEC_degraded_SER
134.6.10 fec_optional_states
134.6.11 amps_lock
134.6.12 fec_align_status
134.6.13 FEC_corrected_cw_counter
134.6.14 FEC_uncorrected_cw_counter
134.6.15 FEC_lane_mapping
134.6.16 FEC_symbol_error_counter_i
134.6.17 align_status
134.6.18 BIP_error_counter_i
134.6.19 lane_mapping
134.6.20 block_lock
134.6.21 am_lock
134.7 Protocol implementation conformance statement (PICS) proforma for Clause 134, Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 50GBASE-R PHYs
134.7.1 Introduction
134.7.2 Identification
134.7.2.1 Implementation identification
134.7.2.2 Protocol summary
134.7.3 Major capabilities/options
134.7.4 PICS proforma tables for Reed-Solomon Forward Error Correction (RS-FEC) sublayer for 50GBASE-R PHYs
134.7.4.1 Transmit function
134.7.4.2 Receive function
134.7.4.3 State diagrams
134.7.4.4 Delay Constraints
135. Physical Medium Attachment (PMA) sublayer, type 50GBASE-R and 100GBASE-P
135.1 Overview
135.1.1 Scope
135.1.2 Position of the PMA in the 50GBASE-R and 100GBASE-P sublayers
135.1.3 Summary of functions
135.1.4 PMA sublayer positioning
135.2 PMA interfaces
135.3 PMA service interface
135.4 Service interface below PMA
135.5 Functions within the PMA
135.5.1 Per input-lane clock and data recovery
135.5.2 Bit-level multiplexing
135.5.3 Skew and Skew Variation
135.5.3.1 Skew generation toward SP0
135.5.3.2 Skew tolerance at SP0
135.5.3.3 Skew generation toward SP1
135.5.3.4 Skew tolerance at SP1
135.5.3.5 Skew generation toward SP2
135.5.3.6 Skew tolerance at SP5
135.5.3.7 Skew generation at SP6
135.5.3.8 Skew tolerance at SP6
135.5.3.9 Skew generation at SP7
135.5.3.10 Skew tolerance at SP7
135.5.4 Delay constraints
135.5.5 Clocking architecture
135.5.6 Signal drivers
135.5.7 PAM4 encoding
135.5.7.1 Gray mapping for PAM4 encoded lanes
135.5.7.2 Precoding for PAM4 encoded lanes
135.5.8 PMA local loopback mode (optional)
135.5.9 PMA remote loopback mode (optional)
135.5.10 PMA test patterns (optional)
135.5.10.1 Test patterns for NRZ encoded signals
135.5.10.1.1 PRBS31 test pattern
135.5.10.1.2 PRBS9 test pattern
135.5.10.1.3 Square-wave test pattern
135.5.10.2 Test patterns for PAM4 encoded signals
135.5.10.2.1 PRBS13Q test pattern
135.5.10.2.2 PRBS31Q test pattern
135.5.10.2.3 SSPRQ test pattern
135.5.10.2.4 Square wave (quaternary) test pattern
135.6 PMA MDIO function mapping
135.7 Protocol implementation conformance statement (PICS) proforma for Clause 135, Physical Medium Attachment (PMA) sublayer, type 50GBASE-R and 100GBASE-P
135.7.1 Introduction
135.7.2 Identification
135.7.2.1 Implementation identification
135.7.2.2 Protocol summary
135.7.3 Major capabilities/options
135.7.4 PICS proforma tables for Physical Medium Attachment (PMA) sublayer, type 50GBASE-R and 100GBASE-P
135.7.4.1 Functions
135.7.4.2 Timing
135.7.4.3 Electrical
135.7.4.4 Diagnostics
135.7.7 Encoding
136. Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136.1 Overview
136.2 Conventions
136.3 PMD service interfaces
136.4 PCS requirements for Auto-Negotiation (AN) service interface
136.5 Delay constraints
136.6 Skew constraints
136.6.1 Skew Constraints for 50GBASE-CR
136.6.2 Skew Constraints for 100GBASE-CR2 and 200GBASE-CR4
136.7 PMD MDIO function mapping
136.8 PMD functional specifications
136.8.1 Link block diagram
136.8.2 PMD transmit function
136.8.3 PMD receive function
136.8.4 PMD global signal detect function
136.8.5 PMD lane-by-lane signal detect function
136.8.6 PMD global transmit disable function (optional)
136.8.7 PMD lane-by-lane transmit disable function (optional)
136.8.8 PMD fault function
136.8.9 PMD transmit fault function (optional)
136.8.10 PMD receive fault function (optional)
136.8.11 PMD control function
136.8.11.1 Training frame structure
136.8.11.1.1 Frame marker
136.8.11.1.2 Control and status fields
136.8.11.1.3 Training pattern
136.8.11.1.4 Zero pad
136.8.11.2 Control field structure
136.8.11.2.1 Initial condition request
136.8.11.2.2 Modulation and precoding request
136.8.11.2.3 Coefficient select
136.8.11.2.4 Coefficient request
136.8.11.3 Status field structure
136.8.11.3.1 Receiver ready
136.8.11.3.2 Modulation and precoding status
136.8.11.3.3 Receiver frame lock
136.8.11.3.4 Initial condition status
136.8.11.3.5 Parity bit
136.8.11.3.6 Coefficient select echo
136.8.11.3.7 Coefficient status
136.8.11.4 Equalization control
136.8.11.4.1 Initial condition setting request process
136.8.11.4.2 Initial condition setting response process
136.8.11.4.3 Coefficient update request process
136.8.11.4.4 Coefficient update response process
136.8.11.5 Modulation and precoding setting
136.8.11.6 Handshake timing
136.8.11.7 Variables, functions, timers, counters, and state diagrams
136.8.11.7.1 Variables
136.8.11.7.2 Functions
136.8.11.7.3 Timers
136.8.11.7.4 Counters
136.8.11.7.5 State diagrams
136.9 PMD electrical characteristics
136.9.1 AC-coupling
136.9.2 Signal paths
136.9.3 Transmitter characteristics
136.9.3.1 Transmitter output waveform
136.9.3.1.1 Linear fit to the measured waveform
136.9.3.1.2 Steady-state voltage and linear fit pulse peak
136.9.3.1.3 Coefficient initialization
136.9.3.1.4 Coefficient step size
136.9.3.1.5 Coefficient range
136.9.3.2 Insertion loss, TP0 to TP2 or TP3 to TP5
136.9.3.3 J3u jitter
136.9.3.4 Transmitter effective return loss (ERL)
136.9.4 Receiver characteristics
136.9.4.1 Receiver input amplitude tolerance
136.9.4.2 Receiver interference tolerance
136.9.4.2.1 Test setup
136.9.4.2.2 Test channel
136.9.4.2.3 Test channel calibration
136.9.4.2.4 Pattern generator and noise injection
136.9.4.2.5 Test procedure
136.9.4.3 Receiver jitter tolerance
136.9.4.3.1 Test setup
136.9.4.3.2 Test procedure
136.9.4.4 Signaling rate range
136.9.4.5 Receiver ERL
136.10 Channel characteristics
136.11 Cable assembly characteristics
136.11.1 Characteristic impedance and reference impedance
136.11.2 Cable assembly insertion loss
136.11.3 Cable assembly ERL
136.11.4 Differential to common-mode return loss
136.11.5 Differential to common-mode conversion loss
136.11.6 Common-mode to common-mode return loss
136.11.7 Cable assembly Channel Operating Margin
136.11.7.1 Channel signal and crosstalk path calculations
136.11.7.1.1 Channel signal path
136.11.7.1.2 Channel crosstalk paths
136.11.7.2 Signal and crosstalk paths used in calculation of COM
136.12 MDI specifications
136.13 Environmental specifications
136.14 Protocol implementation conformance statement (PICS) proforma for Clause 136, Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136.14.1 Introduction
136.14.2 Identification
136.14.2.1 Implementation identification
136.14.2.2 Protocol summary
136.14.3 Major capabilities/options
136.14.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136.14.4.1 PMD functional specifications
136.14.4.2 PMD control function
136.14.4.3 Transmitter specifications
136.14.4.4 Receiver specifications
136.14.4.5 Cable assembly specifications
136.14.4.6 Environmental specifications
137. Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-KR, 100GBASE-KR2, and 200GBASE-KR4
137.1 Overview
137.2 Conventions
137.3 PMD service interfaces
137.4 PCS requirements for Auto-Negotiation (AN) service interface
137.5 Delay constraints
137.6 Skew constraints
137.6.1 Skew Constraints for 50GBASE-KR
137.6.2 Skew Constraints for 100GBASE-KR2 and 200GBASE-KR4
137.7 PMD MDIO function mapping
137.8 PMD functional specifications
137.8.1 Link block diagram
137.8.2 PMD transmit function
137.8.3 PMD receive function
137.8.4 PMD global signal detect function
137.8.5 PMD lane-by-lane signal detect function
137.8.6 PMD global transmit disable function (optional)
137.8.7 PMD lane-by-lane transmit disable function (optional)
137.8.8 PMD fault function
137.8.9 PMD transmit fault function (optional)
137.8.10 PMD receive fault function (optional)
137.8.11 PMD control function
137.9 Electrical characteristics
137.9.1 MDI
137.9.2 Transmitter characteristics
137.9.2.1 Transmitter ERL
137.9.3 Receiver characteristics
137.9.3.1 Receiver ERL
137.10 Channel characteristics
137.10.1 Channel insertion loss
137.10.2 Channel ERL
137.11 Environmental specifications
137.12 Protocol implementation conformance statement (PICS) proforma for Clause 137, Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-KR, 100GBASE-KR2, and 200GBASE-KR4
137.12.1 Introduction
137.12.2 Identification
137.12.2.1 Implementation identification
137.12.2.2 Protocol summary
137.12.3 Major capabilities/options
137.12.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and baseband medium, type 50GBASE-KR, 100GBASE-KR2, and 200GBASE-KR4
137.12.4.1 Functional specifications
137.12.4.2 PMD control function
137.12.4.3 Transmitter characteristics
137.12.4.4 Receiver characteristics
137.12.4.5 Channel characteristics
137.12.4.6 Environmental specifications
138. Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-SR, 100GBASE-SR2, 200GBASE-SR4
138.1 Overview
138.1.1 Bit error ratio
138.2 Physical Medium Dependent (PMD) service interface
138.3 Delay and Skew
138.3.1 Delay constraints
138.3.2 Skew constraints
138.3.2.1 Skew Constraints for 50GBASE-SR
138.3.2.2 Skew Constraints for 100GBASE-SR2 and 200GBASE-SR4
138.4 PMD MDIO function mapping
138.5 PMD functional specifications
138.5.1 PMD block diagram
138.5.2 PMD transmit function
138.5.3 PMD receive function
138.5.4 PMD global signal detect function
138.5.5 PMD lane-by-lane signal detect function
138.5.6 PMD reset function
138.5.7 PMD global transmit disable function (optional)
138.5.8 PMD lane-by-lane transmit disable function (optional)
138.5.9 PMD fault function (optional)
138.5.10 PMD transmit fault function (optional)
138.5.11 PMD receive fault function (optional)
138.6 Lane assignments
138.7 PMD to MDI optical specifications for 50GBASE-SR, 100GBASE-SR2, and 200GBASE-SR4
138.7.1 Transmitter optical specifications
138.7.2 Receiver optical specifications
138.7.3 Illustrative link power budget
138.8 Definition of optical parameters and measurement methods
138.8.1 Test patterns for optical parameters
138.8.1.1 Multi-lane testing considerations
138.8.2 Center wavelength and spectral width
138.8.3 Average optical power
138.8.4 Outer Optical Modulation Amplitude (OMAouter)
138.8.5 Transmitter and dispersion eye closure for PAM4 (TDECQ)
138.8.5.1 TDECQ reference equalizer
138.8.6 Extinction ratio
138.8.7 Transmitter transition time
138.8.8 Relative intensity noise (RIN12OMA)
138.8.9 Receiver sensitivity
138.8.10 Stressed receiver sensitivity
138.8.10.1 Sinusoidal jitter for receiver conformance test
138.9 Safety, installation, environment, and labeling
138.9.1 General safety
138.9.2 Laser safety
138.9.3 Installation
138.9.4 Environment
138.9.5 Electromagnetic emission
138.9.6 Temperature, humidity, and handling
138.9.7 PMD labeling requirements
138.10 Fiber optic cabling model
138.10.1 Fiber optic cabling model
138.10.2 Characteristics of the fiber optic cabling (channel)
138.10.2.1 Optical fiber cable
138.10.2.2 Optical fiber connection
138.10.2.2.1 Connection insertion loss
138.10.2.2.2 Maximum discrete reflectance
138.10.3 Medium Dependent Interface (MDI)
138.10.3.1 Optical lane assignments for 100GBASE-SR2 and 200GBASE-SR4
138.10.3.2 MDI requirements for 50GBASE-SR
138.10.3.3 MDI requirements for 100GBASE-SR2 and 200GBASE-SR4
138.11 Protocol implementation conformance statement (PICS) proforma for Clause 138, Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-SR, 100GBASE-SR2, 200GBASE-SR4
138.11.1 Introduction
138.11.2 Identification
138.11.2.1 Implementation identification
138.11.2.2 Protocol summary
138.11.3 Major capabilities/options
138.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-SR, 100GBASE-SR2, 200GBASE-SR4
138.11.4.1 PMD functional specifications
138.11.4.2 Management functions
138.11.4.3 PMD to MDI optical specifications
138.11.4.4 Optical measurement methods
138.11.4.5 Environmental specifications
138.11.4.6 Characteristics of the fiber optic cabling and MDI
139. Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-FR and 50GBASE-LR
139.1 Overview
139.1.1 Bit error ratio
139.2 Physical Medium Dependent (PMD) service interface
139.3 Delay and Skew
139.3.1 Delay constraints
139.3.2 Skew constraints
139.4 PMD MDIO function mapping
139.5 PMD functional specifications
139.5.1 PMD block diagram
139.5.2 PMD transmit function
139.5.3 PMD receive function
139.5.4 PMD global signal detect function
139.5.5 PMD reset function
139.5.6 PMD global transmit disable function (optional)
139.5.7 PMD fault function (optional)
139.5.8 PMD transmit fault function (optional)
139.5.9 PMD receive fault function (optional)
139.6 PMD to MDI optical specifications for 50GBASE-FR and 50GBASE-LR
139.6.1 50GBASE-FR and 50GBASE-LR transmitter optical specifications
139.6.2 50GBASE-FR and 50GBASE-LR receive optical specifications
139.6.3 50GBASE-FR and 50GBASE-LR illustrative link power budgets
139.7 Definition of optical parameters and measurement methods
139.7.1 Test patterns for optical parameters
139.7.2 Wavelength and side-mode suppression ratio (SMSR)
139.7.3 Average optical power
139.7.4 Outer Optical Modulation Amplitude (OMAouter)
139.7.5 Transmitter and dispersion eye closure for PAM4 (TDECQ)
139.7.5.1 TDECQ conformance test setup
139.7.5.2 Channel requirements
139.7.5.3 TDECQ measurement method
139.7.5.4 TDECQ reference equalizer
139.7.6 Extinction ratio
139.7.7 Transmitter transition time
139.7.8 Relative intensity noise (RIN17.1OMA and RIN15.6OMA)
139.7.9 Receiver sensitivity
139.7.10 Stressed receiver sensitivity
139.7.10.1 Stressed receiver conformance test block diagram
139.7.10.2 Stressed receiver conformance test signal characteristics and calibration
139.7.10.3 Stressed receiver conformance test signal verification
139.8 Safety, installation, environment, and labeling
139.8.1 General safety
139.8.2 Laser safety
139.8.3 Installation
139.8.4 Environment
139.8.5 Electromagnetic emission
139.8.6 Temperature, humidity, and handling
139.8.7 PMD labeling requirements
139.9 Fiber optic cabling model
139.10 Characteristics of the fiber optic cabling (channel)
139.10.1 Optical fiber cable
139.10.2 Optical fiber connection
139.10.2.1 Connection insertion loss
139.10.2.2 Maximum discrete reflectance
139.10.3 Medium Dependent Interface (MDI) requirements
139.11 Protocol implementation conformance statement (PICS) proforma for Clause 139, Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-FR and 50GBASE-LR
139.11.1 Introduction
139.11.2 Identification
139.11.2.1 Implementation identification
139.11.2.2 Protocol summary
139.11.3 Major capabilities/options
139.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 50GBASE-FR and 50GBASE-LR
139.11.4.1 PMD functional specifications
139.11.4.2 Management functions
139.11.4.3 PMD to MDI optical specifications for 50GBASE-FR
139.11.4.4 PMD to MDI optical specifications for 50GBASE-LR
139.11.4.5 Optical measurement methods
139.11.4.6 Environmental specifications
139.11.4.7 Characteristics of the fiber optic cabling and MD
140. Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-DR
140.1 Overview
140.1.1 Bit error ratio
140.2 Physical Medium Dependent (PMD) service interface
140.3 Delay and Skew
140.3.1 Delay constraints
140.3.2 Skew constraints
140.4 PMD MDIO function mapping
140.5 PMD functional specifications
140.5.1 PMD block diagram
140.5.2 PMD transmit function
140.5.3 PMD receive function
140.5.4 PMD global signal detect function
140.5.5 PMD reset function
140.5.6 PMD global transmit disable function (optional)
140.5.7 PMD fault function (optional)
140.5.8 PMD transmit fault function (optional)
140.5.9 PMD receive fault function (optional)
140.6 PMD to MDI optical specifications for 100GBASE-DR
140.6.1 100GBASE-DR transmitter optical specifications
140.6.2 100GBASE-DR receive optical specifications
140.6.3 100GBASE-DR illustrative link power budget
140.7 Definition of optical parameters and measurement methods
140.7.1 Test patterns for optical parameters
140.7.2 Wavelength and side-mode suppression ratio (SMSR)
140.7.3 Average optical power
140.7.4 Outer Optical Modulation Amplitude (OMAouter)
140.7.5 Transmitter and dispersion eye closure for PAM4 (TDECQ)
140.7.5.1 TDECQ reference equalizer
140.7.6 Extinction ratio
140.7.7 Transmitter transition time
140.7.8 Relative intensity noise (RIN15.5OMA)
140.7.9 Receiver sensitivity
140.7.10 Stressed receiver sensitivity
140.8 Safety, installation, environment, and labeling
140.8.1 General safety
140.8.2 Laser safety
140.8.3 Installation
140.8.4 Environment
140.8.5 Electromagnetic emission
140.8.6 Temperature, humidity, and handling
140.8.7 PMD labeling requirements
140.9 Fiber optic cabling model
140.10 Characteristics of the fiber optic cabling (channel)
140.10.1 Optical fiber cable
140.10.2 Optical fiber connection
140.10.2.1 Connection insertion loss
140.10.2.2 Maximum discrete reflectance
140.10.3 Medium Dependent Interface (MDI)
140.11 Protocol implementation conformance statement (PICS) proforma for Clause 140, Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-DR
140.11.1 Introduction
140.11.2 Identification
140.11.2.1 Implementation identification
140.11.2.2 Protocol summary
140.11.3 Major capabilities/options
140.11.4 PICS proforma tables for Physical Medium Dependent (PMD) sublayer and medium, type 100GBASE-DR
140.11.4.1 PMD functional specifications
140.11.4.2 Management functions
140.11.4.3 PMD to MDI optical specifications for 100GBASE-DR
140.11.4.4 Optical measurement methods
140.11.4.5 Environmental specifications
140.11.4.6 Characteristics of the fiber optic cabling and MD
Annex 4A (normative) Simplified full duplex media access control
4A.4 Specific implementations
4A.4.2 MAC parameters
Annex 31B (normative) MAC Control PAUSE operation
31B.3 Detailed specification of PAUSE operation
31B.3.7 Timing considerations for PAUSE operation
31B.4 Protocol implementation conformance statement (PICS) proforma for MAC Control PAUSE operation
31B.4.3 Major capabilities/options
31B.4.6 PAUSE command MAC timing considerations
Annex 93A (normative) Specification methods for electrical channels
93A.1 Channel Operating Margin
93A.1.4 Filters
93A.1.4.2 Transmitter equalizer
93A.1.6 Determination of variable equalizer parameters
93A.5 Effective Return Loss
93A.5.1 Pulse time-domain reflection signal
93A.5.2 Effective reflection waveform
93A.5.3 Sampled effective reflection
93A.5.4 x-quantile of the reflection distribution
93A.5.5 ERL
Annex 135A (informative) 50 Gb/s and 100 Gb/s PMA sublayer partitioning examples
135A.1 Partitioning examples of 50GBASE-R PHYs
135A.2 Partitioning examples of 100GBASE-P PHYs
Annex 135B (normative) Chip-to-Chip 50 Gb/s two-lane Attachment Unit Interface (LAUI-2 C2C)
135B.1 Overview
135B.2 LAUI-2 C2C compliance point definition
135B.3 LAUI-2 C2C electrical characteristics
135B.3.1 LAUI-2 C2C transmitter characteristics
135B.3.2 LAUI-2 C2C receiver characteristics
135B.4 LAUI-2 C2C channel characteristics
135B.5 Protocol implementation conformance statement (PICS) proforma for Annex 135B, Chip-to-Chip 50 Gb/s two-lane Attachment Unit Interface (LAUI-2 C2C)
135B.5.1 Introduction
135B.5.2 Identification
135B.5.2.1 Implementation identification
135B.5.2.2 Protocol summary
135B.5.3 Major capabilities/options
135B.5.4 PICS proforma tables for chip-to-chip 50 Gb/s two-lane Attachment Unit Interface (LAUI-2 C2C)
135B.5.4.1 Transmitter
135B.5.4.2 Receiver
135B.5.4.3 Channel
Annex 135C (normative) Chip-to-module 50 Gb/s two-lane Attachment Unit Interface (LAUI-2 C2M)
135C.1 Overview
135C.1.1 Bit error ratio
135C.2 LAUI-2 C2M compliance point definitions
135C.3 LAUI-2 C2M electrical characteristics
135C.3.1 LAUI-2 C2M host output characteristics
135C.3.2 LAUI-2 C2M module output characteristics
135C.3.3 LAUI-2 C2M host input characteristics
135C.3.4 LAUI-2 C2M module input characteristics
135C.4 LAUI-2 C2M measurement methodology
135C.5 Protocol implementation conformance statement (PICS) proforma for Annex 135C, Chip-to-module 50 Gb/s two-lane Attachment Unit Interface (LAUI-2 C2M)
135C.5.1 Introduction
135C.5.2 Identification
135C.5.2.1 Implementation identification
135C.5.2.2 Protocol summary
135C.5.3 Major capabilities/options
135C.5.4 PICS proforma tables for chip-to-module 50 Gb/s two-lane Attachment Unit Interface (LAUI-2 C2M)
135C.5.4.1 Host output
135C.5.4.2 Module output
135C.5.4.3 Host input
135C.5.4.4 Module input
Annex 135D (normative) Chip-to-chip 50 Gb/s two-lane Attachment Unit Interface (50GAUI-2 C2C) and 100 Gb/s four-lane Attachment Unit Interface (100GAUI-4 C2C)
135D.1 Overview
135D.2 50GAUI-2 C2C and 100GAUI-4 C2C compliance point definition
135D.3 50GAUI-2 C2C and 100GAUI-4 C2C electrical characteristics
135D.3.1 50GAUI-2 C2C and 100GAUI-4 C2C transmitter characteristics
135D.3.2 50GAUI-2 C2C and 100GAUI-4 C2C receiver characteristics
135D.4 50GAUI-2 C2C and 100GAUI-4 C2C channel characteristics
135D.5 Protocol implementation conformance statement (PICS) proforma for Annex 135D, Chip-to-chip 50 Gb/s two-lane Attachment Unit Interface (50GAUI-2 C2C) and 100 Gb/s four-lane Attachment Unit Interface (100GAUI-4 C2C)
135D.5.1 Introduction
135D.5.2 Identification
135D.5.2.1 Implementation identification
135D.5.2.2 Protocol summary
135D.5.3 Major capabilities/options
135D.5.4 PICS proforma tables for chip-to-chip 50 Gb/s two-lane Attachment Unit Interface (50GAUI-2 C2C) and 100 Gb/s four-lane Attachment Unit Interface (100GAUI-4 C2C)
135D.5.4.1 Transmitter
135D.5.4.2 Receiver
135D.5.4.3 Channel
Annex 135E (normative) Chip-to-module 50 Gb/s two-lane Attachment Unit Interface (50GAUI-2 C2M) and 100 Gb/s four-lane Attachment Unit Interface (100GAUI-4 C2M)
135E.1 Overview
135E.1.1 Bit error ratio
135E.2 50GAUI-2 C2M and 100GAUI-4 C2M compliance point definitions
135E.3 50GAUI-2 C2M and 100GAUI-4 C2M electrical characteristics
135E.3.1 50GAUI-2 C2M and 100GAUI-4 C2M host output characteristics
135E.3.2 50GAUI-2 C2M and 100GAUI-4 C2M module output characteristics
135E.3.3 50GAUI-2 C2M and 100GAUI-4 C2M host input characteristics
135E.3.4 50GAUI-2 C2M and 100GAUI-4 C2M module input characteristics
135E.4 50GAUI-2 C2M and 100GAUI-4 C2M measurement methodology
135E.5 Protocol implementation conformance statement (PICS) proforma for Annex 135E, Chip-to-module 50 Gb/s two-lane Attachment Unit Interface (50GAUI-2 C2M) and 100 Gb/s four-lane Attachment Unit Interface (100GAUI-4 C2M)
135E.5.1 Introduction
135E.5.2 Identification
135E.5.2.1 Implementation identification
135E.5.2.2 Protocol summary
135E.5.3 Major capabilities/options
135E.5.4 PICS proforma tables for chip-to-module 50 Gb/s two-lane Attachment Unit Interface (50GAUI-2 C2M) and 100 Gb/s four-lane Attachment Unit Interface (100GAUI-4 C2M)
135E.5.4.1 Host output
135E.5.4.2 Module output
135E.5.4.3 Host input
135E.5.4.4 Module input
Annex 135F (normative) Chip-to-chip 50 Gb/s one-lane Attachment Unit Interface (50GAUI-1 C2C) and 100 Gb/s two-lane Attachment Unit Interface (100GAUI-2 C2C)
135F.1 Overview
135F.2 50GAUI-1 C2C and 100GAUI-2 C2C compliance point definition
135F.3 50GAUI-1 C2C and 100GAUI-2 C2C electrical characteristics
135F.3.1 50GAUI-1 C2C and 100GAUI-2 C2C transmitter characteristics
135F.3.2 50GAUI-1 C2C and 100GAUI-2 C2C receiver characteristics
135F.3.2.1 Transmitter precoder request (optional)
135F.4 50GAUI-1 C2C and 100GAUI-2 C2C channel characteristics
135F.5 Example usage of the optional transmitter precoder request
135F.5.1 Overview
135F.5.2 Configuring precoder setting in the transmit direction
135F.5.3 Configuring precoder setting in the receive direction
135F.6 Protocol implementation conformance statement (PICS) proforma for Annex 135F, Chip-to-chip 50 Gb/s one-lane Attachment Unit Interface (50GAUI-1 C2C) and 100 Gb/s two-lane Attachment Unit Interface (100GAUI-2 C2C)
135F.6.1 Introduction
135F.6.2 Identification
135F.6.2.1 Implementation identification
135F.6.2.2 Protocol summary
135F.6.3 Major capabilities/options
135F.6.4 PICS proforma tables for chip-to-chip 50 Gb/s one-lane Attachment Unit Interface (50GAUI-1 C2C) and 100 Gb/s two-lane Attachment Unit Interface (100GAUI-2 C2C)
135F.6.4.1 Transmitter
135F.6.4.2 Receiver
135F.6.4.3 Channel
Annex 135G (normative) Chip-to-module 50 Gb/s one-lane Attachment Unit Interface (50GAUI-1 C2M) and 100 Gb/s two-lane Attachment Unit Interface (100GAUI-2 C2M)
135G.1 Overview
135G.1.1 Bit error ratio
135G.2 50GAUI-1 C2M and 100GAUI-2 C2M compliance point definitions
135G.3 50GAUI-1 C2M and 100GAUI-2 C2M electrical characteristics
135G.3.1 50GAUI-1 C2M and 100GAUI-2 C2M host output characteristics
135G.3.2 50GAUI-1 C2M and 100GAUI-2 C2M module output characteristics
135G.3.3 50GAUI-1 C2M and 100GAUI-2 C2M host input characteristics
135G.3.4 50GAUI-1 C2M and 100GAUI-2 C2M module input characteristics
135G.4 50GAUI-1 C2M and 100GAUI-2 C2M measurement methodology
135G.5 Protocol implementation conformance statement (PICS) proforma for Annex 135G, Chip-to-module 50 Gb/s one-lane Attachment Unit Interface (50GAUI-1 C2M) and 100 Gb/s two-lane Attachment Unit Interface (100GAUI-2 C2M)
135G.5.1 Introduction
135G.5.2 Identification
135G.5.2.1 Implementation identification
135G.5.2.2 Protocol summary
135G.5.3 Major capabilities/options
135G.5.4 PICS proforma tables for chip-to-module 50 Gb/s one-lane Attachment Unit Interface (50GAUI-1 C2M) and 100 Gb/s two-lane Attachment Unit Interface (100GAUI-2 C2M)
135G.5.4.1 Host output
135G.5.4.2 Module output
135G.5.4.3 Host input
135G.5.4.4 Module input
Annex 136A (informative) TP0 and TP5 test point parameters and channel characteristics for 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136A.1 Overview
136A.2 Transmitter characteristics at TP0
136A.3 Receiver characteristics at TP5
136A.4 Transmitter and receiver differential printed circuit board trace loss
136A.5 Channel insertion loss
136A.6 Channel effective return loss
136A.7 Channel Operating Margin (COM)
Annex 136B (normative) Test fixtures for 50GBASE-CR, 100GBASE-CR2, 200GBASE-CR4, 50GAUI-1 C2M, and 100GAUI-2 C2M
136B.1 Test fixtures
136B.1.1 Mated test fixtures
136B.1.1.1 Mated test fixtures differential insertion loss
136B.1.1.2 Mated test fixtures differential return loss
136B.1.1.3 Mated test fixtures common-mode conversion insertion loss
136B.1.1.4 Mated test fixtures common-mode return loss
136B.1.1.5 Mated test fixtures common-mode to differential mode return loss
136B.1.1.6 Mated test fixtures integrated crosstalk noise
136B.2 Protocol implementation conformance statement (PICS) proforma for Annex 136B, Test fixtures for 50GBASE-CR, 100GBASE-CR2, 200GBASE-CR4, 50GAUI-1 C2M, and 100GAUI-2 C2M
136B.2.1 Introduction
136B.2.2 Identification
136B.2.2.1 Implementation identification
136B.2.2.2 Protocol summary
136B.2.3 Major capabilities/options
136B.2.4 PICS proforma tables for test fixtures for 50GBASE-CR, 100GBASE-CR2, 200GBASE-CR4, 50GAUI-1 C2M, and 100GAUI-2 C2M
Annex 136C (normative) MDIs for 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136C.1 Overview
136C.2 MDI connector types
136C.2.1 SFP28
136C.2.2 QSFP28
136C.2.3 MicroQSFP
136C.2.4 QSFP-DD
136C.2.5 OSFP
136C.3 Protocol implementation conformance statement (PICS) proforma for Annex 136C, MDIs for 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136C.3.1 Introduction
136C.3.2 Identification
136C.3.2.1 Implementation identification
136C.3.2.2 Protocol summary
136C.3.3 Major capabilities/options
136C.3.4 PICS proforma tables for MDIs for 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136C.3.4.1 Contact Mapping
Annex 136D (informative) Host and cable assembly form factors for 50GBASE-CR, 100GBASE-CR2, and 200GBASE-CR4
136D.1 Overview
136D.2 Host form factors
136D.2.1 SFP28 host form factor
136D.2.2 QSFP28 host form factor
136D.2.3 microQSFP host form factor
136D.2.4 QSFP-DD host form factor
136D.2.5 OSFP host form factor
136D.3 Cable assembly form factors
136D.3.1 One-plug to one-plug cable assembly form factor
136D.3.2 One-plug to two-plug cable assembly form factor
136D.3.3 One-plug to four-plug cable assembly form factor
136D.3.4 One-plug to eight-plug cable assembly form factor
Back cover
IEEE Standard for Ethernet
Amendment 3:
Media Access Control Parameters
for 50 Gb/s and Physical Layers and
Management Parameters for 50 Gb/s,
100 Gb/s, and 200 Gb/s Operation
IEEE Computer Society
LAN/MAN Standards Committee
Sponsored by the
IEEE
3 Park Avenue
New York, NY 10016-5997
USA
IEEE Std 802.3cd™-2018
(Amendment to
IEEE Std 802.3™-2018
as amended by
IEEE Std 802.3cb™-2018
and IEEE Std 802.3bt™-2018)
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IEEE Std 802.3cd™-2018
(Amendment to IEEE Std 802.3™-2018
as amended by IEEE Std 802.3cb™-2018
and IEEE Std 802.3bt™-2018)
IEEE Standard for Ethernet
Amendment 3:
Media Access Control Parameters
for 50 Gb/s and Physical Layers and
Management Parameters for 50 Gb/s,
100 Gb/s, and 200 Gb/s Operation
Sponsor
LAN/MAN Standards Committee
of the
IEEE Computer Society
Approved 5 December 2018
IEEE-SA Standards Board
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Abstract: Clause 131 through Clause 140 and Annex 135A through Annex 136D are added to
IEEE Std 802.3-2018 by this amendment to specify IEEE 802.3 Media Access Control (MAC)
parameters, Physical Layer specifications, and management parameters for the transfer of IEEE
802.3 format frames at 50 Gb/s, 100 Gb/s, and 200 Gb/s.
Keywords: 50GAUI-1, 50GAUI-2, 50GBASE-CR, 50GBASE-FR, 50GBASE-KR, 50GBASE-LR,
50GBASE-SR, 50 Gigabit Ethernet, 50GMII, 100GAUI-2, 100GAUI-4, 100GBASE-CR2,
100GBASE-DR, 100GBASE-KR2, 100GBASE-SR2, 100 Gigabit Ethernet, 200GBASE-CR4,
200GBASE-KR4, 200GBASE-SR4, 200 Gigabit Ethernet, amendment, EEE, Energy-Efficient
Ethernet, Ethernet, FEC, forward error correction, IEEE 802.3™, IEEE 802.3cd™, LAUI-2, MMF,
SMF
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2019 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 15 February 2019. Printed in the United States of America.
IEEE and 802 are registered trademarks in the U.S. Patent & Trademark Office, owned by The Institute of Electrical and
Electronics Engineers, Incorporated.
ISBN 978-1-5044-5357-8 STD23441
PDF:
ISBN 978-1-5044-5358-5 STDPD23441
Print:
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Participants
The following individuals were officers and members of the IEEE 802.3 Working Group at the beginning of
the IEEE P802.3cd Working Group ballot.
David J. Law, IEEE 802.3 Working Group Chair
Adam Healey, IEEE 802.3 Working Group Vice-Chair
Pete Anslow, IEEE 802.3 Working Group Secretary
Steven B. Carlson, IEEE 802.3 Working Group Executive Secretary
Valerie Maguire, IEEE 802.3 Working Group Treasurer
Mark Nowell, IEEE P802.3cd Task Force Chair
Matt Brown, IEEE P802.3cd Task Force Editor-in-Chief
Arthur Marris, IEEE P802.3cd Task Force Editor
Gary Nicholl, IEEE P802.3cd Task Force Editor
Adee Ran, IEEE P802.3cd Task Force Editor
Jonathan King,1 IEEE P802.3cd Task Force Editor
Peter Stassar, IEEE P802.3cd Task Force Editor
Justin Abbott
David Abramson
Dale Amason
Eric Baden
Amrik Bains
Thananya Baldwin
Denis Beaudoin
Christian Beia
Vipul Bhatt
William Bliss
Mark Bohm
Brad Booth
Martin Bouda
David Brandt
Ralf-Peter Braun
Theodore Brillhart
Paul Brooks
Phillip Brownlee
Chris Bullock
Jairo Bustos Heredia
Adrian Butter
Anthony Calbone
Clark Carty
Craig Chabot
Mandeep Chadha
David Chalupsky
Jacky Chang
Xin Chang
Chan Chen
Weiying Cheng
Golam Choudhury
Keng Hua Chuang
Christopher R. Cole
John D’Ambrosia
Piers J. G. Dawe
Fred Dawson
Eric DiBiaso
John Dillard
Chris Diminico
Curtis Donahue
Michael Dudek
Frank Effenberger
John Ewen
Ramin Farjad
Shahar Feldman
Matthias Fritsche
Richard Frosch
Andrew Gardner
Ali Ghiasi
Steven Gorshe
Steffen Graber
Olaf Grau
Robert M. Grow
Yong Guo
Mark Gustlin
Marek Hajduczenia
Tomohiro Hashimoto
Akinori Hayakawa
Rajmohan Hegde
David Hess
Yasuo Hidaka
David Hoglund
Rita Horner
Bernd Horrmeyer
Xi Huang
Xingang Huang
Yasuhiro Hyakutake
Jonathan Ingham
Kazuhiko Ishibe
Hideki Isono
Tom Issenhuth
Kenneth Jackson
Andrew Jimenez
John Johnson
Chad Jones
Peter Jones
Upen Kareti
Yasuaki Kawatsu
Yongbum Kim
Mark Kimber
Scott Kipp
Michael Klempa
Curtis Knittle
Shigeru Kobayashi
Paul Kolesar
Toshihiko Kusano
Hans Lackner
Jeffrey Lapak
Mark Laubach
Greg Le Cheminant
Hanan Leizerovich
David Lewis
Jon Lewis
Mike Peng Li
Robert Lingle
Hai-Feng Liu
Zhenyu Liu
Moiz Lokhandwala
Miklos Lukacs
Kent Lusted
Zahy Madgar
Jeffery Maki
David Malicoat
Takeo Masuda
Kirsten Matheus
Erdem Matoglu
1Not a member of the IEEE 802.3 working group at the beginning of the working group ballot.
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Mick McCarthy
Brett McClellan
Thomas McDermott
John McDonough
Larry McMillan
Greg McSorley
Marcel Medina
Richard Mei
Richard Mellitz
Phil Miguelez
Paul Mooney
Ron Muir Dale Murray
Henry Muyshondt
Edward Nakamoto
Kevin Noll
David Ofelt
Thomas Palkert
Sujan Pandey
Sesha Panguluri
Earl Parsons
Wanquan Peng
Ruben Perez De Aranda Alonso
Michael Peters
Jean Picard
David Piehler
Rick Pimpinella
William Powell
Rick Rabinovich
Alon Regev
Duane Remein
Salvatore Rotolo
Sam Sambasivan
Edward Sayre
Fred Schindler
Masood Shariff
Kapil Shrikhande
Jeff Slavick
Daniel Smith
Scott Sommers
Yoshiaki Sone
Bryan Sparrowhawk
Atul Srivastava
Heath Stewart
David Stover
Ken-Ichi Suzuki
Steve Swanson
Andre Szczepanek
William Szeto
Bharat Tailor
Takayuki Tajima
Tomoo Takahara
Kohichi Tamura
Nathan Tracy
Matthew Traverso
David Tremblay
Stephen Trowbridge
Yoshihiro Tsukamoto
Ed Ulrichs
Alexander Umnov
Sterling A. Vaden
Stefano Valle
Paul Vanderlaan
Dylan Walker
Roy Wang
Tongtong Wang
Xinyuan Wang
Matthias Wendt
Oded Wertheim
Natalie Wienckowski
Ludwig Winkel
Peter Wu
Dayin Xu
Yu Xu
Lennart Yseboodt
Hayato Yuki
Andrew Zambell
Huanlin Zhang
Qiwen Zhong
Yan Zhuang
George Zimmerman
Helge Zinner
Pavel Zivny
The following members of the individual balloting committee voted on this amendment. Balloters may have
voted for approval, disapproval, or abstention.
Thomas Alexander
Richard Alfvin
Arne Alping
Pete Anslow
Butch Anton
Eric Baden
John Ballingall
Ralf-Peter Braun
Nancy Bravin
Theodore Brillhart
Matt Brown
Demetrio Bucaneg
Gary Burrell
Jairo Bustos Heredia
William Byrd
John Calvin
Steven B. Carlson
Juan Carreon
Clark Carty
Chan Chen
Keith Chow
Keng Hua Chuang
Charles Cook
Piers J. G. Dawe
Stephen Didde
Michael Dudek
Sourav Dutta
Jason Ellison
Brian Franchuk
Avraham Freedman
Yukihiro Fujimoto
Zhigang Gong
Eric W. Gray
Randall Groves
Mark Gustlin
Adam Healey
Marco Hernandez
David Hess
Yasuo Hidaka
Werner Hoelzl
Rita Horner
Noriyuki Ikeuchi
Sergiu Iordanescu
Osamu Ishida
Atsushi Ito
Raj Jain
SangKwon Jeong
Peter Jones
Manabu Kagami
Piotr Karocki
Stuart Kerry
Yongbum Kim
Jonathan King
Paul Kolesar
Mark Laubach
David J. Law
Hyeong Ho Lee
Hanan Leizerovich
David Lewis
Jon Lewis
Robert Lingle
Hai-Feng Liu
Kent Lusted
Michael Lynch
Elvis Maculuba
Valerie Maguire
Jeffery Maki
Arthur Marris
Michael Maytum
Mick McCarthy
Brett McClellan
Thomas McDermott
Richard Mellitz
Tremont Miao
Charles Moorwood
Rick Murphy
Michael Newman
Charles Ngethe
Gary Nicholl
Nick S. A. Nikjoo
Mark Nowell
Satoshi Obara
Thomas Palkert
Bansi Patel
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