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ZYNQ7000 XC7Z035开发板原理图.pdf

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    5 4 3 2 1 D C B A D C B A ALINX Confidential 5 4 3 2 http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: PAGE01 Block diagram PAGE01 Block diagram PAGE01 Block diagram Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 1 1 1 of of of 26 26 26
    D C B A 5 4 3 2 1 +3.3V +1.8V +3.3V C1 47uF V12 V14 V15 W8 U8 V8 V13 FPGA_DONE W9 FPGA_PROG_B V9 BANK0 U1-1 VCCO_0 VCCO_0 VCCBATT_0 RSVDVCC1 RSVDVCC3 RSVDVCC2 RSVDGND DONE_0 VCCADC_0 VREFP_0 VREFN_0 VP_0 VN_0 DXP_0 DXN_0 PROGRAM_B_0 GNDADC_0 M14 P14 N13 N14 P13 R14 R13 M13 R1 4.7K 3 FPGA_DONE 19 FPGA_TDO +3.3V FPGA_TDI FPGA_TDO FPGA_TCK FPGA_TMS +3.3V R2 4.7K T7 V11 W10 W12 W11 R8 CFGBVS_0 TDI_0 TDO_0 TCK_0 TMS_0 INIT_B_0 AVCC AGND +1.8V BLM18SG121TN1 L1 C2 0.1uF C3 470nF AGND AGND L2 BLM18SG121TN1 xc7z035ffg676-2_0 AGND J16 VCC D- D+ ID GND 1 H S 2 H S 3 H S 4 H S 1 2 3 4 5 6 7 8 9 MINI_USB +3P3OUTV USB_5V C557 4.7uF C553 0.1uF C554 0.1uF C555 0.1uF USB_5V C552 10uF +3P3V R268 10K C556 0.1uF C541 27pF R271 12.1K 1% EECS EECLK EEDATA Y6 12MHZ 2 4 1 3 C540 27pF 40 39 38 37 6 7 34 5 45 44 43 1 2 42 VPLL +3P3V VPHY U45 3 8 VREGIN Y H P V L L P V VCCD VCCCORE VCCA DM DP RESET REF EECS EECLK EEDATA XCSI XCSO TEST 1 D N G A 2 D N G A 3 D N G A 4 9 1 4 2 1 4 2 6 4 I I 1 O C C V 2 O C C V I 3 O C C V ADBUS0/TCK ADBUS1/TDI ADBUS2/TDO ADBUS3/TMS ADBUS4 ADBUS5 ADBUS6 ADBUS7 ACBUS0 ACBUS1 ACBUS2 ACBUS3 ACBUS4 ACBUS5 ACBUS6 ACBUS7 ACBUS8 ACBUS9 R269 R270 R267 R266 33R 33R 33R 33R FPGA_TCK FPGA_TDI JTAG_TDO FPGA_TMS FPGA_TCK JTAG_TDO FPGA_TMS 19 19 19 13 14 15 16 17 18 19 20 21 25 26 27 28 29 30 31 32 33 1 D N G 2 D N G 3 D N G 4 D N G 5 D N G 6 D N G 7 D N G 8 D N G 0 1 1 1 2 2 3 2 5 3 6 3 7 4 8 4 FT232HL +3P3V R262 10K R263 10K R264 10K R265 2K EECS EECLK EEDATA +3P3V C542 0.1uF U12 8 VCC 7 6 NC1 5 NC2 VSS 1 2 3 4 CS CLK DI DO 93LC56BISN +3P3OUTV +3P3V L33 BLM18SG121TN1 +3P3OUTV VPLL +3P3OUTV VPHY L34 BLM18SG121TN1 L35 BLM18SG121TN1 C543 0.1uF C544 0.1uF C549 0.1uF C550 0.1uF C551 0.1uF C545 0.1uF C546 0.1uF C547 0.1uF C548 0.1uF ALINX Confidential 5 4 3 2 http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: Page02 Z7 Bank0 Page02 Z7 Bank0 Page02 Z7 Bank0 Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 2 2 2 of of of 26 26 26 D C B A
    D C B A 5 4 3 2 1 +3.3V BOOT OPTION +3.3V C4 100uF C5 4.7uF C6 470nF C7 470nF OTG_RESET QSPI_D0 QSPI_D1 QSPI_SCK PHY1_RESET MIO[8] =1 ----MIO bank1 voltage=1.8V MIO[2] =0 ----cascaded JTAG MIO[3] =0 ----JTAG/NAND/Quad-SPI/SD MIO[6] =0 ----PLL used MIO[7] =0 ----MIO bank0 voltage=3.3V R12 R13 R14 R16 R18 20K 20K 20K 20K 20K +3.3V +3.3V C8 0.1uF 4 1 X4 VDD OUT OE GND 33.333333Mhz 3 2 U1-2 VCC3V3 BANK500 A26 B23 E24 B24 VCCO_MIO0_500 VCCO_MIO0_500 VCCO_MIO0_500 PS_CLK_500 PS_POR_B_500 R17 33R PS_CLK PS_POR_B C23 12 12 12 QSPI_CS QSPI_D0 QSPI_D1 MIO0_LED QSPI_CS QSPI_D0 QSPI_D1 E26 D26 E25 D25 PS_MIO0_500 PS_MIO1_500 PS_MIO2_500 PS_MIO3_500 QSPI_D2 QSPI_D3 33R QSPI_SCK PHY1_RESET OTG_RESET SD_CD PS_KEY UART_TXD UART_RXD QSPI_D2 QSPI_D3 QSPI_SCK PHY1_RESET OTG_RESET SD_CD UART_TXD UART_RXD 12 12 12 13 14 15 15 15 R15 PS_MIO4_500 PS_MIO5_500 PS_MIO6_500 PS_MIO7_500 PS_MIO8_500 PS_MIO9_500 PS_MIO10_500 PS_MIO11_500 PS_MIO12_500 PS_MIO13_500 PS_MIO14_500 PS_MIO15_500 F24 C26 F23 E23 A24 D24 A25 B26 A23 B25 D23 C24 xc7z035ffg676-2_0 R19 10K R20 10K R21 R22 20K 20K QSPI_D3 QSPI_D2 SW1 SW DIP-2 Boot Mode JTAG NAND QSPI-FLASH SD Card MIO[5] (QSPI_D3) 0 0 1 1 POWER ON RESET MIO[4] (QSPI_D2 ) 0 1 0 1 +3.3V +3.3V R26 1K 1% C15 0.01uF KEY1 POR RST 3 1 U3 #MR VDD GND #RESET 4 2 TCM811TERCTR C16 0.1uF R28 4.7K PS_POR_B Power LED +3.3V R7 330R D5 LED ALINX Confidential FPGA DONE LED +3.3V D6 R8 220 FPGA_DONE R9 330R LED 2 FPGA_DONE +1.8V +1.8V U1-3 R25 1K 1% C13 C9 C14 C10 C11 C12 100uF 4.7uF 4.7uF 470nF 470nF 470nF C20 D17 F21 G18 K18 H18 PS_SRST_B A22 VCCO_MIO1_501 VCCO_MIO1_501 VCCO_MIO1_501 VCCO_MIO1_501 VCCO_MIO1_501 PS_MIO_VREF_501 PS_SRST_B_501 13 13 13 13 13 13 13 13 13 13 13 13 14 14 PHY1_TXCK PHY1_TXD0 PHY1_TXD1 PHY1_TXD2 PHY1_TXD3 PHY1_TXCTL PHY1_RXCK PHY1_RXD0 PHY1_RXD1 PHY1_RXD2 PHY1_RXD3 PHY1_RXCTL OTG_DATA4 OTG_DIR PHY1_TXCK PHY1_TXD0 PHY1_TXD1 PHY1_TXD2 PHY1_TXD3 PHY1_TXCTL PHY1_RXCK PHY1_RXD0 PHY1_RXD1 PHY1_RXD2 PHY1_RXD3 PHY1_RXCTL OTG_DATA4 OTG_DIR G21 G17 PS_MIO16_501 G20 PS_MIO17_501 G19 PS_MIO18_501 H19 PS_MIO19_501 F22 PS_MIO20_501 G22 PS_MIO21_501 F20 PS_MIO22_501 J19 PS_MIO23_501 F19 PS_MIO24_501 H17 PS_MIO25_501 F18 PS_MIO26_501 J18 PS_MIO27_501 E20 PS_MIO28_501 PS_MIO29_501 +1.8V R30 10K 1% PS_SRST_B VCC1V8 BANK501 PS_MIO30_501 PS_MIO31_501 PS_MIO32_501 PS_MIO33_501 PS_MIO34_501 PS_MIO35_501 PS_MIO36_501 PS_MIO37_501 PS_MIO38_501 PS_MIO39_501 PS_MIO40_501 PS_MIO41_501 PS_MIO42_501 PS_MIO43_501 PS_MIO44_501 PS_MIO45_501 PS_MIO46_501 PS_MIO47_501 PS_MIO48_501 PS_MIO49_501 PS_MIO50_501 PS_MIO51_501 PS_MIO52_501 PS_MIO53_501 K19 E21 K17 E22 J16 D19 K16 D20 D21 C21 C22 C19 F17 D18 E18 C18 E17 B19 B21 A18 B22 B20 A20 A19 xc7z035ffg676-2_0 OTG_STP OTG_NXT OTG_DATA0 OTG_DATA1 OTG_DATA2 OTG_DATA3 OTG_CLK OTG_DATA5 OTG_DATA6 OTG_DATA7 40.2 1% SD_CMD SD_D0 SD_D1 SD_D2 SD_D3 MMC_DAT0 MMC_CMD 40.2 1% MMC_DAT1 MMC_DAT2 MMC_DAT3 PHY1_MDC PHY1_MDIO R27 R29 OTG_STP OTG_NXT OTG_DATA0 OTG_DATA1 OTG_DATA2 OTG_DATA3 OTG_CLK OTG_DATA5 OTG_DATA6 OTG_DATA7 SD_CLK SD_CMD SD_D0 SD_D1 SD_D2 SD_D3 MMC_DAT0 MMC_CMD MMC_CCLK MMC_DAT1 MMC_DAT2 MMC_DAT3 PHY1_MDC PHY1_MDIO 14 14 14 14 14 14 14 14 14 14 15 15 15 15 15 15 12 12 12 12 12 12 13 13 SD_CLK MMC_CCLK +3.3V R285 10K KEY3 1 P1 P2 2 Button 5 4 3 2 PS LED +3.3V PS_KEY R284 1K MIO0_LED R10 330R D7 LED http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: PAGE03 Z7 MIO-Config PAGE03 Z7 MIO-Config PAGE03 Z7 MIO-Config Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 3 3 3 of of of 26 26 26 D C B A
    5 4 3 2 1 VADJ BANK12 VCCIO C17 100uF C18 4.7uF C19 4.7uF C20 4.7uF C21 470nF C22 470nF C23 470nF C24 470nF C25 470nF 16 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 PLL_SCL FMC_LA08_P FMC_LA08_N FMC_LA10_P FMC_LA10_N FMC_LA02_P FMC_LA02_N FMC_LA07_P FMC_LA07_N FMC_LA12_P FMC_LA12_N FMC_LA04_P FMC_LA04_N FMC_LA11_P FMC_LA11_N FMC_LA06_P FMC_LA06_N PLL_SCL FMC_LA08_P FMC_LA08_N FMC_LA10_P FMC_LA10_N FMC_LA02_P FMC_LA02_N FMC_LA07_P FMC_LA07_N FMC_LA12_P FMC_LA12_N FMC_VREF FMC_LA04_P FMC_LA04_N FMC_LA11_P FMC_LA11_N FMC_LA06_P FMC_LA06_N AA16 AB13 AC10 AD17 AE14 AF11 W14 Y12 Y11 AB12 AC11 Y10 AA10 AB11 AB10 W13 Y13 AA13 AA12 AE10 AD10 AE12 AF12 AE11 AF10 U1-4 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 VCCO_12 IO_0_12 IO_L1P_T0_12 IO_L1N_T0_12 IO_L2P_T0_12 IO_L2N_T0_12 IO_L3P_T0_DQS_12 IO_L3N_T0_DQS_12 IO_L4P_T0_12 IO_L4N_T0_12 IO_L5P_T0_12 IO_L5N_T0_12 IO_L6P_T0_12 IO_L6N_T0_VREF_12 IO_L7P_T1_12 IO_L7N_T1_12 IO_L8P_T1_12 IO_L8N_T1_12 IO_L9P_T1_DQS_12 IO_L9N_T1_DQS_12 BANK12 IO_L10P_T1_12 IO_L10N_T1_12 IO_L11P_T1_SRCC_12 IO_L11N_T1_SRCC_12 IO_L12P_T1_MRCC_12 IO_L12N_T1_MRCC_12 IO_L13P_T2_MRCC_12 IO_L13N_T2_MRCC_12 IO_L14P_T2_SRCC_12 IO_L14N_T2_SRCC_12 IO_L15P_T2_DQS_12 IO_L15N_T2_DQS_12 IO_L16P_T2_12 IO_L16N_T2_12 IO_L17P_T2_12 IO_L17N_T2_12 IO_L18P_T2_12 IO_L18N_T2_12 IO_L19P_T3_12 IO_L19N_T3_VREF_12 IO_L20P_T3_12 IO_L20N_T3_12 IO_L21P_T3_DQS_12 IO_L21N_T3_DQS_12 IO_L22P_T3_12 IO_L22N_T3_12 IO_L23P_T3_12 IO_L23N_T3_12 IO_L24P_T3_12 IO_L24N_T3_12 IO_25_12 xc7z035ffg676-2_0 BANK13 VCCIO C26 100uF C32 4.7uF C27 4.7uF C28 4.7uF C33 470nF C29 470nF C30 470nF C31 470nF C34 470nF VADJ U1-5 BANK13 AA26 AB23 AC20 AE24 AF21 Y19 V19 AA25 AB25 AB26 AC26 AE25 AE26 AD25 AD26 AF24 AF25 AA24 AB24 AE22 AF22 AE23 AF23 AB21 AB22 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 VCCO_13 IO_0_13 IO_L1P_T0_13 IO_L1N_T0_13 IO_L2P_T0_13 IO_L2N_T0_13 IO_L3P_T0_DQS_13 IO_L3N_T0_DQS_13 IO_L4P_T0_13 IO_L4N_T0_13 IO_L5P_T0_13 IO_L5N_T0_13 IO_L6P_T0_13 IO_L6N_T0_VREF_13 IO_L7P_T1_13 IO_L7N_T1_13 IO_L8P_T1_13 IO_L8N_T1_13 IO_L9P_T1_DQS_13 IO_L9N_T1_DQS_13 IO_L10P_T1_13 IO_L10N_T1_13 IO_L11P_T1_SRCC_13 IO_L11N_T1_SRCC_13 IO_L12P_T1_MRCC_13 IO_L12N_T1_MRCC_13 IO_L13P_T2_MRCC_13 IO_L13N_T2_MRCC_13 IO_L14P_T2_SRCC_13 IO_L14N_T2_SRCC_13 IO_L15P_T2_DQS_13 IO_L15N_T2_DQS_13 IO_L16P_T2_13 IO_L16N_T2_13 IO_L17P_T2_13 IO_L17N_T2_13 IO_L18P_T2_13 IO_L18N_T2_13 IO_L19P_T3_13 IO_L19N_T3_VREF_13 IO_L20P_T3_13 IO_L20N_T3_13 IO_L21P_T3_DQS_13 IO_L21N_T3_DQS_13 IO_L22P_T3_13 IO_L22N_T3_13 IO_L23P_T3_13 IO_L23N_T3_13 IO_L24P_T3_13 IO_L24N_T3_13 IO_25_13 xc7z035ffg676-2_0 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 19 FMC_SCL FMC_LA33_P FMC_LA33_N FMC_LA32_P FMC_LA32_N FMC_LA31_P FMC_LA31_N FMC_LA30_P FMC_LA30_N FMC_LA29_P FMC_LA29_N FMC_SDA FMC_LA26_P FMC_LA26_N FMC_LA24_P FMC_LA24_N FMC_LA25_P FMC_LA25_N FMC_SCL FMC_LA33_P FMC_LA33_N FMC_LA32_P FMC_LA32_N FMC_LA31_P FMC_LA31_N FMC_LA30_P FMC_LA30_N FMC_LA29_P FMC_LA29_N FMC_SDA FMC_VREF FMC_LA26_P FMC_LA26_N FMC_LA24_P FMC_LA24_N FMC_LA25_P FMC_LA25_N AE13 AF13 AC12 AD11 AC13 AD13 AC14 AD14 AB15 AB14 AD16 AD15 AF15 AF14 AE16 AE15 AE17 AF17 Y17 AA17 AB17 AB16 AC17 AC16 AA15 AA14 Y16 Y15 W16 W15 W17 AA22 AA23 AD23 AD24 AC23 AC24 AD20 AD21 AC21 AC22 AF19 AF20 AE20 AE21 AD18 AD19 AE18 AF18 W20 Y20 AA20 AB20 AC18 AC19 AA19 AB19 W18 W19 Y18 AA18 V18 19 FMC_LA09_P 19 FMC_LA09_N 19 FMC_LA05_P 19 FMC_LA05_N 19 FMC_CLK0_P 19 FMC_CLK0_N FMC_LA00_CC_P 19 FMC_LA00_CC_N 19 FMC_LA01_CC_P 19 FMC_LA01_CC_N 19 19 FMC_LA13_P 19 FMC_LA13_N 19 FMC_LA14_P 19 FMC_LA14_N 19 FMC_LA03_P 19 FMC_LA03_N 19 FMC_LA15_P 19 FMC_LA15_N 16 PLL_SDA 19 FMC_VREF 19 FMC_LA16_P 19 FMC_LA16_N 16 REF_CLK_C_P FMC_LA09_P FMC_LA09_N FMC_LA05_P FMC_LA05_N FMC_CLK0_P FMC_CLK0_N FMC_LA00_CC_P FMC_LA00_CC_N FMC_LA01_CC_P FMC_LA01_CC_N FMC_LA13_P FMC_LA13_N FMC_LA14_P FMC_LA14_N FMC_LA03_P FMC_LA03_N FMC_LA15_P FMC_LA15_N PLL_SDA FMC_VREF FMC_LA16_P FMC_LA16_N REF_CLK_C_P SFP1_TX_DIS_LS SFP2_TX_DIS_LS SFP1_RX_LOSS_LS SFP2_RX_LOSS_LS 19 FMC_LA28_P 19 FMC_LA28_N FMC_LA18_CC_P 19 FMC_LA18_CC_N 19 FMC_LA17_CC_P 19 FMC_LA17_CC_N 19 19 FMC_CLK1_P 19 FMC_CLK1_N 19 FMC_LA27_P 19 FMC_LA27_N 19 FMC_LA20_P 19 FMC_LA20_N 19 FMC_LA19_P 19 FMC_LA19_N 19 FMC_LA22_P 19 FMC_LA22_N 19 FMC_LA23_P 19 FMC_LA23_N 19 FMC_PRSNT FMC_LA21_P FMC_LA21_N 19 19 FMC_LA28_P FMC_LA28_N FMC_LA18_CC_P FMC_LA18_CC_N FMC_LA17_CC_P FMC_LA17_CC_N FMC_CLK1_P FMC_CLK1_N FMC_LA27_P FMC_LA27_N FMC_LA20_P FMC_LA20_N FMC_LA19_P FMC_LA19_N FMC_LA22_P FMC_LA22_N FMC_LA23_P FMC_LA23_N FMC_PRSNT FMC_VREF FMC_LA21_P FMC_LA21_N PCIE_PERST_LS PCIE_PRSNT_LS VADJ SFP1_TX_DIS_LS SFP2_TX_DIS_LS SFP1_RX_LOSS_LS SFP2_RX_LOSS_LS C470 0.1uF 1 2 3 4 5 6 7 8 U49 VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 VCCB 1OE 2OE 1B1 1B2 2B1 2B2 GND1 GND2 74AVCH4T245D 16 15 14 13 12 11 10 9 +3.3V C471 0.1uF 20 20 SFP1_TX_DIS SFP2_TX_DIS SFP1_RX_LOSS 20 SFP2_RX_LOSS 20 VADJ +3.3V C590 0.1uF PCIE_PRSNT_LS PCIE_PERST_LS U50 VCCA A1 A2 GND 3 5 4 2 VCCB B1 B2 OE 7 8 1 6 TXS0102DCUR C592 0.1uF VADJ PCIE_PRSNT PCIE_PERST 21 21 D C B A D C B A ALINX Confidential 5 4 3 2 http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: PAGE04 Z7 Bank12 & Bank13 PAGE04 Z7 Bank12 & Bank13 PAGE04 Z7 Bank12 & Bank13 Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 4 4 4 of of of 26 26 26
    D C B A 5 4 +1.5V BANK33 1.5V 3 +1.5V BANK34 1.5V 2 1 C35 100uF C36 4.7uF C37 4.7uF C38 4.7uF C39 470nF C40 470nF C41 470nF C42 470nF C43 470nF C44 100uF C45 4.7uF C46 4.7uF C47 4.7uF C48 470nF C49 470nF C50 470nF C51 470nF C52 470nF PL_VTTREF C53 0.1uF C54 0.1uF +1.5V U1-6 +1.5V BANK33 M3 L6 VCCO_33 J2 VCCO_33 H5 VCCO_33 F1 VCCO_33 E4 VCCO_33 VCCO_33 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 PL_DDR3_D3 PL_DDR3_D1 PL_DDR3_D6 PL_DDR3_D4 PL_DDR3_DQS0_P PL_DDR3_DQS0_N PL_DDR3_D2 PL_DDR3_D7 PL_DDR3_D5 PL_DDR3_D0 PL_DDR3_DM0 PL_DDR3_D10 PL_DDR3_D8 PL_DDR3_D13 PL_DDR3_D11 PL_DDR3_DQS1_P PL_DDR3_DQS1_N PL_DDR3_D3 PL_DDR3_D1 PL_DDR3_D6 PL_DDR3_D4 PL_DDR3_DQS0_P PL_DDR3_DQS0_N PL_DDR3_D2 PL_DDR3_D7 PL_DDR3_D5 PL_DDR3_D0 PL_DDR3_DM0 PL_VTTREF PL_DDR3_D10 PL_DDR3_D8 PL_DDR3_D13 PL_DDR3_D11 PL_DDR3_DQS1_P PL_DDR3_DQS1_N L9 G4 F4 D4 D3 G2 F2 D1 C1 E2 E1 F3 E3 J1 H1 H4 H3 K2 K1 IO_0_VRN_33 IO_L1P_T0_33 IO_L1N_T0_33 IO_L2P_T0_33 IO_L2N_T0_33 IO_L3P_T0_DQS_33 IO_L3N_T0_DQS_33 IO_L4P_T0_33 IO_L4N_T0_33 IO_L5P_T0_33 IO_L5N_T0_33 IO_L6P_T0_33 IO_L6N_T0_VREF_33 IO_L7P_T1_33 IO_L7N_T1_33 IO_L8P_T1_33 IO_L8N_T1_33 IO_L9P_T1_DQS_33 IO_L9N_T1_DQS_33 IO_L10P_T1_33 IO_L10N_T1_33 IO_L11P_T1_SRCC_33 IO_L11N_T1_SRCC_33 IO_L12P_T1_MRCC_33 IO_L12N_T1_MRCC_33 IO_L13P_T2_MRCC_33 IO_L13N_T2_MRCC_33 IO_L14P_T2_SRCC_33 IO_L14N_T2_SRCC_33 IO_L15P_T2_DQS_33 IO_L15N_T2_DQS_33 IO_L16P_T2_33 IO_L16N_T2_33 IO_L17P_T2_33 IO_L17N_T2_33 IO_L18P_T2_33 IO_L18N_T2_33 IO_L19P_T3_33 IO_L19N_T3_VREF_33 IO_L20P_T3_33 IO_L20N_T3_33 IO_L21P_T3_DQS_33 IO_L21N_T3_DQS_33 IO_L22P_T3_33 IO_L22N_T3_33 IO_L23P_T3_33 IO_L23N_T3_33 IO_L24P_T3_33 IO_L24N_T3_33 IO_25_VRP_33 xc7z035ffg676-2_0 H2 G1 L3 K3 J4 J3 M6 M5 L5 L4 N3 N2 M2 L2 N4 M4 N1 M1 M7 L7 K5 J5 M8 L8 K6 J6 N7 N6 K8 K7 N8 PL_DDR3_D15 PL_DDR3_D9 PL_DDR3_D14 PL_DDR3_D12 PL_DDR3_DM1 PL_DDR3_D19 PL_DDR3_DM2 PL_DDR3_D17 PL_DDR3_D18 PL_DDR3_DQS2_P PL_DDR3_DQS2_N PL_DDR3_D20 PL_DDR3_D22 PL_DDR3_D21 PL_DDR3_D23 PL_DDR3_D16 PL_DDR3_D26 PL_VTTREF PL_DDR3_D29 PL_DDR3_D27 PL_DDR3_DQS3_P PL_DDR3_DQS3_N PL_DDR3_D31 PL_DDR3_D25 PL_DDR3_D24 PL_DDR3_DM3 PL_DDR3_D28 PL_DDR3_D30 PL_DDR3_D15 PL_DDR3_D9 PL_DDR3_D14 PL_DDR3_D12 PL_DDR3_DM1 11 11 11 11 11 11 PL_DDR3_D19 11 PL_DDR3_DM2 11 PL_DDR3_D17 11 PL_DDR3_D18 PL_DDR3_DQS2_P11 PL_DDR3_DQS2_N11 11 PL_DDR3_D20 11 PL_DDR3_D22 11 PL_DDR3_D21 11 PL_DDR3_D23 11 PL_DDR3_D16 PL_DDR3_D26 11 11 PL_DDR3_D29 11 PL_DDR3_D27 PL_DDR3_DQS3_P11 PL_DDR3_DQS3_N11 11 PL_DDR3_D31 11 PL_DDR3_D25 11 PL_DDR3_D24 11 PL_DDR3_DM3 11 PL_DDR3_D28 11 PL_DDR3_D30 +1.5V U1-7 +1.5V BANK34 +1.5V 80 1% R31 PL_DDR3_VRN 22 22 22 22 22 22 22 22 PL_LED4 PL_LED3 PL_KEY2 PL_KEY1 PL_KEY4 PL_KEY3 PL_LED1 PL_LED2 PL_LED4 PL_LED3 PL_KEY2 PL_KEY1 PL_KEY4 PL_KEY3 PL_LED1 PL_LED2 A6 B3 C10 D7 G8 K9 K11 J11 H11 G6 G5 H9 G9 H7 H6 J10 J9 J8 H8 F5 E5 D9 D8 F9 E8 VCCO_34 VCCO_34 VCCO_34 VCCO_34 VCCO_34 VCCO_34 IO_0_VRN_34 IO_L1P_T0_34 IO_L1N_T0_34 IO_L2P_T0_34 IO_L2N_T0_34 IO_L3P_T0_DQS_PUDC_B_34 IO_L3N_T0_DQS_34 IO_L4P_T0_34 IO_L4N_T0_34 IO_L5P_T0_34 IO_L5N_T0_34 IO_L6P_T0_34 IO_L6N_T0_VREF_34 IO_L7P_T1_34 IO_L7N_T1_34 IO_L8P_T1_34 IO_L8N_T1_34 IO_L9P_T1_DQS_34 IO_L9N_T1_DQS_34 IO_L10P_T1_34 IO_L10N_T1_34 IO_L11P_T1_SRCC_34 IO_L11N_T1_SRCC_34 IO_L12P_T1_MRCC_34 IO_L12N_T1_MRCC_34 IO_L13P_T2_MRCC_34 IO_L13N_T2_MRCC_34 IO_L14P_T2_SRCC_34 IO_L14N_T2_SRCC_34 IO_L15P_T2_DQS_34 IO_L15N_T2_DQS_34 IO_L16P_T2_34 IO_L16N_T2_34 IO_L17P_T2_34 IO_L17N_T2_34 IO_L18P_T2_34 IO_L18N_T2_34 IO_L19P_T3_34 IO_L19N_T3_VREF_34 IO_L20P_T3_34 IO_L20N_T3_34 IO_L21P_T3_DQS_34 IO_L21N_T3_DQS_34 IO_L22P_T3_34 IO_L22N_T3_34 IO_L23P_T3_34 IO_L23N_T3_34 IO_L24P_T3_34 IO_L24N_T3_34 IO_25_VRP_34 xc7z035ffg676-2_0 E6 D5 F8 E7 G7 F7 C8 C7 D6 C6 C9 B9 B10 A10 A9 A8 B7 A7 C4 C3 B5 B4 B6 A5 A4 A3 C2 B1 B2 A2 K10 FAN_PWM PL_DDR3_A4 PL_DDR3_A11 PL_DDR3_A6 PL_DDR3_A14 PL_DDR3_A8 CLK0_P CLK0_N PL_DDR3_A2 PL_DDR3_S0 PL_DDR3_A7 PL_DDR3_A3 PL_DDR3_A13 PL_DDR3_RESET PL_DDR3_A5 PL_DDR3_A0 PL_DDR3_BA0 PL_DDR3_A9 PL_DDR3_RAS PL_DDR3_BA1 PL_DDR3_WE PL_DDR3_CAS PL_DDR3_CLK0_P PL_DDR3_CLK0_N PL_DDR3_ODT PL_DDR3_BA2 PL_DDR3_A1 PL_DDR3_A12 PL_DDR3_CKE PL_DDR3_A10 PL_DDR3_VRP R32 26 FAN_PWM 11 PL_DDR3_A4 11 PL_DDR3_A11 11 PL_DDR3_A6 11 PL_DDR3_A14 11 PL_DDR3_A8 16 CLK0_P 16 CLK0_N 11 PL_DDR3_A2 11 PL_DDR3_S0 11 PL_DDR3_A7 11 PL_DDR3_A3 11 PL_DDR3_A13 PL_DDR3_RESET 11 11 PL_DDR3_A5 11 PL_DDR3_A0 11 PL_DDR3_BA0 11 PL_DDR3_A9 11 PL_DDR3_RAS 11 PL_DDR3_BA1 11 PL_DDR3_WE 11 PL_DDR3_CAS PL_DDR3_CLK0_P11 PL_DDR3_CLK0_N11 11 PL_DDR3_ODT 11 PL_DDR3_BA2 11 PL_DDR3_A1 11 PL_DDR3_A12 11 PL_DDR3_CKE 11 PL_DDR3_A10 80 1% ALINX Confidential 5 4 3 2 http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: PAGE05 Z7 Bank33 & Bank34 PAGE05 Z7 Bank33 & Bank34 PAGE05 Z7 Bank33 & Bank34 Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 5 5 5 of of of 26 26 26 D C B A
    5 4 3 2 1 +1.8V C55 100uF C56 4.7uF C57 4.7uF C58 4.7uF C59 470nF C60 470nF C61 470nF C62 470nF C63 470nF +1.8V U1-8 +1.8V BANK35 A16 B13 E14 F11 H15 J12 H16 F12 E12 E10 D10 G10 F10 E11 D11 G12 G11 F13 E13 H13 H12 K13 J13 K15 J15 VCCO_35 VCCO_35 VCCO_35 VCCO_35 VCCO_35 VCCO_35 IO_0_VRN_35 IO_L1P_T0_AD0P_35 IO_L1N_T0_AD0N_35 IO_L2P_T0_AD8P_35 IO_L2N_T0_AD8N_35 IO_L3P_T0_DQS_AD1P_35 IO_L3N_T0_DQS_AD1N_35 IO_L4P_T0_35 IO_L4N_T0_35 IO_L5P_T0_AD9P_35 IO_L5N_T0_AD9N_35 IO_L6P_T0_35 IO_L6N_T0_VREF_35 IO_L7P_T1_AD2P_35 IO_L7N_T1_AD2N_35 IO_L8P_T1_AD10P_35 IO_L8N_T1_AD10N_35 IO_L9P_T1_DQS_AD3P_35 IO_L9N_T1_DQS_AD3N_35 PHY2_MDC PHY2_RXD1 PHY2_RXD2 PHY2_TXD3 PHY2_TXD2 PHY2_TXD1 PHY2_TXD0 PHY2_TXCTL PHY2_TXCK PHY2_RXD3 PHY2_RXD0 PHY2_RXCTL PHY2_MDIO PHY2_RESET 18 18 18 18 18 18 18 18 18 18 18 18 18 18 17 17 17 17 PHY2_MDC PHY2_RXD1 PHY2_RXD2 PHY2_TXD3 PHY2_TXD2 PHY2_TXD1 PHY2_TXD0 PHY2_TXCTL PHY2_TXCK PHY2_RXD3 PHY2_RXD0 PHY2_RXCTL PHY2_MDIO PHY2_RESET HDMI_CLK HDMI_D8 HDMI_DE HDMI_D2 IO_L10P_T1_AD11P_35 IO_L10N_T1_AD11N_35 IO_L11P_T1_SRCC_35 IO_L11N_T1_SRCC_35 IO_L12P_T1_MRCC_35 IO_L12N_T1_MRCC_35 IO_L13P_T2_MRCC_35 IO_L13N_T2_MRCC_35 IO_L14P_T2_AD4P_SRCC_35 IO_L14N_T2_AD4N_SRCC_35 IO_L15P_T2_DQS_AD12P_35 IO_L15N_T2_DQS_AD12N_35 IO_L16P_T2_35 IO_L16N_T2_35 IO_L17P_T2_AD5P_35 IO_L17N_T2_AD5N_35 IO_L18P_T2_AD13P_35 IO_L18N_T2_AD13N_35 IO_L19P_T3_35 IO_L19N_T3_VREF_35 IO_L20P_T3_AD6P_35 IO_L20N_T3_AD6N_35 IO_L21P_T3_DQS_AD14P_35 IO_L21N_T3_DQS_AD14N_35 IO_L22P_T3_AD7P_35 IO_L22N_T3_AD7N_35 IO_L23P_T3_35 IO_L23N_T3_35 IO_L24P_T3_AD15P_35 IO_L24N_T3_AD15N_35 IO_25_VRP_35 xc7z035ffg676-2_0 G16 G15 G14 F14 J14 H14 D15 D14 F15 E15 C17 C16 E16 D16 B16 B15 B17 A17 D13 C13 C14 B14 A15 A14 C12 B12 C11 B11 A13 A12 K12 PHY2_RXCK CLK_50MHZ HDMI_SPDIFOUT_B HDMI_D0 HDMI_D5 PHY2_RXCK HDMI_D6 HDMI_D7 HDMI_D17 HDMI_D16 HDMI_D4 HDMI_D3 HDMI_INT HDMI_SDA HDMI_D1 HDMI_D22 HDMI_D23 HDMI_D21 HDMI_SCL HDMI_D12 HDMI_D14 HDMI_SPDIF HDMI_D19 HDMI_D20 HDMI_D18 HDMI_D11 HDMI_VSYNC HDMI_HSYNC HDMI_D10 HDMI_D15 HDMI_D13 HDMI_D9 17 17 18 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 17 +1.8V C581 0.1uF HDMI_SPDIFOUT_B +3.3V C580 0.1uF U48 1 2 3 VCCA VCCB GND A DIR B 6 5 4 SN74LVC1T45DBVR HDMI_SPDIFOUT 17 +1.8V 33R R141 3 2 X3 VCC OUT OE GND 50MHz 4 1 1K R142 C354 0.1uF D C B A D C B A ALINX Confidential 5 4 3 2 http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: PAGE06 Z7 Bank35 PAGE06 Z7 Bank35 PAGE06 Z7 Bank35 Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 6 6 6 of of of 26 26 26
    5 4 3 2 1 D C B A C64 0.1uF C65 0.1uF FMC_GBTCLK0_M2C_P FMC_GBTCLK0_M2C_N FMC_GBTCLK0_M2C_P FMC_GBTCLK0_M2C_N 19 19 MGTAVTT 100 1% R33 AB7 AB8 Trace length from the resistor pins to the FPGA pins MGTRREF and MGTAVTTRCAL Connection must be equal in length U1-9 BANK111 MGTXTXP0_111 MGTXTXN0_111 MGTXRXP0_111 MGTXRXN0_111 MGTXTXP1_111 MGTXTXN1_111 MGTXRXP1_111 MGTXRXN1_111 MGTXTXP2_111 MGTXTXN2_111 MGTXRXP2_111 MGTXRXN2_111 MGTXTXP3_111 MGTXTXN3_111 MGTXRXP3_111 MGTXRXN3_111 MGTREFCLK0P_111 MGTREFCLK0N_111 MGTREFCLK1P_111 MGTREFCLK1N_111 BANK112 MGTAVTTRCAL_112 MGTRREF_112 MGTXTXP0_112 MGTXTXN0_112 MGTXRXP0_112 MGTXRXN0_112 MGTXTXP1_112 MGTXTXN1_112 MGTXRXP1_112 MGTXRXN1_112 MGTXTXP2_112 MGTXTXN2_112 MGTXRXP2_112 MGTXRXN2_112 MGTXTXP3_112 MGTXTXN3_112 MGTXRXP3_112 MGTXRXN3_112 MGTREFCLK0P_112 MGTREFCLK0N_112 MGTREFCLK1P_112 MGTREFCLK1N_112 xc7z035ffg676-2_0 FMC_DP0_C2M_P FMC_DP0_C2M_N FMC_DP0_M2C_P FMC_DP0_M2C_N SFP1_TX_P SFP1_TX_N SFP1_RX_P SFP1_RX_N SFP2_TX_P SFP2_TX_N SFP2_RX_P SFP2_RX_N SMA_TX_P SMA_TX_N SMA_RX_P SMA_RX_N FMC_DP0_C2M_P 19 FMC_DP0_C2M_N 19 FMC_DP0_M2C_P 19 FMC_DP0_M2C_N 19 20 SFP1_TX_P 20 SFP1_TX_N 20 SFP1_RX_P 20 SFP1_RX_N 20 SFP2_TX_P 20 SFP2_TX_N 20 SFP2_RX_P 20 SFP2_RX_N 21 SMA_TX_P 21 SMA_TX_N 21 SMA_RX_P 21 SMA_RX_N FMC_GBTCLK0_M2C_C_P FMC_GBTCLK0_M2C_C_N SFP_CLK0_C_P SFP_CLK0_C_N PCIE_TX0_P PCIE_TX0_N PCIE_RX0_P PCIE_RX0_N PCIE_TX1_P PCIE_TX1_N PCIE_RX1_P PCIE_RX1_N PCIE_TX2_P PCIE_TX2_N PCIE_RX2_P PCIE_RX2_N PCIE_TX3_P PCIE_TX3_N PCIE_RX3_P PCIE_RX3_N 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 PCIE_CLK0_C_P PCIE_CLK0_C_N AF8 AF7 AD8 AD7 AF4 AF3 AE6 AE5 AE2 AE1 AC6 AC5 AC2 AC1 AD4 AD3 W6 W5 AA6 AA5 AA2 AA1 AB4 AB3 W2 W1 Y4 Y3 U2 U1 V4 V3 R2 R1 T4 T3 R6 R5 U6 U5 16 SFP_CLK0_P SFP_CLK0_P 16 SFP_CLK0_N SFP_CLK0_N 16 PCIE_CLK0_P PCIE_CLK0_P 16 PCIE_CLK0_N PCIE_CLK0_N R34 NC R35 NC C66 0.1uF C67 0.1uF C68 0.1uF C69 0.1uF SFP_CLK0_C_P SFP_CLK0_C_N PCIE_CLK0_C_P PCIE_CLK0_C_N http://www.alinx.com.cn D C B A ALINX Confidential 5 4 3 2 Title Title Title Size Size Size Date: Date: Date: PAGE07 Z7 Bank111 & Bank112 PAGE07 Z7 Bank111 & Bank112 PAGE07 Z7 Bank111 & Bank112 Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 7 7 7 Rev Rev Rev 1.0 1.0 1.0 of of of 26 26 26
    5 4 3 2 1 +1.5V C70 100uF C71 100uF C72 4.7uF C73 4.7uF C74 4.7uF C75 470nF C76 470nF C77 470nF C78 470nF C79 470nF C80 470nF C81 470nF BANK502 PS_VTTREF +1.5V U1-10 C82 0.01uF C83 0.01uF 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 PS_DDR3_D0 PS_DDR3_D1 PS_DDR3_D2 PS_DDR3_D3 PS_DDR3_D4 PS_DDR3_D5 PS_DDR3_D6 PS_DDR3_D7 PS_DDR3_D8 PS_DDR3_D9 PS_DDR3_D10 PS_DDR3_D11 PS_DDR3_D12 PS_DDR3_D13 PS_DDR3_D14 PS_DDR3_D15 PS_DDR3_D16 PS_DDR3_D17 PS_DDR3_D18 PS_DDR3_D19 PS_DDR3_D20 PS_DDR3_D21 PS_DDR3_D22 PS_DDR3_D23 PS_DDR3_D24 PS_DDR3_D25 PS_DDR3_D26 PS_DDR3_D27 PS_DDR3_D28 PS_DDR3_D29 PS_DDR3_D30 PS_DDR3_D31 PS_DDR3_D0 PS_DDR3_D1 PS_DDR3_D2 PS_DDR3_D3 PS_DDR3_D4 PS_DDR3_D5 PS_DDR3_D6 PS_DDR3_D7 PS_DDR3_D8 PS_DDR3_D9 PS_DDR3_D10 PS_DDR3_D11 PS_DDR3_D12 PS_DDR3_D13 PS_DDR3_D14 PS_DDR3_D15 PS_DDR3_D16 PS_DDR3_D17 PS_DDR3_D18 PS_DDR3_D19 PS_DDR3_D20 PS_DDR3_D21 PS_DDR3_D22 PS_DDR3_D23 PS_DDR3_D24 PS_DDR3_D25 PS_DDR3_D26 PS_DDR3_D27 PS_DDR3_D28 PS_DDR3_D29 PS_DDR3_D30 PS_DDR3_D31 H25 J22 L26 M23 N20 R24 T21 V25 W22 K21 M21 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 VCCO_DDR_502 PS_DDR_VREF0_502 PS_DDR_VREF1_502 J26 F25 PS_DDR_DQ0_502 PS_DDR_DQ1_502 J25 G26 PS_DDR_DQ2_502 PS_DDR_DQ3_502 H26 H23 PS_DDR_DQ4_502 PS_DDR_DQ5_502 J24 J23 PS_DDR_DQ6_502 PS_DDR_DQ7_502 K26 L23 PS_DDR_DQ8_502 PS_DDR_DQ9_502 M26 K23 PS_DDR_DQ10_502 PS_DDR_DQ11_502 M25 N24 PS_DDR_DQ12_502 PS_DDR_DQ13_502 M24 N23 PS_DDR_DQ14_502 PS_DDR_DQ15_502 R26 PS_DDR_DQ16_502 P24 PS_DDR_DQ17_502 N26 PS_DDR_DQ18_502 P23 PS_DDR_DQ19_502 T24 PS_DDR_DQ20_502 T25 PS_DDR_DQ21_502 T23 PS_DDR_DQ22_502 R23 PS_DDR_DQ23_502 V24 PS_DDR_DQ24_502 U26 PS_DDR_DQ25_502 U24 PS_DDR_DQ26_502 U25 PS_DDR_DQ27_502 W26 PS_DDR_DQ28_502 Y25 PS_DDR_DQ29_502 Y26 PS_DDR_DQ30_502 W23 PS_DDR_DQ31_502 10 10 10 10 10 10 10 10 PS_DDR3_DQS0_P PS_DDR3_DQS0_N PS_DDR3_DQS1_P PS_DDR3_DQS1_N PS_DDR3_DQS2_P PS_DDR3_DQS2_N PS_DDR3_DQS3_P PS_DDR3_DQS3_N PS_DDR3_DQS0_P PS_DDR3_DQS0_N PS_DDR3_DQS1_P PS_DDR3_DQS1_N PS_DDR3_DQS2_P PS_DDR3_DQS2_N PS_DDR3_DQS3_P PS_DDR3_DQS3_N H24 G25 PS_DDR_DQS_P0_502 PS_DDR_DQS_N0_502 L24 L25 PS_DDR_DQS_P1_502 PS_DDR_DQS_N1_502 P25 R25 W24 W25 PS_DDR_DQS_P2_502 PS_DDR_DQS_N2_502 PS_DDR_DQS_P3_502 PS_DDR_DQS_N3_502 PS_DDR_A0_502 PS_DDR_A1_502 PS_DDR_A2_502 PS_DDR_A3_502 PS_DDR_A4_502 PS_DDR_A5_502 PS_DDR_A6_502 PS_DDR_A7_502 PS_DDR_A8_502 PS_DDR_A9_502 PS_DDR_A10_502 PS_DDR_A11_502 PS_DDR_A12_502 PS_DDR_A13_502 PS_DDR_A14_502 PS_DDR_BA0_502 PS_DDR_BA1_502 PS_DDR_BA2_502 PS_DDR_DM0_502 PS_DDR_DM1_502 PS_DDR_DM2_502 PS_DDR_DM3_502 PS_DDR_CKP_502 PS_DDR_CKN_502 PS_DDR_VRP_502 PS_DDR_VRN_502 PS_DDR_ODT_502 PS_DDR_CS_B_502 PS_DDR_CKE_502 PS_DDR_WE_B_502 PS_DDR_CAS_B_502 PS_DDR_RAS_B_502 PS_DDR_DRST_B_502 K22 K20 N21 L22 M20 N22 L20 J21 T20 U20 M22 H21 P20 J20 R20 U22 T22 R22 G24 K25 P26 V26 R21 P21 W21 V21 Y22 Y21 U21 V22 Y23 V23 H22 PS_DDR3_A0 PS_DDR3_A1 PS_DDR3_A2 PS_DDR3_A3 PS_DDR3_A4 PS_DDR3_A5 PS_DDR3_A6 PS_DDR3_A7 PS_DDR3_A8 PS_DDR3_A9 PS_DDR3_A10 PS_DDR3_A11 PS_DDR3_A12 PS_DDR3_A13 PS_DDR3_A14 PS_DDR3_BA0 PS_DDR3_BA1 PS_DDR3_BA2 PS_DDR3_DM0 PS_DDR3_DM1 PS_DDR3_DM2 PS_DDR3_DM3 PS_DDR3_A0 PS_DDR3_A1 PS_DDR3_A2 PS_DDR3_A3 PS_DDR3_A4 PS_DDR3_A5 PS_DDR3_A6 PS_DDR3_A7 PS_DDR3_A8 PS_DDR3_A9 PS_DDR3_A10 PS_DDR3_A11 PS_DDR3_A12 PS_DDR3_A13 PS_DDR3_A14 PS_DDR3_BA0 PS_DDR3_BA1 PS_DDR3_BA2 PS_DDR3_DM0 PS_DDR3_DM1 PS_DDR3_DM2 PS_DDR3_DM3 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 PS_DDR3_CLK0_P PS_DDR3_CLK0_N PS_DDR3_CLK0_P10 PS_DDR3_CLK0_N10 PS_DDR3_VRP PS_DDR3_VRN R36 R37 80 1% 80 1% +1.5V PS_DDR3_ODT PS_DDR3_S0 PS_DDR3_CKE PS_DDR3_WE PS_DDR3_CAS PS_DDR3_RAS PS_DDR3_ODT PS_DDR3_S0 PS_DDR3_CKE PS_DDR3_WE PS_DDR3_CAS PS_DDR3_RAS 10 10 10 10 10 10 PS_DDR3_RESET PS_DDR3_RESET 10 xc7z035ffg676-2_0 D C B A D C B A ALINX Confidential 5 4 3 2 http://www.alinx.com.cn Title Title Title Size Size Size Date: Date: Date: PAGE08 Z7 Bank502 PAGE08 Z7 Bank502 PAGE08 Z7 Bank502 Document Number Document Number Document Number AX7350开发板 Schematics AX7350开发板 Schematics AX7350开发板 Schematics Sheet Sheet Sheet 1 Thursday, June 14, 2018 Thursday, June 14, 2018 Thursday, June 14, 2018 Rev Rev Rev 1.0 1.0 1.0 8 8 8 of of of 26 26 26
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