Mentor Design-for-Test Common Resources.pdf

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Bookcase

Table of Contents

List of Tables

List of Figures

Chapter 1 About Common Resources

Chapter 2 Design Rule Checking

DFTAdvisor Rules Checking

Troubleshooting Rules Violations

Setting the Handling of Rules

Turning on ATPG Analysis

Setting the Level of Gate Data

Setting the Gate Information Type

Reporting Gate Data

Reporting on a Specific Gate

Reporting on All Gates of a Specified Type

Reporting a Histogram of All Gate Types

Reporting on a Path Between Two Gates

Reporting on the First Input of a Gate

Reporting on the First Fanout of a Gate

Flattening Rule Violations

The Design Rules

RAM Rules (A Rules)

A10

A11

A12

A13

BIST Rules (B Rules)

B10

B11

B12

B13

B14

B15

B16

Clock Rules (C Rules)

Clock Terminology

Clock Signals

Clock Cones and Effect Cones

The ATPG Analysis Option

C10

C11

C12

C13

C14

C15

C16

C17

Scan Cell Data Rules (D Rules)

D10

D11

Extra Rules (E Rules)

E10

E11

E12

E13

E14

Flattening Rules (F Rules)

FN1

FN2

FN3

FN4

FN5

FN6

FN7

FN8

FN9

FP1

FP2

FP3

FP4

FP5

FP6

FP7

FP8

FP9

FP10

FP11

FP12

FP13

FG1

FG2

FG3

FG4

FG5

FG6

FG7

FG8

General Rules (G Rules)

G10

G11

G12

EDT Rules (K Rules)

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

Procedure Rules (P Rules)

P10

P11

P12

P13

P14

P15

P16

P17

P18

P19

P20

P21

P22

P23

P24

P25

P26

P27

P28

P29

P30

P31

P32

P33

P34

P35

P36

P37

P38

P39

P40

P41

P42

P43

P44

P45

P46

P47

P48

P49

P50

P51

P52

P53

P54

P55

P56

P57

P58

P59

P62

P63

P64

P65

P70

Scanability Rules (S Rules)

Scan Chain Trace Rules (T Rules)

T10

T11

T12

T13

T14

T15

T16

T17

T18

T19

T20

T21

T22

T23

T24

T25

T26

Timing Rules (W Rules)

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

W21

W22

W23

W24

W25

W26

W27

W28

W29

W30

W31

W32

W33

W34

W35

W36

W37

W38

Other DRC Messages

Transparent Capture Handling Analysis

Oscillation Limitation

RAM Summary Results and Test Capability

Chapter 3 Getting Started with DFTVisualizer

Opening DFTVisualizer

Understanding the DFTVisualizer Windows

Performing Basic Tasks

Saving and Restoring Displays

Searching for an Instance, Net, or Pin

Undocking and Docking Windows

Resizing Windows

Understanding Popup Menus

Copying an Object Name from a Popup Menu to the System Clipboard

Adding Instances to a Display Window

Selecting Objects

Cross-Selecting Objects

Selecting Objects in the Debug or Design Window

Unselecting Objects

Copying Instances Between Windows

Tracing Signal Paths on a Schematic

Understanding Trace Options

Compacting Buffers and Inverters in Traced Circuitry

Tracing a Specific Signal Value to the Source

Tracing Signal Paths in the Design Window

Tracing Up and Down the Design Hierarchy

Bundling Nets

Annotating Schematic Data in the Debug Window

Displaying Multiple Data Sets

Analyzing a DRC Violation

Step 1 - Run an Analysis of the Violation

Running the Analysis

Step 2 - Find the Source of Problem Signals

Step 3 - Apply a Remedy and Rerun DRC

Assessing Test Coverage in the Browser

Analyzing a Fault and Displaying its Location

Executing Report Test Stimulus

Getting Oriented in a Large Design

Setting DFTVisualizer Preferences

Saving/Loading Session Preferences

Understanding the DFTVisualizer Preferences Dialog Box

Global Preferences Dialog Box

Colors Preferences Dialog Box

Debug Window Preferences Dialog Box

Design Window Preferences Dialog Box

Browser Window Preferences Dialog Box

Data Window Preferences Dialog Box

Text Editor Window Preferences Dialog Box

Objects Added to DFTVisualizer Windows

Task Manager Window

Browser Window

Data Window

Debug Window

Design Window

Format Guide Window

Global Search Window

Library Browser Window

Signals Window

Text Editor Window

Transcript Window

Wave Window

DFTVisualizer Command Quick Reference

Chapter 4 Design Library

Defining Scan Information

Defining a Scan Cell Model

Example Scan Definitions

Basic Example

MUX-Scan Cell

Clocked-Scan Cell

LSSD Cell

Complex Scan Model

Defining a Model

Model_name

List_of_pins

Interface Pins and Internal Nodes

Input Statement

Intern Statement

Inout Statement

Output Statement

Cell_type

Attributes

Input Attributes

Intern Attributes

Inout and Output Attributes

Primitive and Attribute Examples

Internal Faults

Support of Arrays Within Library Models

Defining Macros

Using Model Aliases

Reading Multiple Libraries

Verilog Primitives

Supported Primitives

AND Gate

NAND Gate

OR Gate

NOR Gate

Inverter

Buffer

Buffer With High Impedance Output

XOR Gate

XNOR Gate

Tri-State Buffer with Active Low Control

Inverted Tri-State Buffer with Active Low Control

Tri-State Buffer with Active High Control

Inverted Tri-State Buffer with Active High Control

Multiplexer

D Flip-Flop

D Latch

One Time Unit Delay Element (FlexTest Only)

Feedback Inverter

Wire Element

Pull-Up or Pull-Down Device

Power Signal

Ground Signal

Unknown Signal

High Impedance Signal

Undefined

Unidirectional NMOS Transistor

Unidirectional PMOS Transistor

Unidirectional Resistive NMOS Transistor

Unidirectional Resistive PMOS Transistor

Unidirectional Feedback NMOS Transistor

Unidirectional Feedback PMOS Transistor

Unidirectional CMOS1 Transistor

Unidirectional CMOS2 Transistor

Unidirectional Resistive CMOS1 Transistor

Unidirectional Resistive CMOS2 Transistor

Unidirectional Feedback CMOS1 Transistor

Unidirectional Feedback CMOS2 Transistor

Pulse Generators with User Defined Timing

RAM and ROM

RAM and ROM Basics

RAM/ROM Library Primitives

ROM Library Primitive

Basic RAM Library Primitive

Comprehensive RAM Primitive

Attributes of RAM/ROM Primitives

Initialization Files for RAM and ROM

ROM and RAM Port Behavior

Read Port Behavior for _rom and _ram

Read Port Behavior for _cram

Set and Reset Lines for _ram and _cram

Write Port Behavior for _ram

Write Port Behavior for _cram

Read_Write Port Behavior for _cram

DRC for RAMs

ROM Limitations

RAM Limitations

Chapter 5 Creating ATPG Models

Converting TetraMax Primitives to Verilog Primitives

Creating an ATPG Library

Finding Unsupported Constructs in Partial Models

Finding Black Boxes with Vectored Outputs

Reconciling System Verilog reg and Verilog Keyword Compiling Issues

Accounting for Reserved Verilog Keywords

Accounting for Reg and Wire for Interconnect

LibComp Command Summary

LibComp Command Descriptions

Add Model

Delete Model

Dofile

Exit

Help

Load Library

Report Environment

Run

Set Asynchronous Control_Logic

Set Behavioral Processing

Set Dofile Abort

Set Excessive Pull_delay

Set Hold Check

Set System Mode

Set Verification

Set X_from_known Combinational_udp

System

Write Library

UDP Limitations and Examples

Complex Asynchronous Set/Reset Logic

2-1 Mux Translation

Consensus Terms - UDP Rows Consideration

UDP With Both Consensus Terms

LibComp Limitation - Always Converts To _mux

Default Solution - LibComp Outputs _mux

Manual Alternative Solution 1

Manual Alternative Solution 2

Partial Mux Examples - Missing Consensus Terms

Case 1 - Mux Missing 11 Consensus Term

Case 2 - Mux Missing 00 Consensus Term

Case 3 - Mux Missing Both Consensus Terms

Mux Example With Consensus Terms

LibComp Limitation - Complex Asynchronous Logic

Mux Scan DFF With Complex Asynchronous Logic

Example - Mux Scan DFF

Example - Mux Scan Cell With Asynchronous Gated Off By Scan Enable

LibComp Limitation - Verilog Construct Support

Behavioral Constructs

Structural Constructs

DFF Example

D Latch Example

I/O Pad Limitations and Examples

Strength Propagation

Pin Constraints Required for Verification

I/O Pad Code Example

Memory Limitations and Examples

$readmemh and $readmemb

ROM Example

RAM Examples

Single Posedge Ports With Separate Port Clocks

Single Level Ports With Write-Thru and Trisate Output Enable

Single Posedge Write Level Read Ports With Write-Thru

Single Posedge Ports With Separate Port Clocks

Single Level Ports With Separate Port Clocks

Single Posedge Ports With Write Enable

Single Level Ports With Single Read/Write Control and Bit- Blasted Wrapper

Single Level Ports With Read_Off 1 Output and Tristate Output Enable

Single Posedge Ports With Memory Bypass

Single Level Bidirectional Ports With Write-Thru and Output Enable

Single Posedge Ports With Port and Per-Bit Write Enables and Write_Thru

Dual Posedge Ports With Separate Clocks

Dual Posedge Write Level Read Ports With Separate Clocks

Dual Posedge Write Level Read Ports With Separate Clocks and Tristate Output Enable

Dual Level Ports With Separate Clocks and Write-Thru

Dual Posedge Bidirectional Ports With Read_Off 0 and Output Enable

Dual Posedge Separate Clocks Ports With Port and Per-Bit Write Enables

Chapter 6 Verifying ATPG Models

Verification Overview

Specifying which Tool Performs Verification

Verification Prerequisites

Running Verification from the Shell

Verifying a Single Model in an ATPG Library

Interpreting the Verification Results

verify.results File Example

Debugging Models

Re-simulating Verilog Only

Prerequisites for Simulating Verilog Only

Simulating Verilog Only

Fixing DRC Violations

Improving Test Coverage

Troubleshooting One Model at a Time

Assessing the Impact of Low Coverage

Locating Low-Coverage Models

Re-running the FastScan Portion of Verification

Modeling for Optimal Test Coverage

Handling Ignored or Blackboxed Models

Anticipating the Effects of Internal Gating on Clocks

Chapter 7 Test Procedure File

What is a Test Procedure File?

When Do I Need to Create a Test Procedure File?

Procedure File Syntax

Introductory Procedure File Example

Procedure File

#include Statement

Set Statement

Alias Definition

Timing Variables

Timeplate Definition

Always Block

Always Block Syntax

Always Block Example

Procedure Definition

The Procedures

Scan and Clock Procedures

Non-Scan Procedures

Non-Scan Procedure File

Viewing Optimized Named Capture Procedures (NCPs)

Rules for Creating and Editing a Default Capture Procedure

Rules for Creating and Editing Named Capture Procedures

Example Named Capture Procedure

Slow and Load Types

launch_capture_pair Statement

Example PLL Model and Named Capture Procedure

Example 1: Using test_end in a Procedure File

Example 2: Test_end Procedure with Timeplate

Sub_procedure Looping

Disabling Sub_procedure Looping

Sub_procedure Definition Format

Using the Sub_procedure in a Procedure

Procedure File Examples

FlexTest Examples

FlexTest Example 1

FlexTest Example 2

Environment Variables in Procedure Files

Merging Procedure Files

Default Information

Creating Test Procedure Files for End Measure Mode

Supporting Commands

Output Formats

Parameter File Format and Keywords

Appendix A Getting Help

Documentation

Online Command Help

Mentor Graphics Support

Invoking the Tool in Tcl Scripting Mode

Using Tcl Scripting Within the Tool

Usage Limitations

Tcl Scripting Examples

Example 1

Example 2

Example 3

Index

Third-Party Information

End-User License Agreement

Documentation Feedback

Design-for-Test Common Resources Manual Software Version 8.2009_1 February 2009 © 1999-2009 Mentor Graphics Corporation All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information.

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Table of Contents Chapter 1 About Common Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 17 Design Rule Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DFTAdvisor Rules Checking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Troubleshooting Rules Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Setting the Handling of Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turning on ATPG Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Setting the Level of Gate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Setting the Gate Information Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reporting Gate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Flattening Rule Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 The Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RAM Rules (A Rules). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 BIST Rules (B Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Clock Rules (C Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Scan Cell Data Rules (D Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extra Rules (E Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Flattening Rules (F Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 General Rules (G Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 EDT Rules (K Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Procedure Rules (P Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Scanability Rules (S Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Scan Chain Trace Rules (T Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Timing Rules (W Rules) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Other DRC Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Transparent Capture Handling Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Oscillation Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 RAM Summary Results and Test Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Chapter 3 Getting Started with DFTVisualizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Opening DFTVisualizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Understanding the DFTVisualizer Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Performing Basic Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Saving and Restoring Displays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Searching for an Instance, Net, or Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Undocking and Docking Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Resizing Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Understanding Popup Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Adding Instances to a Display Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Design-for-Test Common Resources Manual, V8.2009_1 February 2009 3

Table of Contents Selecting Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Unselecting Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Copying Instances Between Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Tracing Signal Paths on a Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Tracing a Specific Signal Value to the Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Tracing Signal Paths in the Design Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Annotating Schematic Data in the Debug Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Displaying Multiple Data Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Analyzing a DRC Violation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Step 1 - Run an Analysis of the Violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Step 2 - Find the Source of Problem Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Step 3 - Apply a Remedy and Rerun DRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Assessing Test Coverage in the Browser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Analyzing a Fault and Displaying its Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Executing Report Test Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Getting Oriented in a Large Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Setting DFTVisualizer Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Saving/Loading Session Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Understanding the DFTVisualizer Preferences Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . 243 Global Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Colors Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Debug Window Preferences Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Design Window Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Browser Window Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Data Window Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Text Editor Window Preferences Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Objects Added to DFTVisualizer Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Task Manager Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Data Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Debug Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Design Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Format Guide Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Global Search Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Library Browser Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Signals Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Text Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Transcript Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 DFTVisualizer Command Quick Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Chapter 4 Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Defining Scan Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 Defining a Scan Cell Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Example Scan Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Defining a Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Model_name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 4 Design-for-Test Common Resources Manual, V8.2009_1 February 2009

Table of Contents List_of_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Interface Pins and Internal Nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Cell_type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Internal Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Support of Arrays Within Library Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Defining Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Using Model Aliases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Reading Multiple Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Verilog Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Supported Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Buffer With High Impedance Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 XOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 XNOR Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Tri-State Buffer with Active Low Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Inverted Tri-State Buffer with Active Low Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Tri-State Buffer with Active High Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Inverted Tri-State Buffer with Active High Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 D Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 D Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 One Time Unit Delay Element (FlexTest Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Feedback Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Wire Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Pull-Up or Pull-Down Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Power Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 Ground Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Unknown Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 High Impedance Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Undefined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Unidirectional NMOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 Unidirectional PMOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 Unidirectional Resistive NMOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 Unidirectional Resistive PMOS Transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Unidirectional Feedback NMOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Unidirectional Feedback PMOS Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 Unidirectional CMOS1 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Unidirectional CMOS2 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Unidirectional Resistive CMOS1 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Unidirectional Resistive CMOS2 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 Unidirectional Feedback CMOS1 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Unidirectional Feedback CMOS2 Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Pulse Generators with User Defined Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Design-for-Test Common Resources Manual, V8.2009_1 February 2009 5

Table of Contents RAM and ROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Chapter 5 Creating ATPG Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Converting TetraMax Primitives to Verilog Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Creating an ATPG Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Finding Unsupported Constructs in Partial Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Finding Black Boxes with Vectored Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Reconciling System Verilog reg and Verilog Keyword Compiling Issues . . . . . . . . . . . . . . 374 Accounting for Reserved Verilog Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Accounting for Reg and Wire for Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 LibComp Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 LibComp Command Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 UDP Limitations and Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Complex Asynchronous Set/Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 2-1 Mux Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 Consensus Terms - UDP Rows Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 LibComp Limitation - Always Converts To _mux. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 LibComp Limitation - Complex Asynchronous Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 LibComp Limitation - Verilog Construct Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 DFF Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 D Latch Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 I/O Pad Limitations and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 I/O Pad Code Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Memory Limitations and Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 $readmemh and $readmemb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 ROM Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 RAM Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 Chapter 6 Verifying ATPG Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Verification Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Specifying which Tool Performs Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Verification Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Running Verification from the Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Verifying a Single Model in an ATPG Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Interpreting the Verification Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 verify.results File Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Debugging Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 Re-simulating Verilog Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Prerequisites for Simulating Verilog Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Simulating Verilog Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Fixing DRC Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Improving Test Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Troubleshooting One Model at a Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Assessing the Impact of Low Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Locating Low-Coverage Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Re-running the FastScan Portion of Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 6 Design-for-Test Common Resources Manual, V8.2009_1 February 2009

Table of Contents Modeling for Optimal Test Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Handling Ignored or Blackboxed Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Anticipating the Effects of Internal Gating on Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Chapter 7 Test Procedure File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 What is a Test Procedure File? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 When Do I Need to Create a Test Procedure File? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Procedure File Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Introductory Procedure File Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Procedure File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 #include Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 Set Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 Alias Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Timing Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Timeplate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Always Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 Procedure Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 The Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 Scan and Clock Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Non-Scan Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Procedure File Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 FlexTest Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Environment Variables in Procedure Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Merging Procedure Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Default Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Creating Test Procedure Files for End Measure Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 Supporting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Parameter File Format and Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Appendix A Getting Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Online Command Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 Appendix B Using the Tcl Scripting Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Invoking the Tool in Tcl Scripting Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Using Tcl Scripting Within the Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Usage Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Tcl Scripting Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 Design-for-Test Common Resources Manual, V8.2009_1 February 2009 7

Table of Contents Index Third-Party Information End-User License Agreement Design-for-Test Common Resources Manual, V8.2009_1 February 2009 8

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