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PCI PM Spec.pdf
Contents
1. Introduction
1.1. Goals of This Specification
1.2. Target Audience
1.3. Overview/Scope
1.4. Conventions Used in This Document
1.5. Glossary of Terms
1.6. Related Documents
2. PCI Power Management Overview
2.1. PCI Power Management States
2.1.1. PCI Function Power States
2.1.2. Bus Power States
2.1.3. PCI Express Link Power States
2.1.4. Device-Class Specifications
2.1.5. Bus Support for PCI Function Power Management
3. PCI Power Management Interface
3.1. Capabilities List Data Structure
3.1.1. Capabilities List Cap_Ptr Location
3.2. Power Management Register Block Definition
3.2.1. Capability Identifier - Cap_ID (Offset = 0)
3.2.2. Next Item Pointer - Next_Item_Ptr (Offset = 1)
3.2.3. PMC - Power Management Capabilities (Offset = 2)
3.2.4. PMCSR - Power Management Control/Status (Offset = 4)
3.2.5. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions (Offset = 6)
3.2.6. Data (Offset = 7)
4. PCI Bus Power States
4.1. PCI B0 State - Fully On
4.2. PCI B1 State
4.3. PCI B2 State
4.4. PCI B3 State - Off
4.5. PCI Bus Power State Transitions
4.6. PCI Clocking Considerations
4.6.1. Special Considerations for 66-MHz PCI Designs
4.7. Control/Status of PCI Bus Power Management States
4.7.1. Control of Secondary Bus Power Source and Clock
5. PCI Function Power Management States
5.1. PCI Function D0 State
5.2. PCI Function D1 State
5.3. PCI Function D2 State
5.4. PCI Function D3 State
5.4.1. Software Accessible D3 (D3hot)
5.4.2. Power Off (D3cold)
5.4.3. 3.3Vaux/D3cold Add-in Card Power Consumption Requirements
5.5. PCI Function Power State Transitions
5.6. PCI Function Power Management Policies
5.6.1. State Transition Recovery Time Requirements
6. PCI Bridges and Power Management
6.1. Host Bridge or Other System Board Enumerated Bridge
6.2. PCI-to-PCI Bridges
6.3. PCI-to-CardBus Bridge
7. Power Management Events
7.1. Power Management Event (PME#) Signal Routing
7.2. Auxiliary Power
7.2.1. 3.3Vaux DC Characteristics
7.2.2. 3.3Vaux Minimum Required Current Capacity
7.3. 3.3Vaux System Design Requirements
7.3.1. Power Delivery Requirements
7.3.2. PCI Bus RST# Signaling Requirements
7.3.3. Voltage Sequencing
7.4. 3.3Vaux Add-in Card Design Requirements
7.4.1. 3.3Vaux Power Consumption Requirements
7.4.2. Physical Connection to the 3.3Vaux Pin
7.4.3. Isolation of 3.3Vaux from Main 3.3V
7.4.4. 3.3Vaux Presence Detection
8. Software Support for PCI Power Management
8.1. Identifying PCI Function Capabilities
8.2. Placing PCI Functions in a Low Power State
8.2.1. Buses
8.2.2. D3 State
8.3. Restoring PCI Functions From a Low Power State
8.3.1. D0 “Uninitialized” and the DSI Bit
8.3.2. D1 and D2 States
8.3.3. D3 State
8.4. Wake Events
8.4.1. Wake Event Support
8.4.2. The D0 “Initialized” State From a Wake Event
8.5. Get Capabilities
8.6. Set Power State
8.7. Get Power Status
8.8. System Firmware Initialization
9. Other Considerations
PCI Bus Power Management
Interface Specification
Revision 1.2
March 3, 2004
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
Revision History
Revision
Issue Date
Comments
1.0
1.1
1.2
June 30, 1997
Original Issue.
December 18, 1998
Integrated the 3.3Vaux ECR.
March 3, 2004
Changed defined action for D3hot and clarified
bridge behavior when not in D0. Common
document template update.
PCI-SIG disclaims all warranties and liability for the use of this document and the information
contained herein and assumes no responsibility for any errors that may appear in this document, nor
does the PCI-SIG make a commitment to update the information contained herein.
Contact the PCI-SIG office to obtain the latest revision of the specification.
Questions regarding this specification or membership in PCI-SIG may be forwarded to:
Membership Services
www.pcisig.com
E-mail:
Phone:
Fax:
Technical Support
techsupp@pcisig.com
administration@pcisig.com
503-291-2569
503-297-1090
DISCLAIMER
This PCI Bus Power Management Interface Specification is provided "as is" with no
warranties whatsoever, including any warranty of merchantability, noninfringement,
fitness for any particular purpose, or any warranty otherwise arising out of any proposal,
specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary
rights, relating to use of information in this specification. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights is granted herein.
PCI Express is a trademark of PCI-SIG.
All other product names are trademarks, registered trademarks, or service marks of their
respective owners.
2
Copyright © 1997, 1998, 2004 PCI-SIG
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
Contents
1.
2.1.
3.1.1.
3.2.
2.1.1.
2.1.2.
2.1.3.
2.1.4.
2.1.5.
INTRODUCTION............................................................................................................... 7
1.1. GOALS OF THIS SPECIFICATION ...................................................................................... 7
1.2.
TARGET AUDIENCE ........................................................................................................ 8
1.3. OVERVIEW/SCOPE .......................................................................................................... 9
1.4. CONVENTIONS USED IN THIS DOCUMENT..................................................................... 10
1.5. GLOSSARY OF TERMS ................................................................................................... 10
1.6. RELATED DOCUMENTS ................................................................................................. 15
2. PCI POWER MANAGEMENT OVERVIEW ............................................................... 17
PCI POWER MANAGEMENT STATES ............................................................................. 17
PCI Function Power States ................................................................................. 17
Bus Power States................................................................................................. 17
PCI Express Link Power States........................................................................... 17
Device-Class Specifications ................................................................................ 18
Bus Support for PCI Function Power Management ........................................... 19
3. PCI POWER MANAGEMENT INTERFACE .............................................................. 21
3.1. CAPABILITIES LIST DATA STRUCTURE.......................................................................... 22
Capabilities List Cap_Ptr Location .................................................................... 23
POWER MANAGEMENT REGISTER BLOCK DEFINITION.................................................. 24
Capability Identifier - Cap_ID (Offset = 0) ........................................................ 24
Next Item Pointer - Next_Item_Ptr (Offset = 1).................................................. 25
PMC - Power Management Capabilities (Offset = 2) ........................................ 25
PMCSR - Power Management Control/Status (Offset = 4) ................................ 27
PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions (Offset = 6).... 30
Data (Offset = 7) ................................................................................................. 31
4. PCI BUS POWER STATES............................................................................................. 35
PCI B0 STATE - FULLY ON .......................................................................................... 36
PCI B1 STATE.............................................................................................................. 36
PCI B2 STATE.............................................................................................................. 36
PCI B3 STATE - OFF .................................................................................................... 37
PCI BUS POWER STATE TRANSITIONS.......................................................................... 37
PCI CLOCKING CONSIDERATIONS ................................................................................ 38
Special Considerations for 66-MHz PCI Designs............................................... 38
4.7. CONTROL/STATUS OF PCI BUS POWER MANAGEMENT STATES ................................... 39
Control of Secondary Bus Power Source and Clock........................................... 39
3.2.1.
3.2.2.
3.2.3.
3.2.4.
3.2.5.
3.2.6.
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.6.1.
4.7.1.
3
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
5.6.1.
5.5.
5.6.
5.1.
5.2.
5.3.
5.4.
5.4.1.
5.4.2.
5.4.3.
5. PCI FUNCTION POWER MANAGEMENT STATES ................................................ 41
PCI FUNCTION D0 STATE............................................................................................. 41
PCI FUNCTION D1 STATE ............................................................................................ 41
PCI FUNCTION D2 STATE ............................................................................................ 42
PCI FUNCTION D3 STATE ............................................................................................ 42
Software Accessible D3 (D3hot)........................................................................... 43
Power Off (D3cold) ............................................................................................... 43
3.3Vaux/D3cold Add-in Card Power Consumption Requirements ....................... 44
PCI FUNCTION POWER STATE TRANSITIONS ................................................................ 45
PCI FUNCTION POWER MANAGEMENT POLICIES.......................................................... 45
State Transition Recovery Time Requirements ................................................... 50
6. PCI BRIDGES AND POWER MANAGEMENT .......................................................... 53
6.1. HOST BRIDGE OR OTHER SYSTEM BOARD ENUMERATED BRIDGE................................ 55
PCI-TO-PCI BRIDGES................................................................................................... 56
6.2.
PCI-TO-CARDBUS BRIDGE........................................................................................... 56
6.3.
7. POWER MANAGEMENT EVENTS.............................................................................. 57
7.1.
POWER MANAGEMENT EVENT (PME#) SIGNAL ROUTING ........................................... 60
7.2. AUXILIARY POWER....................................................................................................... 61
3.3Vaux DC Characteristics ............................................................................... 61
3.3Vaux Minimum Required Current Capacity................................................... 62
3.3VAUX SYSTEM DESIGN REQUIREMENTS.................................................................. 62
Power Delivery Requirements............................................................................. 62
PCI Bus RST# Signaling Requirements .............................................................. 63
Voltage Sequencing ............................................................................................. 64
3.3VAUX ADD-IN CARD DESIGN REQUIREMENTS......................................................... 65
3.3Vaux Power Consumption Requirements....................................................... 65
Physical Connection to the 3.3Vaux Pin............................................................. 65
Isolation of 3.3Vaux from Main 3.3V.................................................................. 65
3.3Vaux Presence Detection................................................................................ 66
8. SOFTWARE SUPPORT FOR PCI POWER MANAGEMENT.................................. 67
IDENTIFYING PCI FUNCTION CAPABILITIES .................................................................. 67
PLACING PCI FUNCTIONS IN A LOW POWER STATE...................................................... 67
Buses.................................................................................................................... 68
D3 State............................................................................................................... 68
8.3. RESTORING PCI FUNCTIONS FROM A LOW POWER STATE............................................ 69
D0 “Uninitialized” and the DSI Bit.................................................................... 69
D1 and D2 States................................................................................................. 70
D3 State............................................................................................................... 70
8.4. WAKE EVENTS ............................................................................................................. 70
8.4.1. Wake Event Support ............................................................................................ 70
The D0 “Initialized” State From a Wake Event.................................................. 71
8.4.2.
8.5. GET CAPABILITIES........................................................................................................ 71
7.4.1.
7.4.2.
7.4.3.
7.4.4.
8.2.1.
8.2.2.
8.3.1.
8.3.2.
8.3.3.
7.3.
7.2.1.
7.2.2.
7.3.1.
7.3.2.
7.3.3.
7.4.
8.1.
8.2.
4
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
8.6.
SET POWER STATE ....................................................................................................... 71
8.7. GET POWER STATUS..................................................................................................... 72
8.8.
SYSTEM FIRMWARE INITIALIZATION............................................................................. 72
9. OTHER CONSIDERATIONS......................................................................................... 73
5
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
Figures
FIGURE 1-1: OPERATING SYSTEM DIRECTED POWER MANAGEMENT SYSTEM ARCHITECTURE ..... 9
FIGURE 1-2: EXAMPLE ORIGINATING DEVICES............................................................................ 12
FIGURE 3-1: STANDARD PCI CONFIGURATION SPACE HEADER TYPE 0 ...................................... 21
FIGURE 3-2: CAPABILITIES LINKED LIST...................................................................................... 23
FIGURE 3-3: POWER MANAGEMENT REGISTER BLOCK................................................................ 24
FIGURE 4-1: PCI BUS POWER STATE TRANSITIONS..................................................................... 37
FIGURE 5-1: PCI FUNCTION POWER MANAGEMENT STATE TRANSITIONS................................... 45
FIGURE 5-2: NON-BRIDGE PCI FUNCTION POWER MANAGEMENT DIAGRAM ............................. 46
FIGURE 6-1: PCI BRIDGE POWER MANAGEMENT DIAGRAM ....................................................... 53
FIGURE 7-1: PME# SYSTEM ROUTING........................................................................................ 60
FIGURE 7-2: B3 RESET TIMING ................................................................................................... 64
FIGURE 7-3: ADD-IN CARD AUXILIARY POWER ROUTING ........................................................... 66
Tables
TABLE 3-1: PCI STATUS REGISTER ............................................................................................. 22
TABLE 3-2: CAPABILITIES POINTER - CAP_PTR........................................................................... 22
TABLE 3-3: PCI CONFIGURATION SPACE HEADER TYPE/CAP_PTR MAPPINGS ........................... 23
TABLE 3-4: CAPABILITY IDENTIFIER - CAP_ID............................................................................ 24
TABLE 3-5: NEXT ITEM POINTER - NEXT_ITEM_PTR................................................................... 25
TABLE 3-6: POWER MANAGEMENT CAPABILITIES - PMC ........................................................... 25
TABLE 3-7: POWER MANAGEMENT CONTROL/STATUS - PMCSR ............................................... 28
TABLE 3-8: PMCSR BRIDGE SUPPORT EXTENSIONS - PMCSR_BSE......................................... 30
TABLE 3-9: DATA REGISTER ....................................................................................................... 31
TABLE 3-10: POWER CONSUMPTION/DISSIPATION REPORTING ................................................... 31
TABLE 4-1: PCI BUS POWER MANAGEMENT STATES.................................................................. 35
TABLE 4-2: PCI BUS POWER AND CLOCK CONTROL................................................................... 39
TABLE 5-1: D0 POWER MANAGEMENT POLICIES ........................................................................ 47
TABLE 5-2: D1 POWER MANAGEMENT POLICIES ........................................................................ 47
TABLE 5-3: D2 POWER MANAGEMENT POLICIES ........................................................................ 48
TABLE 5-4: D3HOT POWER MANAGEMENT POLICIES .................................................................... 49
TABLE 5-5: D3COLD POWER MANAGEMENT POLICIES................................................................... 50
TABLE 5-6: PCI FUNCTION STATE TRANSITION DELAYS............................................................. 51
TABLE 6-1: PCI BRIDGE POWER MANAGEMENT POLICIES.......................................................... 55
TABLE 7-1: DC OPERATING ENVIRONMENT FOR A 3.3VAUX-ENABLED SYSTEM ........................ 62
6
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
1
Introduction
1.
Since its introduction in 1992, PCI has become a very popular bus. It is used in a wide variety of
computer systems sold today ranging from laptops to large servers. Its bandwidth and efficient
support for multiple masters has allowed it to sustain high performance applications; while at the
same time, its low pin count and high integration factor has enabled very low cost solutions.
Power management in early PC platforms was performed by a combination of firmware and System
Management Mode (SMM) code utilizing hardware unique to each platform. While this strategy
successfully brought the PC platform into the mobile environment, it was beset with problems
because of the fact that there was no standard way to truly determine when the system was busy and
when it was actually idle. The operating system does have this information, so it makes sense to give
it the responsibility for power management. This specification addresses this need.
While the PCI Local Bus Specification, Revision 3.0 (PCI 3.0) is quite complete with a solid definition of
protocols, electrical characteristics, and mechanical form factors, no provision was made for
supporting power management functionality. This specification addresses this requirement by
defining four distinct power states for the PCI bus and four distinct power states for PCI functions
as well as an interface for controlling these power states.
Goals of This Specification
1.1.
The goal of this specification is to establish a standard set of PCI peripheral power management
hardware interfaces and behavioral policies. Once established, this infrastructure enables an
operating system to intelligently manage the power of PCI functions and buses.
Detailed Goals for PCI Power Management Interface:
Enable multiple PCI function power levels
Establish a standard for PCI function Wakeup Events
Establish a standard for reporting power management capabilities
Establish a standard mechanism for controlling a PCI function's power state
Establish a standard mechanism for controlling a PCI bus's power state
Minimal impact to PCI 3.0
Compatible with PCI 3.0 compliant designs
Preserve the designer’s ability to deliver differentiated products
Provide a single architecture for all markets from mobile through server
7
PCI BUS POWER MANAGEMENT INTERFACE SPECIFICATION, REV. 1.2
Key Attributes of This Specification:
Enhances the PCI bus’s Plug and Play capabilities by comprehending power management
Standardized power state definitions
Standardized register interface in PCI Configuration Space
Standardized Wake events
Target Audience
1.2.
This document is intended to address the needs of several distinct audiences. Developers of PCI
peripherals are the first audience. This document describes the hardware requirements of such
devices to allow an operating system to manage the power of those devices. Developers of PCI host
bridges, PCI-to-expansion bus bridges, PCI-to-PCI bus bridges, and PCI-to-CardBus bridges will
also find information describing the requirements for such devices to implement operating system
directed power management.
Software developers are also a targeted audience for this specification. Specifically, developers of
operating systems and device drivers need to understand the power management interfaces
presented by compliant devices to be able to manage them.
8
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