//------------------------------------------------------------------------------------------------- // // File // Generated // Author // //------------------------------------------------------------------------------------------------- `timescale 1 ns / 1 ps : ADC0809.v : 2011-07-21 : wangliang module ADC0809 ( seven_seg ,ale ,OE ,D ,EOC ,clk ,abc_in ,abc_out ,start ,rst ); //系统时钟 //外部控制的通道选择信号 //ADC0809 传进来的数据 //ADC0809 转换完成信号标志 //系统 复位 //FPGA 给数码管的数据 //FPGA 给 ADC0809 的地址锁存信号 //FPGA 给 ADC0809 的使能信号 //FPGA 给 ADC0809 的通道选择信号 //ADC0809 转换开始信号 input input input input input output output output output output [2:0] [7:0] ; clk ; abc_in D ; EOC ; rst ; [15:0] [2:0] seven_seg ; ale ; OE ; abc_out ; start ; parameter st0 = 3'b000, st1 = 3'b001, st2 = 3'b010, st3 = 3'b011, st4 = 3'b100, st5 = 3'b101, st6 = 3'b110 ; reg reg reg reg reg reg reg wire [2:0] p_state ; [2:0] [7:0] [7:0] [2:0] n_state ; ale_r OE_r start_r reg1 qq state ; ; ; ; ; ; assign state = p_state ; always @ (posedge clk or negedge rst) 

begin if ( rst== 1'b0 ) begin p_state <= st0 qq <= 8'b0 ; ; end else begin qq <= qq + 1'b1; if ( ( qq >= 8'b0100_0010) && ( clk == 1'b1 ) ) begin qq <= 8'b0; p_state <=#1 n_state; end end end assign assign assign ; ale = ale_r OE = OE_r start = start_r ; ; assign abc_out = abc_in ; always @ ( EOC ,p_state ) begin case ( p_state ) st0 :begin ale_r <= #1 1'b0; start_r <= #1 1'b0; OE_r <= #1 1'b0; n_state <=#1 st1; end st1 :begin ale_r <= #1 1'b1; start_r <= #1 1'b0; OE_r <= #1 1'b0; n_state <=#1 st2; end st2 :begin ale_r <= #1 1'b0; start_r <= #1 1'b1; OE_r <= #1 1'b0; n_state <=#1 st3; end st3 :begin 

ale_r <= #1 1'b0; start_r <= #1 1'b0; OE_r <= #1 1'b0; if ( EOC == 1'b1 ) n_state <=#1 st3; else n_state <=#1 st4; end st4 :begin ale_r <= #1 1'b0; start_r <= #1 1'b0; OE_r <= #1 1'b0; if ( EOC == 1'b0 ) n_state <=#1 st4; n_state <=#1 st5; else end st5 :begin ale_r <= #1 1'b0; start_r <= #1 1'b0; OE_r <= #1 1'b1; n_state <=#1 st6; end st6 :begin ale_r <= #1 1'b0; start_r <= #1 1'b0; OE_r <= #1 1'b1; reg1 <=#1 D ; n_state <=#1 st0; end default :begin ale_r <= #1 1'b0; start_r <= #1 1'b0; OE_r <= #1 1'b0; n_state <=#1 st0; end endcase end /******************** 数码管显示译码部分 ***********************************/ reg reg Y_r_1; Y_r_2; [7:0] [7:0] 

assign seven_seg[7:0] ={1'b1,(~Y_r_1[6:0])}; assign seven_seg[15:8] = {1'b1,(~Y_r_2[6:0])}; always @(reg1[3:0] ) begin Y_r_1 = 7'b1111111; case (reg1[3:0] ) 4'b0000: Y_r_1 = 7'b0111111; // 0 4'b0001: Y_r_1 = 7'b0000110; // 1 4'b0010: Y_r_1 = 7'b1011011; // 2 4'b0011: Y_r_1 = 7'b1001111; // 3 4'b0100: Y_r_1 = 7'b1100110; // 4 4'b0101: Y_r_1 = 7'b1101101; // 5 4'b0110: Y_r_1 = 7'b1111101; // 6 4'b0111: Y_r_1 = 7'b0000111; // 7 4'b1000: Y_r_1 = 7'b1111111; // 8 4'b1001: Y_r_1 = 7'b1101111; // 9 4'b1010: Y_r_1 = 7'b1110111; // A 4'b1011: Y_r_1 = 7'b1111100; // b 4'b1100: Y_r_1 = 7'b0111001; // c 4'b1101: Y_r_1 = 7'b1011110; // d 4'b1110: Y_r_1 = 7'b1111001; // E 4'b1111: Y_r_1 = 7'b1110001; // F default: Y_r_1 = 7'b0000000; endcase end always @( reg1[7:4] ) begin Y_r_2 = 7'b1111111; case ( reg1[7:4] ) 4'b0000: Y_r_2 = 7'b0111111; // 0 4'b0001: Y_r_2 = 7'b0000110; // 1 4'b0010: Y_r_2 = 7'b1011011; // 2 4'b0011: Y_r_2 = 7'b1001111; // 3 4'b0100: Y_r_2 = 7'b1100110; // 4 4'b0101: Y_r_2 = 7'b1101101; // 5 4'b0110: Y_r_2 = 7'b1111101; // 6 4'b0111: Y_r_2 = 7'b0000111; // 7 4'b1000: Y_r_2 = 7'b1111111; // 8 4'b1001: Y_r_2 = 7'b1101111; // 9 4'b1010: Y_r_2 = 7'b1110111; // A 4'b1011: Y_r_2 = 7'b1111100; // b 

4'b1100: Y_r_2 = 7'b0111001; // c 4'b1101: Y_r_2 = 7'b1011110; // d 4'b1110: Y_r_2 = 7'b1111001; // E 4'b1111: Y_r_2 = 7'b1110001; // F default: Y_r_2 = 7'b0000000; endcase end endmodule