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arm-cortex-a9技术参考手册.pdf
ARM® Cortex®‑A9 Technical Reference Manual
Contents
List of Figures
List of Tables
Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Timing diagrams
Signals
Additional reading
Feedback
Feedback on this product
Feedback on content
1 : Introduction
1.1 : About the Cortex®‑A9 processor
1.1.1 : Data engine
Media Processing Engine
Floating-Point Unit
1.1.2 : System design components
1.2 : Processor variants
1.3 : Compliance
1.3.1 : ARM® architecture
1.3.2 : Advanced Microcontroller Bus Architecture
1.3.3 : Program Flow Trace architecture
1.3.4 : Debug architecture
1.3.5 : Generic Interrupt Controller architecture
1.4 : Features
1.5 : Interfaces
1.6 : Configurable options
1.7 : Test features
1.8 : Product documentation and design flow
1.8.1 : Documentation
1.8.2 : Design flow
1.9 : Product revisions
2 : Functional Description
2.1 : About the functions
2.1.1 : Instruction queue
2.1.2 : Dynamic branch prediction
2.1.3 : Register renaming
2.1.4 : PTM interface
2.1.5 : Performance monitoring
2.1.6 : Virtualization of interrupts
2.2 : Interfaces
2.2.1 : AXI interface
2.2.2 : APB external debug interface
2.2.3 : Program Flow Trace and Program Trace Macrocell
2.3 : Clocking and resets
2.3.1 : Synchronous clocking
2.3.2 : Reset
Reset modes
Power-on reset
Warm reset
MPE SIMD logic reset
Debug reset
2.3.3 : Dynamic high-level clock gating
2.4 : Power management
2.4.1 : Energy efficiency features
2.4.2 : Processor power control
Run mode
Standby modes
Dormant mode
Shutdown mode
Communication to the power management controller
2.4.3 : Power domains
2.4.4 : Cortex®‑A9 voltage domains
2.5 : Constraints and limitations of use
3 : Programmers Model
3.1 : About the programmers model
3.2 : ThumbEE architecture
3.3 : The Jazelle® Extension
3.4 : Advanced SIMD architecture
3.5 : Security Extensions architecture
3.5.1 : System boot sequence
3.6 : Multiprocessing Extensions
3.7 : Modes of operation and execution
3.8 : Memory model
3.9 : Addresses in the Cortex®‑A9 processor
4 : System Control
4.1 : About system control
4.1.1 : Deprecated registers
4.2 : Register summary
4.2.1 : CP15 system control registers grouped by CRn order
c0 registers
c1 registers
c2 registers
c3 registers
c4 registers
c5 registers
c6 registers
c7 registers
c8 registers
c9 registers
c10 registers
c11 registers
c12 registers
c13 registers
c14 registers
c15 registers
4.2.2 : CP15 system control registers grouped by function
Identification registers
Virtual memory control registers
Fault Handling registers
Other system control registers
Cache maintenance operations
Address translation operations
Miscellaneous operations
Performance monitor registers
Security Extensions registers
Preload Engine registers
TLB maintenance
Implementation defined registers
4.3 : Register descriptions
4.3.1 : Main ID Register
4.3.2 : TLB Type Register
4.3.3 : Multiprocessor Affinity Register
4.3.4 : Revision ID register
4.3.5 : Cache Size Identification Register
4.3.6 : Cache Level ID Register
4.3.7 : Auxiliary ID Register
4.3.8 : Cache Size Selection Register
4.3.9 : System Control Register
4.3.10 : Auxiliary Control Register
4.3.11 : Coprocessor Access Control Register
4.3.12 : Secure Debug Enable Register
4.3.13 : Non-secure Access Control Register
4.3.14 : Virtualization Control Register
4.3.15 : Data Fault Status Register
4.3.16 : TLB Lockdown Register
4.3.17 : PLE ID Register
4.3.18 : PLE Activity Status Register
4.3.19 : PLE FIFO Status Register
4.3.20 : Preload Engine User Accessibility Register
4.3.21 : Preload Engine Parameters Control Register
4.3.22 : Virtualization Interrupt Register
4.3.23 : Power Control Register
4.3.24 : NEON™ Busy Register
4.3.25 : Configuration Base Address Register
4.3.26 : TLB lockdown operations
TLB VA Register bit assignments
TLB PA Register bit assignments
Attributes Register bit assignments
Invalidate TLB Entries on ASID Match
5 : Jazelle® DBX registers
5.1 : About coprocessor CP14
5.2 : CP14 Jazelle® register summary
5.3 : CP14 Jazelle® register descriptions
5.3.1 : Jazelle® ID Register
Write operation of the JIDR
5.3.2 : Jazelle® Operating System Control Register
5.3.3 : Jazelle® Main Configuration Register
5.3.4 : Jazelle® Parameters Register
5.3.5 : Jazelle® Configurable Opcode Translation Table Register
6 : Memory Management Unit
6.1 : About the MMU
6.1.1 : Memory Management Unit
Domains
TLB
ASIDs
System control coprocessor
6.2 : TLB Organization
6.2.1 : Micro TLB
6.2.2 : Main TLB
TLB match process
TLB lockdown
6.3 : Memory access sequence
6.4 : MMU enabling or disabling
6.5 : External aborts
6.5.1 : External aborts on data read or write
6.5.2 : Synchronous and asynchronous aborts
7 : Level 1 Memory System
7.1 : About the L1 memory system
7.1.1 : Memory system
Cache features
Instruction cache features
Data cache features
Store buffer
7.2 : Security Extensions support
7.3 : About the L1 instruction side memory system
7.3.1 : Enabling program flow prediction
7.3.2 : Program flow prediction
Predicted and nonpredicted instructions
Thumb® state conditional branches
Return stack predictions
7.4 : About the L1 data side memory system
7.4.1 : Local Monitor
Treatment of intervening STR operations
LDREX/STREX operations using different sizes
Effect of implementation defined instructions and write operations
7.4.2 : External aborts handling
7.4.3 : Cortex®‑A9 behavior for Normal Memory Cacheable memory regions
7.5 : About DSB
7.6 : Data prefetching
7.6.1 : The PLD instruction
7.6.2 : Data prefetching
7.7 : Parity error support
7.7.1 : GHB and BTAC data corruption
8 : Level 2 Memory Interface
8.1 : About the Cortex®‑A9 L2 interface
8.1.1 : AXI master 0 interface and AXI master 1 interface attributes
8.1.2 : Supported AXI transfers
8.1.3 : AXI transaction IDs
8.1.4 : AXI USER bits
Data side read bus, ARUSERM0[6:0]
Instruction side read bus, ARUSERM1[6:0]
Data side write bus, AWUSERM0[8:0]
8.1.5 : Exclusive L2 cache
8.2 : Optimized accesses to the L2 memory interface
8.2.1 : Prefetch hint to the L2 memory interface
8.2.2 : Early BRESP
8.2.3 : Write full line of zeros
8.2.4 : Speculative coherent requests
8.3 : STRT instructions
9 : Preload Engine
9.1 : About the Preload Engine
9.2 : PLE control register descriptions
9.3 : PLE operations
9.3.1 : Preload Engine FIFO flush operation
9.3.2 : Preload Engine pause channel operation
9.3.3 : Preload Engine resume channel operation
9.3.4 : Preload Engine kill channel operation
9.3.5 : PLE Program New Channel operation
10 : Debug
10.1 : Debug Systems
10.1.1 : Debug host
10.1.2 : Protocol converter
10.1.3 : Debug target
10.2 : About the Cortex®‑A9 debug interface
10.3 : Debug register features
10.3.1 : Processor interfaces
10.3.2 : Breakpoints and watchpoints
10.3.3 : Effects of resets on debug registers
10.4 : Debug register summary
10.5 : Debug register descriptions
10.5.1 : Breakpoint Value Registers
10.5.2 : Breakpoint Control Registers
BCR Register bit assignments
Meaning of the BVR
10.5.3 : Watchpoint Value Registers
10.5.4 : Watchpoint Control Registers
10.6 : Debug management registers
10.6.1 : Peripheral Identification Registers
10.6.2 : Component Identification Registers
10.7 : Debug events
10.7.1 : Watchpoints
10.7.2 : Asynchronous aborts
10.8 : External debug interface
10.8.1 : Debugging modes
10.8.2 : Authentication signals
10.8.3 : Changing the authentication signals
10.8.4 : Debug APB Interface
10.8.5 : External debug request interface
11 : Performance Monitoring Unit
11.1 : About the Performance Monitoring Unit
11.2 : PMU register summary
11.3 : PMU management registers
11.3.1 : Peripheral Identification Registers
11.3.2 : Component Identification Registers
11.4 : Performance monitoring events
11.4.1 : Implemented architectural events
11.4.2 : Cortex®‑A9 specific events
A : Signal Descriptions
A.1 : Clock signals
A.2 : Reset signals
A.3 : Interrupt line signals
A.4 : Configuration signals
A.5 : WFE and WFI standby signals table
A.6 : Power management signals
A.7 : AXI interfaces
A.7.1 : AXI Master0 signals data accesses
Write address channel signals for AXI Master0
Write data channel signals
Write response channel signals
Read address channel signals for AXI Master0
Read data channel signals
AXI Master0 Clock enable signals
A.7.2 : AXI Master1 signals instruction accesses
Read address channel signals for AXI Master1
Read data channel signals
AXI Master1 Clock enable signals
A.8 : Performance monitoring signals
A.8.1 : Event signals and event numbers
A.9 : Exception flags signal
A.10 : Parity signal
A.11 : MBIST interface
A.11.1 : MBIST interface signals
A.11.2 : MBIST signals with parity support implemented
A.11.3 : MBIST signals without parity support implemented
A.12 : Scan test signal
A.13 : External Debug interface signals
A.13.1 : Authentication interface
A.13.2 : APB interface signals
A.13.3 : CTI signals
A.13.4 : Miscellaneous debug interface signals
A.14 : PTM interface signals
B : Cycle Timings and Interlock Behavior
B.1 : About instruction cycle timing
B.2 : Data-processing instructions
B.3 : Load and store instructions
B.3.1 : Single load and store operation cycle timings
B.3.2 : Load multiple operations cycle timings
B.3.3 : Store multiple operations cycle timings
B.4 : Multiplication instructions
B.5 : Branch instructions
B.6 : Serializing instructions
C : Revisions
C.1 : Revisions
ARM® Cortex®-A9
Revision: r4p1
Technical Reference Manual
Copyright © 2008-2012, 2016 ARM. All rights reserved.
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ARM® Cortex®-A9
Technical Reference Manual
Copyright © 2008-2012, 2016 ARM. All rights reserved.
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ARM® Cortex®-A9
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ARM® Cortex®-A9
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Product Status
The information in this document is Final, that is for a developed product.
Web Address
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Contents
ARM® Cortex®-A9 Technical Reference Manual
Chapter 1
Chapter 2
Preface
About this book ..................................................... ..................................................... 14
Feedback .................................................................................................................... 17
Introduction
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
About the Cortex®-A9 processor .............................................................................. 1-19
Processor variants ................................................. ................................................. 1-21
Compliance .............................................................................................................. 1-22
Features .................................................................................................................. 1-23
Interfaces ........................................................ ........................................................ 1-24
Configurable options ................................................................................................ 1-25
Test features ............................................................................................................ 1-26
Product documentation and design flow .................................................................. 1-27
Product revisions .................................................. .................................................. 1-29
Functional Description
2.1
2.2
2.3
2.4
2.5
About the functions .................................................................................................. 2-32
Interfaces ........................................................ ........................................................ 2-34
Clocking and resets ................................................ ................................................ 2-36
Power management ................................................................................................ 2-39
Constraints and limitations of use ............................................................................ 2-43
Chapter 3
Programmers Model
3.1
About the programmers model ................................................................................ 3-45
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3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
ThumbEE architecture .............................................. .............................................. 3-46
The Jazelle® Extension ............................................................................................ 3-47
Advanced SIMD architecture ......................................... ......................................... 3-48
Security Extensions architecture ...................................... ...................................... 3-49
Multiprocessing Extensions .......................................... .......................................... 3-50
Modes of operation and execution .......................................................................... 3-51
Memory model .................................................... .................................................... 3-52
Addresses in the Cortex®-A9 processor .................................................................. 3-53
System Control
4.1
4.2
4.3
About system control ............................................... ............................................... 4-55
Register summary ................................................. ................................................. 4-56
Register descriptions ............................................... ............................................... 4-70
Jazelle® DBX registers
5.1
5.2
5.3
About coprocessor CP14 ........................................... ........................................... 5-102
CP14 Jazelle® register summary ..................................... ..................................... 5-103
CP14 Jazelle® register descriptions ................................... ................................... 5-104
Memory Management Unit
6.1
6.2
6.3
6.4
6.5
About the MMU ...................................................................................................... 6-110
TLB Organization ................................................. ................................................. 6-112
Memory access sequence .......................................... .......................................... 6-114
MMU enabling or disabling .................................................................................... 6-115
External aborts ................................................... ................................................... 6-116
Level 1 Memory System
7.1
7.2
7.3
7.4
7.5
7.6
7.7
About the L1 memory system ................................................................................ 7-118
Security Extensions support .................................................................................. 7-119
About the L1 instruction side memory system ........................... ........................... 7-120
About the L1 data side memory system ................................................................ 7-123
About DSB ...................................................... ...................................................... 7-125
Data prefetching .................................................................................................... 7-126
Parity error support ................................................................................................ 7-127
Level 2 Memory Interface
8.1
8.2
8.3
About the Cortex®-A9 L2 interface .................................... .................................... 8-129
Optimized accesses to the L2 memory interface ......................... ......................... 8-133
STRT instructions .................................................................................................. 8-135
Preload Engine
9.1
9.2
9.3
About the Preload Engine ...................................................................................... 9-137
PLE control register descriptions ..................................... ..................................... 9-138
PLE operations ...................................................................................................... 9-139
Debug
10.1
10.2
10.3
10.4
10.5
Debug Systems ................................................. ................................................. 10-142
About the Cortex®-A9 debug interface ................................ ................................ 10-143
Debug register features ........................................... ........................................... 10-144
Debug register summary .......................................... .......................................... 10-145
Debug register descriptions ........................................ ........................................ 10-147
Chapter 4
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
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Chapter 11
Appendix A
Appendix B
10.6
10.7
10.8
Debug management registers ...................................... ...................................... 10-154
Debug events ...................................................................................................... 10-156
External debug interface ...................................................................................... 10-157
Performance Monitoring Unit
11.1
11.2
11.3
11.4
About the Performance Monitoring Unit ............................... ............................... 11-162
PMU register summary ........................................................................................ 11-163
PMU management registers ................................................................................ 11-165
Performance monitoring events ..................................... ..................................... 11-167
Signal Descriptions
A.1
A.2
A.3
A.4
A.5
A.6
A.7
A.8
A.9
A.10
A.11
A.12
A.13
A.14
Clock signals ................................................................................................ Appx-A-174
Reset signals ............................................... ............................................... Appx-A-175
Interrupt line signals .......................................... .......................................... Appx-A-176
Configuration signals ......................................... ......................................... Appx-A-177
WFE and WFI standby signals table ............................................................ Appx-A-178
Power management signals ........................................................................ Appx-A-179
AXI interfaces .............................................................................................. Appx-A-180
Performance monitoring signals .................................................................. Appx-A-185
Exception flags signal .................................................................................. Appx-A-188
Parity signal ................................................ ................................................ Appx-A-189
MBIST interface ............................................. ............................................. Appx-A-190
Scan test signal ............................................. ............................................. Appx-A-191
External Debug interface signals ................................ ................................ Appx-A-192
PTM interface signals .................................................................................. Appx-A-195
Cycle Timings and Interlock Behavior
B.1
B.2
B.3
B.4
B.5
B.6
About instruction cycle timing ...................................................................... Appx-B-199
Data-processing instructions ................................... ................................... Appx-B-200
Load and store instructions .......................................................................... Appx-B-201
Multiplication instructions ...................................... ...................................... Appx-B-205
Branch instructions ...................................................................................... Appx-B-206
Serializing instructions ........................................ ........................................ Appx-B-207
Appendix C
Revisions
C.1
Revisions .................................................. .................................................. Appx-C-209
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List of Figures
ARM® Cortex®-A9 Technical Reference Manual
Figure 1
Figure 1-1
Figure 2-1
Figure 2-2
Figure 2-3
Figure 2-4
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 4-8
Figure 4-9
Figure 4-10
Figure 4-11
Figure 4-12
Figure 4-13
Figure 4-14
Figure 4-15
Figure 4-16
Figure 4-17
Key to timing diagram conventions ........................................................................................... 16
Cortex-A9 uniprocessor system ............................................................................................ 1-19
Cortex-A9 processor top-level diagram ................................................................................. 2-32
PTM interface signals ............................................................................................................ 2-34
ACLKENM0 used with a 3:1 clock ratio ................................................................................. 2-36
Power domains for the Cortex-A9 processor ......................................................................... 2-42
MIDR bit assignments ........................................................................................................... 4-70
TLBTR bit assignments ......................................................................................................... 4-71
MPIDR bit assignments ......................................................................................................... 4-72
REVIDR bit assignments ....................................................................................................... 4-73
CCSIDR bit assignments ....................................................................................................... 4-74
CLIDR bit assignments .......................................................................................................... 4-75
CSSELR bit assignments ...................................................................................................... 4-77
SCTLR bit assignments ......................................................................................................... 4-78
ACTLR bit assignments ......................................................................................................... 4-81
CPACR bit assignments ........................................................................................................ 4-83
SDER bit assignments ........................................................................................................... 4-84
NSACR bit assignments ........................................................................................................ 4-85
VCR bit assignments ............................................................................................................. 4-87
DFSR bit assignments ........................................................................................................... 4-88
TLB Lockdown Register bit assignments .............................................................................. 4-90
PLEIDR bit assignments ........................................................................................................ 4-91
PLEASR bit assignments ...................................................................................................... 4-91
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7
Figure 4-18
Figure 4-19
Figure 4-20
Figure 4-21
Figure 4-22
Figure 4-23
Figure 4-24
Figure 4-25
Figure 4-26
Figure 4-27
Figure 4-28
Figure 4-29
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 7-1
Figure 7-2
Figure 9-1
Figure 10-1
Figure 10-2
Figure 10-3
Figure 10-4
Figure 10-5
Figure 10-6
PLESFR bit assignments ....................................................................................................... 4-92
PLEUAR bit assignments ...................................................................................................... 4-93
PLEPCR bit assignments ...................................................................................................... 4-93
VIR bit assignments ............................................................................................................... 4-94
Power Control Register bit assignments ............................................................................... 4-95
NEON Busy Register bit assignments ................................................................................... 4-96
Configuration Base Address Register bit assignments ......................................................... 4-97
Lockdown TLB index bit assignments ................................................................................... 4-98
TLB VA Register bit assignments .......................................................................................... 4-98
Memory space identifier format ............................................................................................. 4-99
TLB PA Register bit assignments .......................................................................................... 4-99
Main TLB Attributes Register bit assignments ..................................................................... 4-100
JIDR bit assignments ........................................................................................................... 5-104
JOSCR bit assignments ...................................................................................................... 5-105
JMCR bit assignments ......................................................................................................... 5-106
Jazelle Parameters Register bit assignments ..................................................................... 5-107
Jazelle Configurable Opcode Translation Table Register bit assignments .......................... 5-108
Branch prediction and instruction cache .............................................................................. 7-120
Parity support ...................................................................................................................... 7-127
Program new channel operation bit assignments ................................................................ 9-140
Typical debug system ........................................................................................................ 10-142
Debug registers interface and CoreSight infrastructure .................................................... 10-143
BCR Register bit assignments ........................................................................................... 10-148
WCR Register bit assignments .......................................................................................... 10-151
External debug interface signals ....................................................................................... 10-157
Debug request restart-specific connections ...................................................................... 10-160
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8
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