MC9S12DP256／DG128 Hardware & Basic System Design.pdf

发布时间：2022-06-01 发布人：admin 分类：说明书资料大小：1.65M 资料格式：pdf 举报版权申诉

hanweiwallywang-5531285-4744302543394054204.pdf-第1页.png

第1页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第2页.png

第2页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第3页.png

第3页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第4页.png

第4页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第5页.png

第5页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第6页.png

第6页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第7页.png

第7页 / 共38页

hanweiwallywang-5531285-4744302543394054204.pdf-第8页.png

第8页 / 共38页

文本预览

MC9S12DP256/DG128 Hardware & Basic System Design 清华 Freescale MCU/DSP应用开发研究中心

Chinese Textbook 2007 修订本 2006 修订本

CPU12 Reference Book 458pages

9S12 Documentation MC9S12DP256/DG128 Device User Guide HCS12 V1.5 Core User Guide 128pages 548pages Device User Guide Block User Guides PIM_9DP256 Block User Guide (Port Integrate Module) 54pages 44pages FTS256K Block User Guide (Flach) EETS4K Block User Guide (EEPROM) 35pages CRG Block User Guide Clock Reset Generator 54pages ECT_16B8C Block User Guide (Enhanced Capture Timer) 56pages ATD_10B16C Block User Guide (A/D) SCI Block User Guide SPI Block User Guide PWM_8B8C Block User Guide Inter-Integrated Circuit(IIC)Block Guide MSCAN Block User Guide VREG Block User Guide (Voltage Regulator) BYTE FLIGHT Block Guide BDLC Block Guide(J1850) 35pages 46pages 33pages 51pages 40 pages 73pages 15pages 64 pages 89Pages

Reference Manual (Hardware) 122 pages (2.1M) Data book 9S12DT128B manual 9S12DP256B manual

HCS12 Building Blocks 4K BYTES EEPROM 12K SRAM 256K FLASEEPROM PWM 8 CHAN ECT 8 CHAN SCI 0 SCI 1 Internal Bus SPI 2 or PWM CH 4-7 SPI 1 or PWM CH 0-3 SPI 0 HCS12 CPU BKP INT MMI SIM CM BDM MEBI PLL PIT ms CAN 3 ms CAN 2 ms CAN 1 ms CAN 0 or BDLC PIM VREG ATD 1 ATD 0 CRG ms CAN 4 or IIC • HCS12 CPU Core & System Integration Module • Support Modules: Vreg & Clocks & Reset Generator • Memories: Flash, RAM, EEPROM • Peripherals: SCI,SPI,CAN,IIC, PWM, ATD, Timer, etc.

• 16-bit HCS12 CPU Upward compatible with HC11 20-bit ALU Instruction pipe Enhanced indexed addressing • SIM (System Integ. module) MEB (Multiplexed External Bus) MMC (Module Mapping Control) BKP (Breakpoints) BDM (Background Debug Mode) • Clocks Reset Generator (CRG) low current oscillator, PLL, reset, clocks, COP watchdog, Real time interrupt, clock monitoring Main Features: • On-chip Voltage Regulator 2.25 to 2.75V Digital Supply Voltage 4.75V to 5.25V Analog and I/O Voltage • Technology: 0.25 micron CMOS 50 MHz CPU equivalent to 25MHz bus operation (66/33MHz in design)

Peripherals 2 x Serial Communications Interface (SCI) 3 x Serial Peripheral interface (SPI) up to 5 x 1M b/s, CAN 2.0 A, B msCAN module Byte Data Link Controller (BDLC,J1850) Inter-IC Bus (IIC) 10-bit Analog-to-Digital Converter Standard 8 channel Timer Enhanced Capture Timer (ECT) PWM module Stepper Motor controller • • • • • • • • • •

分享到：

赞收藏

资料库

MC9S12DP256／DG128 Hardware & Basic System Design.pdf

相关推荐

行业

热门标签

最新资料