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RTL8367S-CG.pdf
1. General Description
2. Features
3. System Applications
4. Application Examples
4.1. 5-Port 1000Base-T Switch
4.2. 5-Port 1000Base-T Router with SGMII/HSGMII and/or MII/RGMII
5. Block Diagram
6. Pin Assignments
6.1. Package Identification
6.2. Pin Assignments Table
7. Pin Descriptions
7.1. Media Dependent Interface Pins
7.2. High Speed Serial Interface Pins
7.3. General Purpose Interfaces
7.3.1. RGMII Pins
7.3.2. MII Pins
7.4. LED Pins
7.5. Configuration Strapping Pins
7.5.1. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF)
7.6. Management Interface Pins
7.7. Miscellaneous Pins
7.8. Test Pins
7.9. Power and GND Pins
8. Physical Layer Functional Overview
8.1. MDI Interface
8.2. 1000Base-T Transmit Function
8.3. 1000Base-T Receive Function
8.4. 100Base-TX Transmit Function
8.5. 100Base-TX Receive Function
8.6. 10Base-T Transmit Function
8.7. 10Base-T Receive Function
8.8. Auto-Negotiation for UTP
8.9. Crossover Detection and Auto Correction
8.10. Polarity Correction
9. General Function Description
9.1. Reset
9.1.1. Hardware Reset
9.1.2. Software Reset
9.1.2.1 CHIP_RESET
9.1.2.2 SOFT_RESET
9.2. IEEE 802.3x Full Duplex Flow Control
9.3. Half Duplex Flow Control
9.3.1. Back-Pressure Mode
9.4. Search and Learning
9.5. SVL and IVL/SVL
9.6. Illegal Frame Filtering
9.7. IEEE 802.3 Reserved Group Addresses Filtering Control
9.8. Broadcast/Multicast/Unknown DA Storm Control
9.9. Port Security Function
9.10. MIB Counters
9.11. Port Mirroring
9.12. VLAN Function
9.12.1. Port-Based VLAN
9.12.2. IEEE 802.1Q Tag-Based VLAN
9.12.3. Protocol-Based VLAN
9.12.4. Port VID
9.13. QoS Function
9.13.1. Input Bandwidth Control
9.13.2. Priority Assignment
9.13.3. Priority Queue Scheduling
9.13.4. IEEE 802.1p/Q and DSCP Remarking
9.13.5. ACL-Based Priority
9.14. IGMP & MLD Snooping Function
9.15. IEEE 802.1x Function
9.15.1. Port-Based Access Control
9.15.2. Authorized Port-Based Access Control
9.15.3. Port-Based Access Control Direction
9.15.4. MAC-Based Access Control
9.15.5. MAC-Based Access Control Direction
9.15.6. Optional Unauthorized Behavior
9.15.7. Guest VLAN
9.16. IEEE 802.1D Function
9.17. Embedded 8051
9.18. Realtek Cable Test (RTCT)
9.19. LED Indicators
9.20. Green Ethernet
9.20.1. Link-On and Cable Length Power Saving
9.20.2. Link-Down Power Saving
9.21. IEEE 802.3az Energy Efficient Ethernet (EEE) Function
9.22. Interrupt Pin for External CPU
10. Interface Descriptions
10.1. EEPROM SMI Host to EEPROM
10.2. EEPROM SMI Slave for External CPU
10.3. General Purpose Interface
10.3.1. Extension Ports RGMII Mode Interface (1Gbps)
10.3.2. Extension Ports MII MAC/PHY Mode Interface (10/100Mbps)
11. Register Descriptions
11.1. PCS Register (PHY 0~4)
11.2. Register 0: Control
11.3. Register 1: Status
11.4. Register 2: PHY Identifier 1
11.5. Register 3: PHY Identifier 2
11.6. Register 4: Auto-Negotiation Advertisement
11.7. Register 5: Auto-Negotiation Link Partner Ability
11.8. Register 6: Auto-Negotiation Expansion
11.9. Register 7: Auto-Negotiation Page Transmit Register
11.10. Register 8: Auto-Negotiation Link Partner Next Page Register
11.11. Register 9: 1000Base-T Control Register
11.12. Register 10: 1000Base-T Status Register
11.13. Register 15: Extended Status
12. Electrical Characteristics
12.1. Absolute Maximum Ratings
12.2. Recommended Operating Range
12.3. Thermal Characteristics
12.3.1. Assembly Description
12.3.2. Material Properties
12.3.3. Simulation Conditions
12.3.4. Thermal Performance of LQFP-128 on PCB Under Still Air Convection
12.4. DC Characteristics
12.5. AC Characteristics
12.5.1. EEPROM SMI Host Mode Timing Characteristics
12.5.2. EEPROM SMI Slave Mode Timing Characteristics
12.5.3. MDIO Slave Mode Timing Characteristics
12.5.4. MII MAC Mode Timing
12.5.5. MII PHY Mode Timing
12.5.6. RGMII Timing Characteristics
12.5.7. HSGMII Characteristics
12.5.8. SGMII Characteristics
12.6. Power and Reset Characteristics
13. Mechanical Dimensions
14. Ordering Information
RTL8367S-CG
LAYER 2 MANAGED 5+2-PORT
10/100/1000M SWITCH CONTROLLER
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. Pre-0.94
11 Jan 2016
Track ID: xxxx-xxxx-xx
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
RTL8367S
Datasheet
COPYRIGHT
©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8367S IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Summary
Preliminary release.
1. Revised Section 6. Pin Assignments
2. Revised Section 6.2. Pin Assignments Table
3. Revised Section 7.3. General Purpose Interfaces
4. Revised Section 7.5. Configuration Strapping Pins
5. Revised Section 7.6. Management
6. Revised Section 7.7. Miscellaneous Pins
1. Revised Section 6. Pin Assignments
2. Revised Section 6.2. Pin Assignments Table
3. Revised Section 7.3. General Purpose Interfaces
4. Revised Section 7.5. Configuration Strapping Pins
5. Revised Section 7.6. Management Interface Pins
6. Revised Section 7.7. Miscellaneous Pins
7. Revised Section 9.19. LED Indicators
8. Revised Section 12.2. Recommended Operating Range
9. Add Section 12.5.7. HSGMII Characteristics
10. Add Section 12.5.8. SGMII Characteristics
Revision
Pre-0.9
Pre-0.91
Release Date
2015/08/06
2015/08/18
Pre-0.92
2015/11/18
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
ii
Track ID: xxxx-xxxx-xx Rev. Pre-0.94
RTL8367S
Datasheet
Revision
Pre-0.93
Release Date
2015/12/30
Summary
1. Revised Section 12.2. Recommended Operating Range
2. Revised Section 12.3.1. Assembly Description
3. Revised Section 12.3.2. Material Properties
4. Revised Section 12.3.3. Simulation Conditions
5. Revised Section 12.3.4. Thermal Performance of LQFP-128 on PCB Under Still
6. Delete Section 12.3.5. Thermal Performance of LQFP-128 on PCB Under Forced
Air Convection
Convection
Pre-0.94
2016/01/11
1. Revised Section 12.5.2. EEPROM SMI Slave Mode Timing Characteristics
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Table of Contents
RTL8367S
Datasheet
4.1.
4.2.
6.1.
6.2.
7.1.
7.2.
7.3.
5.
6.
7.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
1. GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................3
2.
3.
SYSTEM APPLICATIONS...............................................................................................................................................5
4. APPLICATION EXAMPLES ...........................................................................................................................................5
5-PORT 1000BASE-T SWITCH ......................................................................................................................................5
5-PORT 1000BASE-T ROUTER WITH SGMII/HSGMII AND/OR MII/RGMII ................................................................6
BLOCK DIAGRAM...........................................................................................................................................................7
PIN ASSIGNMENTS .........................................................................................................................................................8
PACKAGE IDENTIFICATION...........................................................................................................................................8
PIN ASSIGNMENTS TABLE............................................................................................................................................9
PIN DESCRIPTIONS.......................................................................................................................................................12
MEDIA DEPENDENT INTERFACE PINS.........................................................................................................................12
HIGH SPEED SERIAL INTERFACE PINS ........................................................................................................................13
GENERAL PURPOSE INTERFACES................................................................................................................................13
7.3.1. RGMII Pins...........................................................................................................................................................15
7.3.2. MII Pins................................................................................................................................................................16
LED PINS...................................................................................................................................................................18
CONFIGURATION STRAPPING PINS .............................................................................................................................19
7.5.1. Configuration Strapping Pins (DISAUTOLOAD, DIS_8051, and EN_SPIF)......................................................20
MANAGEMENT INTERFACE PINS ................................................................................................................................21
MISCELLANEOUS PINS ...............................................................................................................................................21
TEST PINS ..................................................................................................................................................................23
POWER AND GND PINS..............................................................................................................................................23
PHYSICAL LAYER FUNCTIONAL OVERVIEW......................................................................................................24
MDI INTERFACE ........................................................................................................................................................24
1000BASE-T TRANSMIT FUNCTION ...........................................................................................................................24
1000BASE-T RECEIVE FUNCTION ..............................................................................................................................24
100BASE-TX TRANSMIT FUNCTION...........................................................................................................................24
100BASE-TX RECEIVE FUNCTION .............................................................................................................................25
10BASE-T TRANSMIT FUNCTION ...............................................................................................................................25
10BASE-T RECEIVE FUNCTION ..................................................................................................................................25
AUTO-NEGOTIATION FOR UTP ..................................................................................................................................25
CROSSOVER DETECTION AND AUTO CORRECTION.....................................................................................................26
POLARITY CORRECTION.............................................................................................................................................26
9. GENERAL FUNCTION DESCRIPTION......................................................................................................................27
RESET ........................................................................................................................................................................27
9.1.1. Hardware Reset....................................................................................................................................................27
Software Reset ......................................................................................................................................................27
9.1.2.
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................27
HALF DUPLEX FLOW CONTROL .................................................................................................................................28
9.3.1. Back-Pressure Mode ............................................................................................................................................28
SEARCH AND LEARNING ............................................................................................................................................29
SVL AND IVL/SVL ...................................................................................................................................................29
ILLEGAL FRAME FILTERING .......................................................................................................................................29
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL.............................................................................30
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
9.1.
9.2.
9.3.
9.4.
9.5.
9.6.
9.7.
8.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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RTL8367S
Datasheet
10.
11.
10.3.1.
10.3.2.
9.14.
9.15.
9.15.1.
9.15.2.
9.15.3.
9.15.4.
9.15.5.
9.15.6.
9.15.7.
9.12.1.
9.12.2.
9.12.3.
9.12.4.
9.13.1.
9.13.2.
9.13.3.
9.13.4.
9.13.5.
9.8.
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL .....................................................................................31
PORT SECURITY FUNCTION........................................................................................................................................31
9.9.
9.10. MIB COUNTERS.........................................................................................................................................................31
9.11.
PORT MIRRORING ......................................................................................................................................................31
9.12. VLAN FUNCTION ......................................................................................................................................................32
Port-Based VLAN ............................................................................................................................................32
IEEE 802.1Q Tag-Based VLAN.......................................................................................................................32
Protocol-Based VLAN .....................................................................................................................................33
Port VID ..........................................................................................................................................................33
9.13. QOS FUNCTION..........................................................................................................................................................34
Input Bandwidth Control .................................................................................................................................34
Priority Assignment .........................................................................................................................................34
Priority Queue Scheduling...............................................................................................................................34
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................35
ACL-Based Priority .........................................................................................................................................35
IGMP & MLD SNOOPING FUNCTION.........................................................................................................................36
IEEE 802.1X FUNCTION.............................................................................................................................................37
Port-Based Access Control..............................................................................................................................37
Authorized Port-Based Access Control ...........................................................................................................37
Port-Based Access Control Direction..............................................................................................................37
MAC-Based Access Control.............................................................................................................................37
MAC-Based Access Control Direction ............................................................................................................38
Optional Unauthorized Behavior.....................................................................................................................38
Guest VLAN .....................................................................................................................................................38
IEEE 802.1D FUNCTION ............................................................................................................................................38
9.16.
EMBEDDED 8051........................................................................................................................................................38
9.17.
9.18. REALTEK CABLE TEST (RTCT) .................................................................................................................................39
LED INDICATORS.......................................................................................................................................................39
9.19.
9.20. GREEN ETHERNET......................................................................................................................................................41
Link-On and Cable Length Power Saving .......................................................................................................41
Link-Down Power Saving ................................................................................................................................41
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ...............................................................................41
INTERRUPT PIN FOR EXTERNAL CPU.........................................................................................................................41
INTERFACE DESCRIPTIONS .................................................................................................................................42
10.1.
EEPROM SMI HOST TO EEPROM ...........................................................................................................................42
EEPROM SMI SLAVE FOR EXTERNAL CPU..............................................................................................................43
10.2.
10.3. GENERAL PURPOSE INTERFACE..................................................................................................................................44
Extension Ports RGMII Mode Interface (1Gbps) ............................................................................................45
Extension Ports MII MAC/PHY Mode Interface (10/100Mbps) ......................................................................45
REGISTER DESCRIPTIONS ....................................................................................................................................48
PCS REGISTER (PHY 0~4).........................................................................................................................................48
11.1.
11.2. REGISTER 0: CONTROL...............................................................................................................................................49
11.3. REGISTER 1: STATUS..................................................................................................................................................50
11.4. REGISTER 2: PHY IDENTIFIER 1.................................................................................................................................51
11.5. REGISTER 3: PHY IDENTIFIER 2.................................................................................................................................51
11.6. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT .................................................................................................51
11.7. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY.......................................................................................52
11.8. REGISTER 6: AUTO-NEGOTIATION EXPANSION..........................................................................................................53
11.9. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER..................................................................................53
11.10.
REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER ............................................................54
REGISTER 9: 1000BASE-T CONTROL REGISTER ....................................................................................................54
11.11.
11.12.
REGISTER 10: 1000BASE-T STATUS REGISTER .....................................................................................................55
11.13.
REGISTER 15: EXTENDED STATUS.........................................................................................................................55
9.20.1.
9.20.2.
9.21.
9.22.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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RTL8367S
Datasheet
12.
12.6.
13.
14.
12.3.1.
12.3.2.
12.3.3.
12.3.4.
ELECTRICAL CHARACTERISTICS......................................................................................................................56
12.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................56
12.2. RECOMMENDED OPERATING RANGE..........................................................................................................................56
12.3.
THERMAL CHARACTERISTICS.....................................................................................................................................57
Assembly Description ......................................................................................................................................57
Material Properties .........................................................................................................................................57
Simulation Conditions .....................................................................................................................................57
Thermal Performance of LQFP-128 on PCB Under Still Air Convection.......................................................58
12.4. DC CHARACTERISTICS...............................................................................................................................................59
12.5. AC CHARACTERISTICS...............................................................................................................................................60
EEPROM SMI Host Mode Timing Characteristics .........................................................................................60
EEPROM SMI Slave Mode Timing Characteristics ........................................................................................61
MDIO Slave Mode Timing Characteristics .....................................................................................................62
MII MAC Mode Timing ...................................................................................................................................63
MII PHY Mode Timing ....................................................................................................................................64
RGMII Timing Characteristics ........................................................................................................................65
HSGMII Characteristics..................................................................................................................................67
SGMII Characteristics.....................................................................................................................................69
POWER AND RESET CHARACTERISTICS ......................................................................................................................71
MECHANICAL DIMENSIONS.................................................................................................................................72
ORDERING INFORMATION...................................................................................................................................73
12.5.1.
12.5.2.
12.5.3.
12.5.4.
12.5.5.
12.5.6.
12.5.7.
12.5.8.
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: xxxx-xxxx-xx Rev. Pre-0.94
List of Tables
RTL8367S
Datasheet
TABLE 1. PIN ASSIGNMENTS TABLE ..............................................................................................................................................9
TABLE 2. MEDIA DEPENDENT INTERFACE PINS...........................................................................................................................12
TABLE 3. GENERAL PURPOSE INTERFACES PINS..........................................................................................................................13
TABLE 4. EXTENSION GMAC2 RGMII PINS ...............................................................................................................................15
TABLE 5. EXTENSION GMAC2 MII PINS (MII MAC MODE OR MII PHY MODE).......................................................................16
TABLE 6. LED PINS.....................................................................................................................................................................18
TABLE 7. CONFIGURATION STRAPPING PINS................................................................................................................................19
TABLE 8. CONFIGURATION STRAPPING PINS (DISAUTOLOAD, DIS_8051, AND EN_SPIF) ......................................................20
TABLE 9. MANAGEMENT INTERFACE PINS ....................................................................................................................................21
TABLE 10. MISCELLANEOUS PINS .................................................................................................................................................21
TABLE 11. TEST PINS ....................................................................................................................................................................23
TABLE 12. POWER AND GND PINS................................................................................................................................................23
TABLE 13. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................26
TABLE 14. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE.........................................................................................30
TABLE 15. IPV4/IPV6 MULTICAST ROUTING PROTOCOLS.............................................................................................................36
TABLE 16. LED DEFINITIONS........................................................................................................................................................39
TABLE 17. RTL8367S EXTENSION PORT 2 PIN DEFINITIONS ........................................................................................................44
TABLE 18. EXTENSION GMAC2 RGMII PINS...............................................................................................................................45
TABLE 19. EXTENSION GMAC2 MII PINS ....................................................................................................................................45
TABLE 20. PCS REGISTER (PHY 0~4)...........................................................................................................................................48
TABLE 21. REGISTER 0: CONTROL ................................................................................................................................................49
TABLE 22. REGISTER 1: STATUS....................................................................................................................................................50
TABLE 23. REGISTER 2: PHY IDENTIFIER 1...................................................................................................................................51
TABLE 24. REGISTER 3: PHY IDENTIFIER 2...................................................................................................................................51
TABLE 25. REGISTER 4: AUTO-NEGOTIATION ADVERTISEMENT...................................................................................................51
TABLE 26. REGISTER 5: AUTO-NEGOTIATION LINK PARTNER ABILITY ........................................................................................52
TABLE 27. REGISTER 6: AUTO-NEGOTIATION EXPANSION............................................................................................................53
TABLE 28. REGISTER 7: AUTO-NEGOTIATION PAGE TRANSMIT REGISTER....................................................................................53
TABLE 29. REGISTER 8: AUTO-NEGOTIATION LINK PARTNER NEXT PAGE REGISTER...................................................................54
TABLE 30. REGISTER 9: 1000BASE-T CONTROL REGISTER...........................................................................................................54
TABLE 31. REGISTER 10: 1000BASE-T STATUS REGISTER............................................................................................................55
TABLE 32. REGISTER 15: EXTENDED STATUS ...............................................................................................................................55
TABLE 33. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................56
TABLE 34. RECOMMENDED OPERATING RANGE ...........................................................................................................................56
TABLE 35. ASSEMBLY DESCRIPTION.............................................................................................................................................57
TABLE 36. MATERIAL PROPERTIES ...............................................................................................................................................57
TABLE 37. SIMULATION CONDITIONS ...........................................................................................................................................57
TABLE 38. THERMAL PERFORMANCE OF LQFP-128 ON PCB UNDER STILL AIR CONVECTION.....................................................58
TABLE 39. THERMAL PERFORMANCE OF LQFP-128 ON PCB UNDER FORCED CONVECTION......................錯誤! 尚未定義書籤。
TABLE 40. DC CHARACTERISTICS.................................................................................................................................................59
TABLE 41. EEPROM SMI HOST MODE TIMING CHARACTERISTICS.............................................................................................61
TABLE 42. EEPROM SMI SLAVE MODE TIMING CHARACTERISTICS ...........................................................................................61
TABLE 43. MDIO TIMING CHARACTERISTICS AND REQUIREMENT ...............................................................................................62
TABLE 44. MII MAC MODE TIMING.............................................................................................................................................63
TABLE 45. MII PHY MODE TIMING CHARACTERISTICS................................................................................................................64
TABLE 46. RGMII TIMING CHARACTERISTICS..............................................................................................................................66
TABLE 47. HSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS.........................................................................................67
TABLE 48. HSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ...............................................................................................68
TABLE 49. SGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS............................................................................................69
TABLE 50. SGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ..................................................................................................70
TABLE 51. POWER AND RESET CHARACTERISTICS........................................................................................................................71
TABLE 52. ORDERING INFORMATION ............................................................................................................................................73
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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RTL8367S
Datasheet
Layer 2 Managed 5+2-Port 10/100/1000M Switch Controller
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Track ID: xxxx-xxxx-xx Rev. Pre-0.94
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