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基于VHDL动态扫描数字时钟.docx

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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY eda1 IS PORT ( CLK:IN STD_LOGIC; C_OUT:OUT STD_LOGIC_VECTOR(6 DOWNTO 0); L0,L1,L2,L3,L4,L5:OUT STD_LOGIC); END ENTITY; ARCHITECTURE BHV OF eda1 IS SIGNAL Q:INTEGER RANGE 0 TO 50000000; SIGNAL SEL:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL CLK2:STD_LOGIC; SIGNAL S1:STD_LOGIC; SIGNAL S10:STD_LOGIC; SIGNAL m1:STD_LOGIC; SIGNAL m10:STD_LOGIC; SIGNAL h1:STD_LOGIC; SIGNAL h10:STD_LOGIC; SIGNAL SEC1:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL SEC10:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL MIN1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL MIN10: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL HOUR1: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL HOUR10: STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN IF Q=50000000 THEN CLK2<='1';Q<=0; ELSE CLK2<='0';Q<=Q+1; END IF; END IF; END PROCESS; PROCESS(CLK2) BEGIN IF CLK2'EVENT AND CLK2='1' THEN IF SEC1<"1001" THEN SEC1<=SEC1+1;S1<='0'; ELSE SEC1<="0000";S1<='1'; END IF; END IF; END PROCESS; PROCESS(S1) BEGIN IF CLK2'EVENT AND CLK2='1' THEN IF S1='1' THEN
IF SEC10="0101" THEN SEC10<="0000";S10<='1'; ELSE SEC10<=SEC10+1;S10<='0'; END IF; END IF; END IF; END PROCESS; PROCESS(S10) BEGIN IF CLK2'EVENT AND CLK2='1' THEN IF S10='1' THEN IF MIN1="1001" THEN MIN1<="0000"; M1<='1'; ELSE MIN1<=MIN1+1; M1<='0'; END IF; END IF; END IF; END PROCESS; PROCESS(M1) BEGIN IF CLK2'EVENT AND CLK2='1' THEN IF M1='1' THEN IF MIN10="0101" THEN MIN10<="0000";M10<='1'; ELSE MIN10<=MIN10+1; M10<='0'; END IF; END IF; END IF; END PROCESS; PROCESS(M10) BEGIN IF CLK2'EVENT AND CLK2='1' THEN IF M10='1' THEN IF (HOUR1="1001")OR((HOUR1="0100")AND(HOUR10="0010")) THEN HOUR1<="0000";H1<='1'; ELSE HOUR1<=HOUR1+1; H1<='0'; END IF; END IF; END IF; END PROCESS;
PROCESS(CLK) BEGIN IF CLK2'EVENT AND CLK2='1' THEN IF SEL="110" THEN SEL<="000"; ELSE SEL<=SEL+1; END IF; END IF; END PROCESS; PROCESS(SEL) BEGIN IF SEL= "000" THEN L0<='1'; CASE SEC1 IS WHEN "0000" => C_OUT<="0111111"; WHEN "0001" => C_OUT<="0000110"; WHEN "0010" => C_OUT<="1011011"; WHEN "0011" => C_OUT<="1001111"; WHEN "0100" => C_OUT<="1100110"; WHEN "0101" => C_OUT<="1101101"; WHEN "0110" => C_OUT<="1111101"; WHEN "0111" => C_OUT<="0000111"; WHEN "1000" => C_OUT<="1111111"; WHEN "1001" => C_OUT<="1101111"; WHEN OTHERS => C_OUT<="ZZZZZZZ"; END CASE; ELSIF SEL= "001" THEN L1<='1'; CASE SEC10 IS WHEN "0000" => C_OUT<="0111111"; WHEN "0001" => C_OUT<="0000110"; WHEN "0010" => C_OUT<="1011011"; WHEN "0011" => C_OUT<="1001111"; WHEN "0100" => C_OUT<="1100110"; WHEN "0101" => C_OUT<="1101101"; WHEN OTHERS => C_OUT<="ZZZZZZZ"; END CASE; ELSIF SEL= "010" THEN L2<='1'; CASE MIN1 IS WHEN "0000" => C_OUT<="0111111"; WHEN "0001" => C_OUT<="0000110"; WHEN "0010" => C_OUT<="1011011"; WHEN "0011" => C_OUT<="1001111"; WHEN "0100" => C_OUT<="1100110"; WHEN "0101" => C_OUT<="1101101"; WHEN "0110" => C_OUT<="1111101";
WHEN "0111" => C_OUT<="0000111"; WHEN "1000" => C_OUT<="1111111"; WHEN "1001" => C_OUT<="1101111"; WHEN OTHERS => C_OUT<="ZZZZZZZ"; END CASE; ELSIF SEL= "011" THEN L3<='1'; CASE MIN10 IS WHEN "0000" => C_OUT<="0111111"; WHEN "0001" => C_OUT<="0000110"; WHEN "0010" => C_OUT<="1011011"; WHEN "0011" => C_OUT<="1001111"; WHEN "0100" => C_OUT<="1100110"; WHEN "0101" => C_OUT<="1101101"; WHEN OTHERS => C_OUT<="ZZZZZZZ"; END CASE; ELSIF SEL= "100" THEN L4<='1'; CASE HOUR1 IS WHEN "0000" => C_OUT<="0111111"; WHEN "0001" => C_OUT<="0000110"; WHEN "0010" => C_OUT<="1011011"; WHEN "0011" => C_OUT<="1001111"; WHEN "0100" => C_OUT<="1100110"; WHEN "0101" => C_OUT<="1101101"; WHEN "0110" => C_OUT<="1111101"; WHEN "0111" => C_OUT<="0000111"; WHEN "1000" => C_OUT<="1111111"; WHEN "1001" => C_OUT<="1101111"; WHEN OTHERS => C_OUT<="ZZZZZZZ"; END CASE; ELSIF SEL= "101" THEN L5<='1'; CASE HOUR10 IS WHEN "0000" => C_OUT<="0111111"; WHEN "0001" => C_OUT<="0000110"; WHEN OTHERS => C_OUT<="ZZZZZZZ"; END CASE; END IF; END PROCESS; END ARCHITECTURE;
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