第1页 / 共15页
第2页 / 共15页
第3页 / 共15页
第4页 / 共15页
第5页 / 共15页
第6页 / 共15页
第7页 / 共15页
第8页 / 共15页
AT89C51说明书.pdf
Features
• Compatible with MCS-51™ Products
• 4K Bytes of In-System Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-Bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial Channel
• Low Power Idle and Power Down Modes
Description
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatible with the industry standard MCS-51™ instruction set and pinout. The
on-chip Flash allows the program memory to be reprogrammed in-system or by a con-
ventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with
Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
Pin Configurations
(continued)
PDIP
8-Bit
Microcontroller
with 4K Bytes
Flash
AT89C51
P 1 . 0
P 1 . 1
P 1 . 2
P 1 . 3
P 1 . 4
P 1 . 5
P 1 . 6
P 1 . 7
R S T
( R X D ) P 3 . 0
( T X D ) P 3 . 1
I N T 0
) P 3 . 2
) P 3 . 3
I N T 1
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
) P 3 . 6
W R
(
(
R D
) P 3 . 7
X TA L 2
X TA L 1
G N D
(
(
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
V C C
P 0 . 0 ( A D 0 )
P 0 . 1 ( A D 1 )
P 0 . 2 ( A D 2 )
P 0 . 3 ( A D 3 )
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
P 2 . 4 ( A 1 2 )
P 2 . 3 ( A 1 1 )
P 2 . 2 ( A 1 0 )
P 2 . 1 ( A 9 )
P 2 . 0 ( A 8 )
PLCC
)
0
D
A
)
1
D
A
)
2
D
A
)
3
D
A
(
(
(
(
I N D E X
C O R N E R
4
.
1
P
3
.
1
P
2
.
1
P
1
.
1
P
0
.
1
P
C
N
C
C
V
0
.
0
P
1
.
0
P
2
.
0
P
3
.
0
P
4
3
5
2
4 4
4 2
4 3
1
4 1
PQFP/TQFP
)
0
D
A
)
1
D
A
)
2
D
A
)
3
D
A
(
(
(
(
I N D E X
C O R N E R
4
.
1
P
3
.
1
P
2
.
1
P
1
.
1
P
0
.
1
P
C
N
C
C
V
0
.
0
P
1
.
0
P
2
.
0
P
3
.
0
P
4 4
4 3
4 2
P 1 . 5
P 1 . 6
P 1 . 7
R S T
( R X D ) P 3 . 0
N C
( T X D ) P 3 . 1
I N T 0
) P 3 . 2
) P 3 . 3
I N T 1
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
(
(
1
2
3
4
5
6
7
8
9
1 0
1 1
4 0
4 1
3 9
3 8
3 6
3 7
3 4
3 5
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
N C
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
1 3
1 5
1 7
1 9
2 1
2 2
2 0
1 8
1 6
1 4
1 2
2
L
A
T
X
1
L
A
T
X
6
.
3
P
7
.
3
P
)
)
R
W
(
D
R
(
D
N
G
D
N
G
0
.
2
P
1
.
2
P
2
.
2
P
3
.
2
P
4
.
2
P
)
8
A
)
9
A
(
(
)
0
1
A
)
1
1
A
)
2
1
A
(
(
(
P 1 . 5
P 1 . 6
P 1 . 7
R S T
( R X D ) P 3 . 0
N C
( T X D ) P 3 . 1
) P 3 . 2
I N T 0
I N T 1
) P 3 . 3
( T 0 ) P 3 . 4
( T 1 ) P 3 . 5
(
(
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
P 0 . 4 ( A D 4 )
P 0 . 5 ( A D 5 )
P 0 . 6 ( A D 6 )
P 0 . 7 ( A D 7 )
E A / V P P
N C
A L E / P R O G
P S E N
P 2 . 7 ( A 1 5 )
P 2 . 6 ( A 1 4 )
P 2 . 5 ( A 1 3 )
1 9
2 5
2 7
2 6
2 1
2 3
2 2
2 4
2 0
2
L
A
T
X
1
L
A
T
X
6
.
3
P
7
.
3
P
)
)
R
W
(
D
R
(
D
N
G
C
N
0
.
2
P
1
.
2
P
2
.
2
P
3
.
2
P
4
.
2
P
)
8
A
(
)
9
A
(
)
0
1
A
)
1
1
A
)
2
1
A
(
(
(
0265F-A–12/97
4-29
Block Diagram
VCC
GND
P0.0 - P0.7
P2.0 - P2.7
PORT 0 DRIVERS
PORT 2 DRIVERS
RAM ADDR.
REGISTER
RAM
PORT 0
LATCH
PORT 2
LATCH
FLASH
B
REGISTER
ACC
STACK
POINTER
TMP2
TMP1
ALU
PSW
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
INSTRUCTION
REGISTER
PORT 1
LATCH
PORT 3
LATCH
PSEN
ALE/PROG
EA / VPP
RST
TIMING
AND
CONTROL
OSC
PORT 1 DRIVERS
PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
4-30
AT89C51
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
The AT89C51 provides the following standard features: 4K
bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit
timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock cir-
cuitry. In addition, the AT89C51 is designed with static logic
for operation down to zero frequency and supports two
software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The
Power Down Mode saves the RAM contents but freezes
the oscillator disabling all other chip functions until the next
hardware reset.
Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 may also be configured to be the multiplexed low-
order address/data bus during accesses to external pro-
gram and data memory. In this mode P0 has internal pul-
lups.
Port 0 also receives the code bytes during Flash program-
ming, and outputs the code bytes during program verifica-
tion. External pullups are required during program verifica-
tion.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 1 also receives the low-order address bytes during
Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application it uses strong internal pullups
AT89C51
when emitting 1s. During accesses to external data mem-
ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (IIL) because of the pullups.
Port 3 also serves the functions of various special features
of the AT89C51 as listed below:
Port Pin
Alternate Functions
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (timer 0 external input)
T1 (timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
Port 3 also receives some control signals for Flash pro-
gramming and verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE/PROG
Address Latch Enable output pulse for latching the low byte
of the address during accesses to external memory. This
pin is also the program pulse input (PROG) during Flash
programming.
In normal operation ALE is emitted at a constant rate of 1/6
the oscillator frequency, and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external Data Mem-
ory.
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
4-31
When the AT89C51 is executing code from external pro-
gram memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during
each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
EA should be strapped to VCC for internal program execu-
tions.
This pin also receives the 12-volt programming enable volt-
age (VPP) during Flash programming, for parts that require
12-volt VPP.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively,
of an inverting amplifier which can be configured for use as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maxi-
mum voltage high and low time specifications must be
observed.
It should be noted that when idle is terminated by a hard
ware reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles before
the internal reset algorithm takes control. On-chip hardware
inhibits access to internal RAM in this event, but access to
the port pins is not inhibited. To eliminate the possibility of
an unexpected write to a port pin when Idle is terminated by
reset, the instruction following the one that invokes Idle
should not be one that writes to a port pin or to external
memory.
Figure 1. Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
Note:
C1, C2 = 30 pF – 10 pF for Crystals
= 40 pF – 10 pF for Ceramic Resonators
Figure 2. External Clock Drive Configuration
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-
chip peripherals remain active. The mode is invoked by
software. The content of the on-chip RAM and all the spe-
cial functions registers remain unchanged during this
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset.
Status of External Pins During Idle and Power Down Modes
Mode
Idle
Idle
Power Down
Power Down
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Data
Float
Data
Float
Data
Data
Data
Data
Data
Address
Data
Data
Data
Data
Data
Data
4-32
AT89C51
AT89C51
Program Memory Lock Bits
On the chip are three lock bits which can be left unpro-
grammed (U) or can be programmed (P) to obtain the addi-
tional features listed in the table below:
When lock bit 1 is programmed, the logic level at the EA pin
is sampled and latched during reset. If the device is pow-
ered up without a reset, the latch initializes to a random
value, and holds that value until reset is activated. It is nec-
essary that the latched value of EA be in agreement with
the current logic level at that pin in order for the device to
function properly.
Power Down Mode
In the power down mode the oscillator is stopped, and the
instruction that invokes power down is the last instruction
executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
nated. The only exit from power down is a hardware reset.
Reset redefines the SFRs but does not change the on-chip
RAM. The reset should not be activated before VCC is
restored to its normal operating level and must be held
active long enough to allow the oscillator to restart and sta-
bilize.
Lock Bit Protection Modes
Program Lock Bits
Protection Type
LB1
LB2
LB3
1
2
3
4
U
P
P
P
U
U
P
P
U
U
U
P
No program lock features.
MOVC instructions executed from external program memory are disabled from fetching code
bytes from internal memory, EA is sampled and latched on reset, and further programming of the
Flash is disabled.
Same as mode 2, also verify is disabled.
Same as mode 3, also external execution is disabled.
Programming the Flash
The AT89C51 is normally shipped with the on-chip Flash
memory array in the erased state (that is, contents = FFH)
and ready to be programmed. The programming interface
accepts either a high-voltage (12-volt) or a low-voltage
(VCC) program enable signal. The low voltage program-
ming mode provides a convenient way to program the
AT89C51 inside the user’s system, while the high-voltage
programming mode is compatible with conventional third
party Flash or EPROM programmers.
The AT89C51 is shipped with either the high-voltage or
low-voltage programming mode enabled. The respective
top-side marking and device signature codes are listed in
the following table.
Top-Side Mark
Signature
VPP = 12V
AT89C51
xxxx
yyww
(030H)=1EH
(031H)=51H
(032H)=FFH
VPP = 5V
AT89C51
xxxx-5
yyww
(030H)=1EH
(031H)=51H
(032H)=05H
The AT89C51 code memory array is programmed byte-by-
byte in either programming mode. To program any non-
blank byte in the on-chip Flash Memory, the entire memory
must be erased using the Chip Erase Mode.
Programming Algorithm: Before programming the
AT89C51, the address, data and control signals should be
set up according to the Flash programming mode table and
Figures 3 and 4. To program the AT89C51, take the follow-
ing steps.
1.
Input the desired memory location on the address
lines.
2.
Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming
mode.
5. Pulse ALE/PROG once to program a byte in the Flash
array or the lock bits. The byte-write cycle is self-timed
and typically takes no more than 1.5 ms. Repeat steps
1 through 5, changing the address and data for the
entire array or until the end of the object file is reached.
Data Polling: The AT89C51 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an
attempted read of the last byte written will result in the com-
plement of the written datum on PO.7. Once the write cycle
has been completed, true data are valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can also
be monitored by the RDY/BSY output signal. P3.4 is pulled
low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is
done to indicate READY.
4-33
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read back
via the address and data lines for verification. The lock bits
cannot be verified directly. Verification of the lock bits is
achieved by observing that their features are enabled.
Chip Erase: The entire Flash array is erased electrically
by using the proper combination of control signals and by
holding ALE/PROG low for 10 ms. The code array is written
with all “1”s. The chip erase operation must be executed
before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are
read by the same procedure as a normal verification of
locations 030H,
031H, and 032H, except that P3.6 and P3.7 must be pulled
to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming
Programming Interface
Every code byte in the Flash array can be written and the
entire array can be erased by using the appropriate combi-
nation of control signals. The write operation cycle is self-
timed and once initiated, will automatically time itself to
completion.
All major programming vendors offer worldwide support for
the Atmel microcontroller series. Please contact your local
programming vendor for the appropriate software revision.
Flash Programming Modes
RST
PSEN
ALE/PROG
H
EA/VPP
H/12V
H
H/12V
H/12V
H/12V
P2.6
P2.7
P3.6
P3.7
L
L
H
H
H
H
L
H
L
H
H
L
L
L
H
H
H
L
H
L
L
H
H
H
L
L
L
L
(1)
H/12V
H
H
Mode
Write Code Data
Read Code Data
Write Lock
Bit - 1
Bit - 2
Bit - 3
Chip Erase
Read Signature Byte
H
H
H
H
H
H
H
L
L
L
L
L
L
L
Note:
1. Chip Erase requires a 10-ms PROG pulse.
4-34
AT89C51
Figure 3. Programming the Flash
Figure 4. Verifying the Flash
AT89C51
A0 - A7
ADDR.
OOOOH/OFFFH
A8 - A11
SEE FLASH
PROGRAMMING
MODES ABLE
T
AT89C51
P1
VCC
P2.0 - P2.3
P0
+5V
PGM
DATA
P2.6
P2.7
P3.6
P3.7
ALE
PROG
A0 - A7
ADDR.
OOOOH/0FFFH
A8 - A11
SEE FLASH
PROGRAMMING
MODES ABLE
T
VCC
P0
ALE
AT89C51
P1
P2.0 - P2.3
P2.6
P2.7
P3.6
P3.7
XTAL2
EA
V /VIH PP
XTAL2
EA
3-24 MHz
3-24 MHz
XTAL1
GND
RST
PSEN
VIH
XTAL1
GND
RST
PSEN
+5V
PGM DATA
(USE 10K
PULLUPS)
VIH
VIH
Flash Programming and Verification Characteristics
TA = 0°C to 70°C, VCC = 5.0 – 10%
Symbol
Parameter
Min
(1)
VPP
(1)
IPP
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tAVQV
tELQV
tEHQZ
tGHBL
tWC
Note:
(1)
Programming Enable Voltage
Programming Enable Current
Oscillator Frequency
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2.7 (ENABLE) High to VPP
VPP Setup to PROG Low
VPP Hold After PROG
PROG Width
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to BUSY Low
Byte Write Cycle Time
11.5
3
48tCLCL
48tCLCL
48tCLCL
48tCLCL
48tCLCL
10
10
1
0
1. Only used in 12-volt programming mode.
Max
12.5
1.0
24
Units
V
mA
MHz
110
48tCLCL
48tCLCL
48tCLCL
1.0
2.0
m s
m s
m s
m s
ms
4-35
Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)
P1.0 - P1.7
P2.0 - P2.3
PORT 0
ALE/PROG
EA/VPP
P2.7
(ENABLE)
P3.4
(RDY/BSY)
tAVGL
tSHGL
PROGRAMMING
ADDRESS
DATA IN
tDVGL
tGHDX
VPP
tEHSH
tGLGH
tGHBL
VERIFICATION
ADDRESS
tAVQV
DATA OUT
tGHAX
tGHSL
LOGIC 1
LOGIC 0
tELQV
BUSY
tWC
READY
tEHQZ
Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)
P1.0 - P1.7
P2.0 - P2.3
PORT 0
ALE/PROG
EA/VPP
P2.7
(ENABLE)
P3.4
(RDY/BSY)
VERIFICATION
ADDRESS
tAVQV
DATA OUT
tAVGL
tSHGL
PROGRAMMING
ADDRESS
DATA IN
tDVGL
tGHDX
tGLGH
tGHBL
tEHSH
tGHAX
LOGIC 1
LOGIC 0
tELQV
BUSY
tWC
READY
tEHQZ
4-36
AT89C51
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
