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DATASHEET_FT2201_v1.4_for _20181112(1).pdf
FT2201
Table of Contents
1. GENERAL DESCRIPTION
2. FEATURES
3. BLOCK DIAGRAM
3.1. Block Function
3.1.1. System interface
3.1.2. Grayscale voltage generating circuit
3.1.3. Timing controller
3.1.4. Oscillator (OSC)
3.1.5. Source driver circuit
3.1.6. Gate driver circuit
3.1.7. LCD driving power supply circuit
4. PIN DESCRIPTIONS
4.1. Pin Definition
4.2. Power Supply Configuration (VDDI / VDD)
4.3. Application Circuit & BOM List
5. INSTRUCTIONS
5.1. Outline
5.1.1. System function command list and description
5.2. SYSTEM COMMAND DESCRIPTION
5.2.1. NOP (00h) : No Operation
5.2.2. SWRESET (01h): Software Reset
5.2.3. RDDID (04H): Read ID1~ID3
5.2.4. RDNUMED (05H) Read Number of the Errors on DSI
5.2.5. RDDPM (0AH): Read Display Power Mode
5.2.6. RDDMADCTR (0BH): Read Display MADCTR
5.2.7. RDDCOLMOD (0CH): Read Display Pixel Format
5.2.8. RDDIM (0DH): Read Display Image Mode
5.2.9. RDDSM (0EH): Read Display Signal Mode
5.2.10. RDDSDR (0FH): Read Display Self-Diagnostic Result
5.2.11. SLPIN (10H): Sleep In
5.2.12. SLPOUT (11H): Sleep Out
5.2.13. PTLON (12H): Partial Display Mode On
5.2.14. NORON (13H): Normal Display Mode On
5.2.15. INVOFF (20h) : Display Inversion Off
5.2.16. INVON (21h) : Display Inversion On
5.2.17. ALLPOFF (22H): All Pixels Off
5.2.18. ALLPON (23H): All Pixels On
5.2.19. DISPOFF (28H): Display Off
5.2.20. DISPON (29H): Display On
5.2.21. CASET (2AH): Column Address Set
5.2.22. PASET (2BH): Page Address Set
5.2.23. RAMWR (2CH): Memory Write
5.2.24. RAMRD (2EH): Memory Read
5.2.25. PTLAR (30H): Partial Area
5.2.26. VPTLAR (31H): Vertical Partial Area
5.2.27. TEOFF (34H): Tearing Effect Line OFF
5.2.28. TEON (35H): Tearing Effect Line ON
5.2.29. MADCTR (36H): Memory Data Access Control
5.2.30. IDMOFF (38H): Idle Mode Off
5.2.31. IDMON (39H): Idle Mode On
5.2.32. COLMOD (3AH): Interface Pixel Format
5.2.33. RAMWRCNT (3CH): Memory Write Continue
5.2.34. RAMRDCNT (3EH): Memory Read Continue
5.2.35. WRTESCN (44H): Write TE Scan Line
5.2.36. RDSCNL (45H): Read Scan Line
5.2.37. DSTBON (4FH): Deep Standby Mode On
5.2.38. WRSTEW (50H) Write STE Width
5.2.39. WRDBVC (51H) Write Display Brightness Value Control
5.2.40. RDDBVC (52H) Read Display Brightness Value Control
5.2.41. WRACL (55H) Write Auto Current Limitation
5.2.42. RDACL (56H) Read Auto Current Limitation
5.2.43. RDSTEW (60H) Read STE Width
5.2.44. FCC_WRSRE (92H) Focal CleverColor - Write SRE
5.2.45. FCC_RDSRE (93H) Focal CleverColor - Read SRE
5.2.46. RDDDBSTR (A1H): Read DDB Start
5.2.47. RDDDBCNT (A8H): Read DDB Continue
5.2.48. RDFCRC (AAH): Read First CRC
5.2.49. RDCCRC (AFH): Read Continue CRC
5.2.50. RDID1 (DAH): Read ID1
5.2.51. RDID2 (DBH): Read ID2
5.2.52. RDID3 (DCH): Read ID3
6. FUNCTIONS
6.1. Interface Type Selection
6.2. MIPI-DSI Interface
6.2.1. General description
6.2.2. Interface level communication
6.2.2.1. General
6.2.2.2. DSI-CLK lanes
6.2.3. DSI data lanes
6.2.3.1. General
6.2.3.2. Escape modes
6.2.3.3. High-Speed Data Transmission (HSDT)
6.2.3.4. Bus Turnaround (BTA)
6.2.3.5. Two Data-lane High Speed Transmission
6.2.3.6. Three data-lane high speed transmission
6.2.4. Packet level communication
6.2.4.1. Short Packet (SPa) and Long Packet (LPa) structures
6.2.4.2. Packet transmissions
6.2.5. Customer-defined generic read data type format
6.3. Parallel 8-bit MCU Interface
6.3.1. Parallel Read Command Transmission
6.3.2. Parallel Write Command Transmission
6.3.3. MCU Color Mode
6.3.4. Interface Pause and Recovery
6.3.5. Display Module Data Transfer
6.3.5.1. Method 1
6.3.5.2. Method 2
6.4. Serial Peripheral Interface (SPI)
6.4.1. Serial Write Transmission
6.4.1.1. Type1 Write Transmission (SPI3 single data wire with 9-bit packet)
6.4.1.2. Type2 Write Transmission (SPI4 single data wire with 8-bit packet)
6.4.1.3. Type3 Write Transmission (SPI16 single data wire with 16-bit packet)
6.4.1.4. Type4 Write Transmission (SPI3 dual data wire with 9-bit command packet)
6.4.1.5. Type5 Write Transmission (SPI4 dual data wire with 8-bit command packet)
6.4.2. Serial Read Command Transmission
6.4.2.1. Type1 Read Transmission
6.4.2.2. Type2 Read Transmission
6.4.2.3. Type3 Read Transmission
6.4.2.4. Type4 Read Transmission
6.4.2.5. Type5 Read Transmission
6.5. BIST Function
6.5.1. General Description
6.5.2. BIST Command Set
6.5.3. Free Run Function Description
6.5.4. Single Mode Function Description
6.5.5. BIST Mode Pattern
6.6. Power On/Off Sequence
6.6.1. Case 1 – RESX line is held high or unstable by host at power on
6.6.2. Case 2 – RESX line is held low or unstable by host at power on
6.6.3. Uncontrolled power off
6.6.4. Power on/off sequence and OTP program for MIPI, GOA, SOURCE, Swire interface
6.6.5. Normal power on/off sequence
6.6.6. Abnormal power off sequence
6.7. Power Level Definition
6.8. Tear Effect Information
6.8.1. General
6.8.1.1. Tearing effect line models
6.8.1.2. Tearing effect line timing
6.8.1.3. Example 1 MCU write is faster then panel read
6.8.1.4. Example 1 MCU write is slower then panel read
6.8.2. Tearing effect bus trigger
6.8.2.1. Tearing effect bus trigger enable
6.8.2.2. Tearing effect bus trigger disable
6.8.2.3. Tearing effect bus trigger sequencesTearing effect bus trigger enable sequence – DCSW-L and HSDT
6.8.2.4. Tearing effect bus trigger enable sequence – DCSW-L and LPDT
6.8.2.5. Tearing effect bus trigger enable sequence – DCSW1-S and HPDT
6.8.2.6. Tearing effect bus trigger enable sequence – DCSW1-S and LPDT
6.8.2.7. Tearing effect bus trigger enable sequence – DCSWN-S and HPDT
6.8.2.8. Tearing effect bus trigger enable sequence – DCSWN-S and LPDT
6.9. CRC (Cyclic Redundancy Check)
6.10. Sun Light Readable ( SRE )
6.11. OTP Programming Procedure
6.11.1. Internal Programming Mode
6.11.1.1. Programming flow chart
6.11.1.2. Programming Sequence
6.11.2. External Programming Mode
6.11.2.1. Programming flow chart
6.11.2.2. Programming Sequence
7. ELECTRICAL SPECIFICATION
7.1. Absolute Maximum Ratings
7.2. DC characteristic
7.2.1. Basic DC characteristic
7.2.2. MIPI DC character
7.3. AC characteristic
7.3.1. Reset timing characteristics
7.3.2. Parallel interface characteristics 8-bits bus (8080-series MCU)
7.3.3. Serial interface characteristics (SPI)
7.3.4. MIPI-DSI characteristics
7.3.4.1. High speed mode
7.3.4.2. Low power mode
7.3.4.3. Bursts
7.3.4.4. LP-11 between High Speed and Low Power Modes
8. CHIP INFORMATION
8.1. PAD Assignment
8.2. PAD Dimension
8.3. PAD Location
8.4. Alignment Mark
9. DISCLAIMER
10. REVISION HISTORY
FT2201
121-channel 8-bit Source Driver with
System-on-chip for LTPS AMOLED
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Preliminary
Apr. 5, 2017
Version 1.4
..
FocalTech Systems reserves the right to change this documentation without prior notice. Information provided by FocalTech Systems is believed to be accurate
and reliable. However, FocalTech Systems makes no warranty for any errors which may appear in this document. Contact FocalTech Systems to obtain the latest
version of device specifications before placing your order. No responsibility is assumed by FocalTech Systems for any infringement of patent or other rights of
third parties which may result from its use. In addition, FocalTech Systems products are not authorized for use as critical components in life support devices/
systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without
the express written approval of FocalTech Systems.
FocalTech Confidential For 日欣 Use Only
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Preliminary
FT2201
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Table of Contents
1. GENERAL DESCRIPTION .............................................................................................................................. 1
2. FEATURES ............................................................................................................................................... 2
3. BLOCK DIAGRAM ....................................................................................................................................... 5
3.1. Block Function ................................................................................................................................. 5
3.1.1. System interface ..................................................................................................................... 5
3.1.2. Grayscale voltage generating circuit .............................................................................................. 6
3.1.3. Timing controller ..................................................................................................................... 6
3.1.4. Oscillator (OSC) ..................................................................................................................... 6
3.1.5. Source driver circuit ................................................................................................................. 6
3.1.6. Gate driver circuit .................................................................................................................... 6
3.1.7. LCD driving power supply circuit .................................................................................................. 6
4. PIN DESCRIPTIONS .................................................................................................................................... 7
4.1. Pin Definition ................................................................................................................................... 7
4.2. Power Supply Configuration (VDDI / VDD) ............................................................................................... 11
4.3. Application Circuit & BOM List ............................................................................................................. 12
5. INSTRUCTIONS ........................................................................................................................................ 14
5.1. Outline ......................................................................................................................................... 14
5.1.1. System function command list and description ................................................................................ 14
5.2. SYSTEM COMMAND DESCRIPTION ..................................................................................................... 17
5.2.1. NOP (00h) : No Operation ........................................................................................................ 17
5.2.2. SWRESET (01h): Software Reset ............................................................................................... 18
5.2.3. RDDID (04H): Read ID1~ID3 ..................................................................................................... 19
5.2.4. RDNUMED (05H) Read Number of the Errors on DSI ........................................................................ 20
5.2.5. RDDPM (0AH): Read Display Power Mode .................................................................................... 21
5.2.6. RDDMADCTR (0BH): Read Display MADCTR ................................................................................ 22
5.2.7. RDDCOLMOD (0CH): Read Display Pixel Format ............................................................................ 23
5.2.8. RDDIM (0DH): Read Display Image Mode ..................................................................................... 24
5.2.9. RDDSM (0EH): Read Display Signal Mode .................................................................................... 25
5.2.10. RDDSDR (0FH): Read Display Self-Diagnostic Result ...................................................................... 26
5.2.11. SLPIN (10H): Sleep In ........................................................................................................... 27
5.2.12. SLPOUT (11H): Sleep Out ...................................................................................................... 28
5.2.13. PTLON (12H): Partial Display Mode On ....................................................................................... 29
5.2.14. NORON (13H): Normal Display Mode On .................................................................................... 30
5.2.15. INVOFF (20h) : Display Inversion Off .......................................................................................... 31
5.2.16. INVON (21h) : Display Inversion On ........................................................................................... 32
5.2.17. ALLPOFF (22H): All Pixels Off ................................................................................................. 33
5.2.18. ALLPON (23H): All Pixels On ................................................................................................... 34
5.2.19. DISPOFF (28H): Display Off .................................................................................................... 35
5.2.20. DISPON (29H): Display On ..................................................................................................... 36
5.2.21. CASET (2AH): Column Address Set ........................................................................................... 37
5.2.22. PASET (2BH): Page Address Set .............................................................................................. 38
5.2.23. RAMWR (2CH): Memory Write ................................................................................................. 39
5.2.24. RAMRD (2EH): Memory Read .................................................................................................. 40
5.2.25. PTLAR (30H): Partial Area ...................................................................................................... 41
5.2.26. VPTLAR (31H): Vertical Partial Area ........................................................................................... 43
5.2.27. TEOFF (34H): Tearing Effect Line OFF ....................................................................................... 44
5.2.28. TEON (35H): Tearing Effect Line ON .......................................................................................... 45
5.2.29. MADCTR (36H): Memory Data Access Control .............................................................................. 46
5.2.30. IDMOFF (38H): Idle Mode Off .................................................................................................. 48
5.2.31. IDMON (39H): Idle Mode On ................................................................................................... 49
5.2.32. COLMOD (3AH): Interface Pixel Format ...................................................................................... 50
5.2.33. RAMWRCNT (3CH): Memory Write Continue ................................................................................ 51
5.2.34. RAMRDCNT (3EH): Memory Read Continue ................................................................................. 52
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5.2.35. WRTESCN (44H): Write TE Scan Line ........................................................................................ 53
5.2.36. RDSCNL (45H): Read Scan Line .............................................................................................. 54
5.2.37. DSTBON (4FH): Deep Standby Mode On .................................................................................... 55
5.2.38. WRSTEW (50H) Write STE Width ............................................................................................. 56
5.2.39. WRDBVC (51H) Write Display Brightness Value Control .................................................................... 57
5.2.40. RDDBVC (52H) Read Display Brightness Value Control .................................................................... 59
5.2.41. WRACL (55H) Write Auto Current Limitation ................................................................................. 61
5.2.42. RDACL (56H) Read Auto Current Limitation .................................................................................. 62
5.2.43. RDSTEW (60H) Read STE Width .............................................................................................. 63
5.2.44. FCC_WRSRE (92H) Focal CleverColor - Write SRE ........................................................................ 64
5.2.45. FCC_RDSRE (93H) Focal CleverColor - Read SRE ........................................................................ 65
5.2.46. RDDDBSTR (A1H): Read DDB Start .......................................................................................... 66
5.2.47. RDDDBCNT (A8H): Read DDB Continue ..................................................................................... 67
5.2.48. RDFCRC (AAH): Read First CRC .............................................................................................. 68
5.2.49. RDCCRC (AFH): Read Continue CRC ........................................................................................ 69
5.2.50. RDID1 (DAH): Read ID1 ........................................................................................................ 70
5.2.51. RDID2 (DBH): Read ID2 ........................................................................................................ 71
5.2.52. RDID3 (DCH): Read ID3 ........................................................................................................ 72
6. FUNCTIONS ............................................................................................................................................ 73
6.1. Interface Type Selection ..................................................................................................................... 73
6.2. MIPI-DSI Interface ............................................................................................................................ 74
6.2.1. General description ................................................................................................................ 74
6.2.2. Interface level communication .................................................................................................... 74
6.2.3. DSI data lanes ..................................................................................................................... 80
6.2.4. Packet level communication ...................................................................................................... 91
6.2.5. Customer-defined generic read data type format ............................................................................ 103
6.3. Parallel 8-bit MCU Interface ............................................................................................................... 104
6.3.1. Parallel Read Command Transmission ........................................................................................ 104
6.3.2. Parallel Write Command Transmission ........................................................................................ 105
6.3.3. MCU Color Mode ................................................................................................................. 105
6.3.4. Interface Pause and Recovery .................................................................................................. 107
6.3.5. Display Module Data Transfer .................................................................................................. 109
6.4. Serial Peripheral Interface (SPI) .......................................................................................................... 110
6.4.1. Serial Write Transmission ....................................................................................................... 110
6.4.2. Serial Read Command Transmission .......................................................................................... 119
6.5. BIST Function ............................................................................................................................... 124
6.5.1. General Description .............................................................................................................. 124
6.5.2. BIST Command Set .............................................................................................................. 124
6.5.3. Free Run Function Description ................................................................................................. 125
6.5.4. Single Mode Function Description .............................................................................................. 125
6.5.5. BIST Mode Pattern ............................................................................................................... 126
6.6. Power On/Off Sequence ................................................................................................................... 128
6.6.1. Case 1 – RESX line is held high or unstable by host at power on ......................................................... 128
6.6.2. Case 2 – RESX line is held low or unstable by host at power on .......................................................... 129
6.6.3. Uncontrolled power off ........................................................................................................... 129
6.6.4. Power on/off sequence and OTP program for MIPI, GOA, SOURCE, Swire interface ................................... 130
6.6.5. Normal power on/off sequence ................................................................................................. 132
6.6.6. Abnormal power off sequence .................................................................................................. 133
6.7. Power Level Definition ..................................................................................................................... 134
6.8. Tear Effect Information ..................................................................................................................... 135
6.8.1. General ............................................................................................................................. 135
6.8.2. Tearing effect bus trigger ........................................................................................................ 139
6.9. CRC (Cyclic Redundancy Check) ........................................................................................................ 147
6.10. Sun Light Readable ( SRE ) ............................................................................................................. 148
6.11. OTP Programming Procedure ........................................................................................................... 150
6.11.1. Internal Programming Mode ................................................................................................... 150
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6.11.2. External Programming Mode .................................................................................................. 151
7. ELECTRICAL SPECIFICATION ..................................................................................................................... 152
7.1. Absolute Maximum Ratings ............................................................................................................... 152
7.2. DC characteristic ............................................................................................................................ 153
7.2.1. Basic DC characteristic .......................................................................................................... 153
7.2.2. MIPI DC character ................................................................................................................ 155
7.3. AC characteristic ............................................................................................................................ 157
7.3.1. Reset timing characteristics ..................................................................................................... 157
7.3.2. Parallel interface characteristics 8-bits bus (8080-series MCU) ............................................................ 158
7.3.3. Serial interface characteristics (SPI) ........................................................................................... 160
7.3.4. MIPI-DSI characteristics ......................................................................................................... 161
8. CHIP INFORMATION ................................................................................................................................. 166
8.1. PAD Assignment ............................................................................................................................ 166
8.2. PAD Dimension ............................................................................................................................. 167
8.3. PAD Location ................................................................................................................................ 168
8.4. Alignment Mark ............................................................................................................................. 173
9. DISCLAIMER .......................................................................................................................................... 174
10. REVISION HISTORY ................................................................................................................................ 175
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1. GENERAL DESCRIPTION
The FT2201 is a single-chip solution for LTPS AMOLED that incorporates gate drivers and display RAM. It’s capable of supporting up
to 240RGBx240, 240RGBx204, 214RGBx128, 180RGBx120, 176RGBx176, 160RGBx128, 144RGBx256, 128RGBx432, 128RGBx160,
128RGBx128, 128RGBx86, 128RGBx64, 96RGBx240, 96RGBx96, 96RGBx 64 and 64RGBx160 in resolution.
The FT2201 is able to operate with low IO interface power supply and incorporate with several charge pumps to generate various voltage
levels that form an on-chip power management system for gate driver and source driver.
The FT2201 can support MIPI interface, 8-bit system interfaces, serial peripheral interfaces (SPI), dual peripheral interfaces to update display
image and configure system. It supports a function to display eight colors and a standby mode for power control consideration. For further
power control, the auto current limitation (ACL) function based on image content and a deep standby mode are also supported.
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2. FEATURES
– Single-chip PMOS LTPS DDIC with Full RAM
– Display Resolution
• 240RGB x 240
• 240RGB x 204
• 214RGB x 128
• 180RGB x 120
• 176RGB x 176
• 160RGB x 128
• 144RGB x 256
• 128RGB x 432
• 128RGB x 160
• 128RGB x 128
• 128RGB x 86
• 128RGB x 64
• 96RGB x 240
• 96RGB x 96
• 96RGB x 64
• 64RGB x 160
– Source Channel Option
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– Display Data Memory: 1,382,400 bits (240 x 240 x 24-bit)
– Display mode
• Full color mode : 16.7Mcolors (RGB888l)
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• Reduced color mode: 252Kcolors (RGB666)
• Reduced color mode: 65Kcolors (RGB565)
• Idle mode: 16.7M / 4096 / 8colors
– System Interfaces
• 8-bit 80 series MPU interface
• Serial peripheral interface (SPI)
• Dual serial peripheral interface (Dual-SPI)
• MIPI Display Serial Interface 1 data lane (D-PHY v1.0, DSI v1.02, and DCS v1.02)
– Display Features
• Support RGB separated gamma setting
• Support programmable Y-correction function
• Support partial display function
• Support Sunligh Readable (SRE) function
– Power Saving Mode
• Auto Current Limitation (ACL)
• Brightness Control (BC)
• Deep Standby Function
– On Chip Function
• Built-in internal oscillator for display clock
• Built-in OTP function to adjust panel setting / command default
• Built-in OTP programming power
• Built-in Charge Pump for VGHR/VGLR
• Built-in BVP3D/BVN3D voltage generator for panel voltage
• Built-in VREFP5/VREFN5 voltage generator for panel voltage
• Support 121ch source output (MUX 1-6)
• Support 10ch gate control output (L/R) and 6ch source MUX control output (L/R)
• Support programmable GOA timing
• Support S-wire interface for power IC control
– Power Supply Range
• I/O and logic power supply voltage (VDDI): 1.65V ~ 3.60V
• Analog power supply voltage (VCI): 2.70V ~ 3.60V
– Output Voltage Range
• Positive gate driver voltage range for VGHR: 4.50V ~ 12.5V
• Negitive gate driver voltage range for VGLR: -4.50V ~ -11.0V
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• BVP3D panel voltage range: 1.90V ~ 5.00V
• BVN3D panel voltage range: -0.40V ~ -4.50V
• VREFP5 panel voltage range: 0.50V ~ 5.00V
• VREFN5 panel voltage range: -0.50V ~ -4.50V
• AVDD, Step-up 1 output voltage : 4.50V ~ 6.50V (VCIx1, VCIx2)
• VCL, Step-up 2 output voltage: -4.50 ~ -5.00V (VCIx-1, AVDDx-1)
• Gamma highest voltage range: 2.00V ~ 6.30V
• Gamma lowest voltage range: 0.20V ~ 4.50V
– Package: COF/COG
– Chip size: 8300um x 1290um (with scribe line)
– Power Supply Specification
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No.
Item
1
2
3
Source Driver
Gate control timing Level shift
Input Voltage
VDDI
VCC
VCI
4
OLED drive voltages
(VDDA/VDDB/VDDR)
AVDD
VCL
VGHR
VGLR
VREFP5
VREFN5
BVP3D
BVN3D
AVDD
VCL
VGMP
VGSP
5
6
Internal step-up circuits
Gamma reference
Description
121 pins (240 x RGB)
VGHR-VGLR
1.65V ~ 3.6V
Connect to VDDI or VCI
2.7V ~ 3.6V
4.5V ~ 6.5V
-4.5V ~ -5V
4.5V ~ 12.5V
-4.5V ~ -11V
0.5V ~ 5V
-0.5V ~ -4.5V
1.9V ~ 5V
0V, -0.4V ~ -4.5V, -5V
VCI, VCI x 2
VCI x -1, AVDD x -1
2V ~ 6.3V
0.2V ~ 4.5V
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