Micron 3D TLC datasheet.pdf

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NAND Flash Memory - Fortis Flash

Features

Part Numbering Information

General Description

Asynchronous, NV-DDR, NV-DDR2, NV-DDR3 Signal Descriptions

Signal Assignments

Package Dimensions

Architecture

Device and Array Organization

Bus Operation – Asynchronous Interface

Asynchronous Enable/Standby

Asynchronous Bus Idle

Asynchronous Pausing Data Input/Output

Asynchronous Commands

Asynchronous Addresses

Asynchronous Data Input

Asynchronous Data Output

Write Protect

Ready/Busy#

Bus Operation – NV-DDR Interface

NV-DDR Enable/Standby

NV-DDR Bus Idle/Driving

NV-DDR Pausing Data Input/Output

NV-DDR Commands

NV-DDR Addresses

NV-DDR DDR Data Input

NV-DDR Data Output

Write Protect

Ready/Busy#

Bus Operation – NV-DDR2 Interface

Differential Signaling

Warmup Cycles

On-die Termination (ODT)

Self-termination On-die Termination (ODT)

Matrix Termination

Matrix Termination Examples

NV-DDR2 Standby

NV-DDR2 Idle

NV-DDR2 Pausing Data Input/Output

NV-DDR2 Commands

NV-DDR2 Addresses

NV-DDR2 Data Input

NV-DDR2 Data Output

Write Protect

Ready/Busy#

Bus Operation – NV-DDR3 Interface

On-die Termination (ODT)

Device Initialization

VPP Initialization

Electronic Mirroring

Activating Interfaces

Activating the Asynchronous Interface

Activating the NV-DDR Interface

Activating the NV-DDR2 Interface

Activating the NV-DDR3 Interface

CE# Pin Reduction and Volume Addressing

Initialization Sequence

Volume Appointment Without CE# Pin Reduction

Appointing Volume Addresses

Selecting a Volume

Multiple Volume Operation Restrictions

Volume Reversion

Command Definitions

Reset Operations

RESET (FFh)

SYNCHRONOUS RESET (FCh)

RESET LUN (FAh)

HARD RESET (FDh)

Identification Operations

READ ID (90h)

READ ID Parameter Tables

READ PARAMETER PAGE (ECh)

Parameter Page Data Structure Tables

READ UNIQUE ID (EDh)

Configuration Operations

SET FEATURES (EFh)

GET FEATURES (EEh)

GET/SET FEATURES by LUN (D4h/D5h)

VOLUME SELECT (E1h)

ODT CONFIGURE (E2h)

ZQ Calibration

ZQ Calibration Long (F9h)

ZQ Calibration Short (D9h)

ZQ external resistor value, tolerance, and capacitive loading

Status Operations

READ STATUS (70h)

READ STATUS ENHANCED (78h)

FIXED ADDRESS READ STATUS ENHANCED (71h)

Column Address Operations

CHANGE READ COLUMN (05h-E0h)

CHANGE READ COLUMN ENHANCED (06h-E0h)

CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation

CHANGE WRITE COLUMN (85h)

CHANGE ROW ADDRESS (85h)

Read Operations

READ MODE (00h)

READ PAGE (00h-30h)

READ PAGE CACHE SEQUENTIAL (31h)

READ PAGE CACHE RANDOM (00h-31h)

READ PAGE CACHE LAST (3Fh)

READ PAGE MULTI-PLANE (00h-32h)

Read Retry Operations

Auto Read Calibration

Two Pass Programming

PROGRAM PAGE (80h-10h)

PROGRAM PAGE CACHE (80h-15h)

PROGRAM PAGE MULTI-PLANE (80h-11h)

PROGRAM SUSPEND (84h) and PROGRAM RESUME (13h)

Program Continuation

SLC Operations

Erase Operations

ERASE BLOCK (60h-D0h)

ERASE BLOCK MULTI-PLANE (60h-D1h)

ERASE BLOCK MULTI-PLANE (60h-60h-D0h)

ERASE SUSPEND (61h) and ERASE RESUME (D2h)

Copyback Operations

COPYBACK READ (00h-35h)

COPYBACK PROGRAM (85h–10h)

COPYBACK READ MULTI-PLANE (00h-32h)

COPYBACK PROGRAM MULTI-PLANE (85h-11h)

One-Time Programmable (OTP) Operations

PROGRAM OTP PAGE (80h-10h)

PROTECT OTP AREA (80h-10h)

READ OTP PAGE (00h-30h)

Multi-Plane Operations

Multi-Plane Addressing

Interleaved Die (Multi-LUN) Operations

Error Management

Shared Pages - TLC

Output Drive Impedance

AC Overshoot/Undershoot Specifications

Input Slew Rate

Output Slew Rate

Power Cycle and Ramp Requirements

Electrical Specifications

Package Electrical Specification and Pad Capacitance

Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous)

Electrical Specifications – DC Characteristics and Operating Conditions (NV-DDR, NV-DDR2, NV-DDR3)

Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ)

Single-Ended Requirements for Differential signals

Testing Conditions

Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous)

Electrical Specifications – AC Characteristics and Operating Conditions (NV-DDR, NV-DDR2, NV-DDR3)

Electrical Specifications – Array Characteristics

Asynchronous Interface Timing Diagrams

NV-DDR Interface Timing Diagrams

NV-DDR2 and NV-DDR3 Interface Timing Diagrams

Revision History

Rev. E – 7/1/16

Rev. D – 06/04/16

Rev. C – 5/13/16

Rev. B – 11/25/15

Rev. A – 08/05/15

Micron Confidential and Proprietary Advance‡ TLC 384Gb to 6Tb Async/Sync NAND Features NAND Flash Memory - Fortis Flash MT29F384G08EBHBB, MT29F768G08EEHBB MT29F1T208ECHBB, MT29F1HT08EMHBB MT29F3T08EUHBB, MT29F6T08ETHBB Features • Open NAND Flash Interface (ONFI) 4.0-compliant1 • JEDEC NAND Flash Interoperability (JESD230B) compliant2 • Triple-level cell (TLC) • Organization – Page size x8: 18,592 bytes (16,384 + 2208 bytes) – Block size: 1536 pages, (24,576K + 3312K bytes) – Plane size: 4 planes x 548 blocks per plane – Device size: 384Gb: 2192 blocks; 768Gb: 4384 blocks; 1T2: 6576 blocks; 1H2: 8768 blocks; 3Tb: 17,536 blocks; 6Tb: 35,072 blocks • NV-DDR3 I/O performance4 – Up to NV-DDR3 timing mode 9 – Clock rate: 3ns (NV-DDR3) – Read/write throughput per pin: 667 MT/s • NV-DDR2 I/O performance4 – Up to NV-DDR2 timing mode 8 – Clock rate: 3.75ns (NV-DDR2) – Read/write throughput per pin: 533 MT/s • NV-DDR I/O performance 4 – Up to NV-DDR timing mode 5 – Clock rate: 10ns (NV-DDR) – Read/write throughput per pin: 200 MT/s • Asynchronous I/O performance 4 – Up to asynchronous timing mode 5 – tRC/tWC: 20ns (MIN) – Read/write throughput per pin: 50 MT/s • Array performance – SNAP READ operation time: 58µs (TYP) 5 – Single-Plane READ PAGE without/with VPP: 92/90µs (TYP)5 – Effective Program page without/with VPP: 2100/2000µs (TYP) – Erase block: 15ms (TYP) • Operating Voltage Range – VCC: 2.7–3.6V – VCCQ: 1.7–1.95V; 1.14–1.26V • Command set: ONFI NAND Flash Protocol • Advanced Command Set – Program cache – Read cache sequential – Read cache random – One-time programmable (OTP) mode – Multi-plane commands – Multi-LUN operations – Read Unique ID – Copyback – SLC Mode – Read Retry6 – ZQ Calibration 6 1 / 1 / 7 : e s a e l e R • First block (block address 00h) is valid when ship- ped from factory. For minimum required ECC, see Error Management (page 206).6 • RESET (FFh) required as first command after pow- er-on • Operation status byte provides software method for detecting – Operation completion – Pass/fail condition – Write-protect status • Data strobe (DQS) signals provide a hardware meth- od for synchronizing data DQ in the NV-DDR/NV- DDR2/NV-DDR3 interface • Copyback operations supported within the plane from which data is read • On-die Termination (ODT) 3 • Quality and reliability6 – Testing methodology: JESD47 – Data retention: See qualification report - May vary for targeted application – TLC Endurance: 1500 PROGRAM/ERASE cycles 7 – SLC Endurance: 30,000 PROGRAM/ERASE cycles • Operating temperature: – Commercial: 0°C to +70°C • Package – 132-ball BGA Notes: 1. The ONFI 4.0 specification is available at www.onfi.org. 2. The JEDEC specification is available at www.jedec.org/standards-documents. 3. ODT functionality is supported only in NV- DDR2 or NV-DDR3. PDF: 09005aef86697e57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN ‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. 1

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features 4. Asynchronous, NV-DDR, and NV-DDR2 func- tionality is only available within the 1.8V VCCQ supply range. NV-DDR3 functionality is only available within the 1.2V VCCQ supply range. 5. Regarding to Randomization default set- ting and the enabling/disabling method, contact factory for technical details. Array Read times listed are without internal ran- domization. 6. Read Retry and Auto Read Calibration oper- ations are required to achieve specified en- durance and for general array data integri- ty. 7. For minimum required ECC, see Error Man- agement (page 206).6. Contact factory for endurance capability details using BCH ECC. 6 1 / 1 / 7 : e s a e l e R PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Numbering MT 29F 384G 08 E B H B B R ES :B Micron Technology NAND Flash 29F = NAND Flash memory Density 384G = 384Gb 768G = 768Gb 1T2 = 1.125Tb 1HT = 1.5Tb 3T = 3Tb 6T = 6Tb Device Width 08 = 8 bits Bit/Cell Level E 3-bit I/O Classification B E C M U T Die # of CE# # of R/B# 1 2 3 4 8 16 1 2 3 4 4 8 Common 1 2 Separate - 2 CH 3 Separate - 2 CH 4 Separate - 2 CH Separate - 2 CH 4 4 Separate - 2 CH Operating Voltage Range H = VCC: 3.3V (2.7–3.6V), V : 1.8V (1.7–1.95V) or 1.2V (1.14–1.26V) CCQ Note: 1. Pb-free package. Design Revision B = Second revision Production Status Blank = Production ES = Engineering sample Special Options R = Fortis Flash Operating Temperature Range Blank = Commercial (0°C to +70°C) Speed Grade (NV-DDR2/NV-DDR3 mode - BGA) -3 = 667 MT/s Package Code J4 = 132-ball VBGA 12mm x 18mm x 1.0mm1 M4 = 132-ball TBGA 12mm x 18mm x 1.3mm1 M5 = 132-ball LBGA 12mm x 18mm x 1.5mm1 Interface B = Async/NV-DDR/NV-DDR2 or NV-DDR3 Generation Feature Set B = 2nd set of device features 6 1 / 1 / 7 : e s a e l e R PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features Contents General Description ....................................................................................................................................... 15 Asynchronous, NV-DDR, NV-DDR2, NV-DDR3 Signal Descriptions .................................................................. 15 Signal Assignments ......................................................................................................................................... 17 Package Dimensions ....................................................................................................................................... 18 Architecture ................................................................................................................................................... 21 Device and Array Organization ........................................................................................................................ 22 Bus Operation – Asynchronous Interface ......................................................................................................... 30 Asynchronous Enable/Standby ................................................................................................................... 30 Asynchronous Bus Idle ............................................................................................................................... 30 Asynchronous Pausing Data Input/Output .................................................................................................. 31 Asynchronous Commands .......................................................................................................................... 31 Asynchronous Addresses ............................................................................................................................ 32 Asynchronous Data Input ........................................................................................................................... 33 Asynchronous Data Output ......................................................................................................................... 34 Write Protect .............................................................................................................................................. 35 Ready/Busy# .............................................................................................................................................. 35 Bus Operation – NV-DDR Interface ................................................................................................................. 38 NV-DDR Enable/Standby ............................................................................................................................ 39 NV-DDR Bus Idle/Driving ........................................................................................................................... 39 NV-DDR Pausing Data Input/Output .......................................................................................................... 40 NV-DDR Commands .................................................................................................................................. 40 NV-DDR Addresses ..................................................................................................................................... 41 NV-DDR DDR Data Input ........................................................................................................................... 42 NV-DDR Data Output ................................................................................................................................. 43 Write Protect .............................................................................................................................................. 45 Ready/Busy# .............................................................................................................................................. 45 Bus Operation – NV-DDR2 Interface ................................................................................................................ 45 Differential Signaling .................................................................................................................................. 47 Warmup Cycles .......................................................................................................................................... 47 On-die Termination (ODT) ......................................................................................................................... 48 Self-termination On-die Termination (ODT) ................................................................................................ 50 Matrix Termination .................................................................................................................................... 51 Matrix Termination Examples ..................................................................................................................... 54 NV-DDR2 Standby ...................................................................................................................................... 59 NV-DDR2 Idle ............................................................................................................................................ 60 NV-DDR2 Pausing Data Input/Output ......................................................................................................... 60 NV-DDR2 Commands ................................................................................................................................. 60 NV-DDR2 Addresses ................................................................................................................................... 61 NV-DDR2 Data Input .................................................................................................................................. 62 NV-DDR2 Data Output ............................................................................................................................... 63 Write Protect .............................................................................................................................................. 64 Ready/Busy# .............................................................................................................................................. 64 Bus Operation – NV-DDR3 Interface ................................................................................................................ 65 On-die Termination (ODT) ......................................................................................................................... 65 Device Initialization ....................................................................................................................................... 68 VPP Initialization ......................................................................................................................................... 70 Electronic Mirroring ....................................................................................................................................... 71 Activating Interfaces ....................................................................................................................................... 74 Activating the Asynchronous Interface ........................................................................................................ 74 Activating the NV-DDR Interface ................................................................................................................. 74 PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 6 1 / 1 / 7 : e s a e l e R

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features Activating the NV-DDR2 Interface ............................................................................................................... 74 Activating the NV-DDR3 Interface ............................................................................................................... 75 CE# Pin Reduction and Volume Addressing ..................................................................................................... 77 Initialization Sequence ............................................................................................................................... 79 Volume Appointment Without CE# Pin Reduction ....................................................................................... 80 Appointing Volume Addresses ..................................................................................................................... 81 Selecting a Volume ..................................................................................................................................... 81 Multiple Volume Operation Restrictions ...................................................................................................... 81 Volume Reversion ....................................................................................................................................... 82 Command Definitions .................................................................................................................................... 84 Reset Operations ............................................................................................................................................ 87 RESET (FFh) ............................................................................................................................................... 87 SYNCHRONOUS RESET (FCh) .................................................................................................................... 88 RESET LUN (FAh) ....................................................................................................................................... 89 HARD RESET (FDh) .................................................................................................................................... 90 Identification Operations ................................................................................................................................ 91 READ ID (90h) ............................................................................................................................................ 91 READ ID Parameter Tables .......................................................................................................................... 93 READ PARAMETER PAGE (ECh) .................................................................................................................. 94 Parameter Page Data Structure Tables ..................................................................................................... 96 READ UNIQUE ID (EDh) ........................................................................................................................... 111 Configuration Operations .............................................................................................................................. 112 SET FEATURES (EFh) ................................................................................................................................. 113 GET FEATURES (EEh) ................................................................................................................................ 114 GET/SET FEATURES by LUN (D4h/D5h) .................................................................................................... 114 VOLUME SELECT (E1h) ............................................................................................................................. 133 ODT CONFIGURE (E2h) ............................................................................................................................ 135 ZQ Calibration ........................................................................................................................................... 139 ZQ Calibration Long (F9h) ..................................................................................................................... 140 ZQ Calibration Short (D9h) .................................................................................................................... 141 ZQ external resistor value, tolerance, and capacitive loading ................................................................... 142 Status Operations .......................................................................................................................................... 144 READ STATUS (70h) .................................................................................................................................. 146 READ STATUS ENHANCED (78h) ............................................................................................................... 146 FIXED ADDRESS READ STATUS ENHANCED (71h) .................................................................................... 147 Column Address Operations .......................................................................................................................... 148 CHANGE READ COLUMN (05h-E0h) ......................................................................................................... 148 CHANGE READ COLUMN ENHANCED (06h-E0h) ...................................................................................... 149 CHANGE READ COLUMN ENHANCED (00h-05h-E0h) Operation ............................................................... 150 CHANGE WRITE COLUMN (85h) ............................................................................................................... 150 CHANGE ROW ADDRESS (85h) .................................................................................................................. 151 Read Operations ............................................................................................................................................ 153 READ MODE (00h) .................................................................................................................................... 155 READ PAGE (00h-30h) ............................................................................................................................... 156 READ PAGE CACHE SEQUENTIAL (31h) ..................................................................................................... 157 READ PAGE CACHE RANDOM (00h-31h) ................................................................................................... 158 READ PAGE CACHE LAST (3Fh) ................................................................................................................. 160 READ PAGE MULTI-PLANE (00h-32h) ........................................................................................................ 161 Read Retry Operations ............................................................................................................................... 162 Auto Read Calibration ................................................................................................................................ 163 Two Pass Programming .................................................................................................................................. 166 PROGRAM PAGE (80h-10h) ........................................................................................................................ 167 PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 6 1 / 1 / 7 : e s a e l e R

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features PROGRAM PAGE CACHE (80h-15h) ............................................................................................................ 170 PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................ 174 PROGRAM SUSPEND (84h) and PROGRAM RESUME (13h) ......................................................................... 181 Program Continuation ............................................................................................................................... 183 SLC Operations ......................................................................................................................................... 184 Erase Operations ........................................................................................................................................... 185 ERASE BLOCK (60h-D0h) ........................................................................................................................... 186 ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 186 ERASE BLOCK MULTI-PLANE (60h-60h-D0h) ............................................................................................ 187 ERASE SUSPEND (61h) and ERASE RESUME (D2h) .................................................................................... 187 Copyback Operations .................................................................................................................................... 190 COPYBACK READ (00h-35h) ...................................................................................................................... 191 COPYBACK PROGRAM (85h–10h) .............................................................................................................. 192 COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 196 COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 197 One-Time Programmable (OTP) Operations ................................................................................................... 200 PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 201 PROTECT OTP AREA (80h-10h) .................................................................................................................. 202 READ OTP PAGE (00h-30h) ........................................................................................................................ 203 Multi-Plane Operations ................................................................................................................................. 204 Multi-Plane Addressing ............................................................................................................................. 204 Interleaved Die (Multi-LUN) Operations ......................................................................................................... 204 Error Management ........................................................................................................................................ 206 Shared Pages - TLC ........................................................................................................................................ 207 Output Drive Impedance ............................................................................................................................... 211 AC Overshoot/Undershoot Specifications ....................................................................................................... 216 Input Slew Rate ............................................................................................................................................. 219 Output Slew Rate ........................................................................................................................................... 227 Power Cycle and Ramp Requirements ............................................................................................................ 230 Electrical Specifications ................................................................................................................................. 231 Package Electrical Specification and Pad Capacitance ................................................................................. 232 Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 234 Electrical Specifications – DC Characteristics and Operating Conditions (NV-DDR, NV-DDR2, NV-DDR3) ........ 235 Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 239 Single-Ended Requirements for Differential signals ..................................................................................... 243 Testing Conditions ........................................................................................................................................ 244 Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 245 Electrical Specifications – AC Characteristics and Operating Conditions (NV-DDR, NV-DDR2, NV-DDR3) ......... 248 Electrical Specifications – Array Characteristics .............................................................................................. 267 Asynchronous Interface Timing Diagrams ...................................................................................................... 269 NV-DDR Interface Timing Diagrams .............................................................................................................. 277 NV-DDR2 and NV-DDR3 Interface Timing Diagrams ...................................................................................... 296 Revision History ............................................................................................................................................ 319 Rev. E – 7/1/16 ........................................................................................................................................... 319 Rev. D – 06/04/16 ....................................................................................................................................... 321 Rev. C – 5/13/16 ......................................................................................................................................... 321 Rev. B – 11/25/15 ....................................................................................................................................... 326 Rev. A – 08/05/15 ....................................................................................................................................... 328 6 1 / 1 / 7 : e s a e l e R PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved.

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features List of Tables Table 1: Asynchronous, NV-DDR, NV-DDR2, and NV-DDR3 Signal Definitions ................................................ 15 Table 2: Array Addressing for Logical Unit (LUN) - TLC Mode operation .......................................................... 27 Table 3: Array Addressing for Logical Unit (LUN) - SLC Mode operation ........................................................... 29 Table 4: Asynchronous Interface Mode Selection ............................................................................................ 30 Table 5: NV-DDR Interface Mode Selection .................................................................................................... 38 Table 6: NV-DDR2 Interface Mode Selection ................................................................................................... 46 Table 7: On-die Termination DC Electrical Characteristics without ZQ Calibration ........................................... 49 Table 8: On-die Termination DC Electrical Characteristics with ZQ Calibration ................................................ 49 Table 9: RTT(EFF) Impedance Values with ZQ Calibration .................................................................................. 50 Table 10: LUN state for Matrix Termination .................................................................................................... 52 Table 11: Volume appointment for Matrix Termination example ..................................................................... 54 Table 12: Non-Target ODT for Data Output, Target ODT for Data Input settings configuration example ............ 55 Table 13: Parallel Non-Target ODT settings configuration example .................................................................. 58 Table 14: On-die Termination DC Electrical Characteristics without ZQ Calibration ......................................... 65 Table 15: On-die Termination DC Electrical Characteristics with ZQ Calibration .............................................. 66 Table 16: RTT(EFF) Impedance Values with ZQ Calibration ................................................................................ 66 Table 17: Command Set ................................................................................................................................. 84 Table 18: Read ID Parameters for Address 00h ................................................................................................ 93 Table 19: Read ID Parameters for Address 20h ................................................................................................ 93 Table 20: Read ID Parameters for Address 40h ................................................................................................ 93 Table 21: ONFI Parameter Page Data Structure ............................................................................................... 96 Table 22: JEDEC Parameter Page Defintion .................................................................................................... 105 Table 23: Feature Address Definitions ............................................................................................................ 112 Table 24: GET/SET FEATURES by LUN Operation LUN address cycle decoding .............................................. 115 Table 25: Feature Address 01h: Timing mode ................................................................................................. 115 Table 26: Feature Address 02h: NV-DDR2 and NV-DDR3 configuration ........................................................... 117 Table 27: Feature Address 30h: VPP ................................................................................................................ 119 Table 28: Feature Address 58h: Volume configuration .................................................................................... 119 Table 29: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 120 Table 30: Feature Address 81h: Programmable R/B# Pull-Down Strength ........................................................ 120 Table 31: Feature Addresses 89h: Read Retry .................................................................................................. 121 Table 32: Feature Address 90h: Array Operation Mode .................................................................................... 121 Table 33: Feature Address 91h: SLC Mode Enable ........................................................................................... 122 Table 34: Feature Address 96h: Auto Read Calibration .................................................................................... 123 Table 35: Feature Address DFh: Flag Check Functionality ............................................................................... 123 Table 36: Feature Address E6h: Sleep Mode and Sleep VCCQ ............................................................................ 124 Table 37: Sleep Mode and Sleep VCCQparameters ........................................................................................... 126 Table 38: Feature Address E7h: Temperature Sensor Readout ......................................................................... 128 Table 39: Temperature Sensor Readout parameter ......................................................................................... 129 Table 40: Feature Address F5h: Snap Read / Express Read .............................................................................. 129 Table 41: Feature Address F6h: Sleep Lite ...................................................................................................... 132 Table 42: LUN state for Matrix Termination with Sleep Lite Feature ................................................................ 133 Table 43: Volume Address ............................................................................................................................. 135 Table 44: ODT Configuration Matrix ............................................................................................................. 136 Table 45: LUN address cycle decoding ........................................................................................................... 142 Table 46: I/O Drive Strength Settings ............................................................................................................. 142 Table 47: Status Register Definition ............................................................................................................... 144 Table 48: R1 address cycle decoding for 71h Operation .................................................................................. 148 Table 49: PROGRAM SUSPEND (84h) Status Details ....................................................................................... 181 Table 50: ERASE SUSPEND (61h) Status Details ............................................................................................. 188 PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 6 1 / 1 / 7 : e s a e l e R

Micron Confidential and Proprietary Advance TLC 384Gb to 6Tb Async/Sync NAND Features Table 51: ERASE SUSPEND (61h) behavior for ERASE operations ................................................................... 188 Table 52: OTP Area Details ............................................................................................................................ 201 Table 53: Error Management Details ............................................................................................................. 206 Table 54: Shared Pages ................................................................................................................................. 207 Table 55: Output Drive Strength Conditions (VCCQ = 1.7–1.95V) ...................................................................... 211 Table 56: Output Drive Strength Impedance Values without ZQ Calibration (VCCQ = 1.7–1.95V) ....................... 211 Table 57: Output Drive Strength Impedance Values with ZQ Calibration (VCCQ = 1.7–1.95V) ............................ 212 Table 58: Output Drive Strength Conditions (VCCQ = 1.14–1.26V) .................................................................... 213 Table 59: Output Drive Strength Impedance Values without ZQ Calibration (VCCQ = 1.14–1.26V) ..................... 213 Table 60: Output Drive Strength Impedance Values with ZQ Calibration (VCCQ = 1.14–1.26V) .......................... 213 Table 61: Output Drive Sensitivity with ZQ Calibration ................................................................................... 214 Table 62: Output Driver Voltage and Temperature Sensitivity with ZQ Calibration ........................................... 215 Table 63: Pull-Up and Pull-Down Output Impedance Mismatch without ZQ Calibration for Asynchronous, NV- DDR and NV-DDR2 ................................................................................................................................... 215 Table 64: Pull-Up and Pull-Down Output Impedance Mismatch with ZQ Calibration for NV-DDR2 .................. 215 Table 65: Pull-Up and Pull-Down Output Impedance Mismatch without ZQ calibration for NV-DDR3 ............. 216 Table 66: Pull-Up and Pull-Down Output Impedance Mismatch with ZQ calibration for NV-DDR3 .................. 216 Table 67: Aynchronous Overshoot/Undershoot Parameters ........................................................................... 216 Table 68: NV-DDR Overshoot/Undershoot Parameters .................................................................................. 217 Table 69: NV-DDR2 Overshoot/Undershoot Parameters ................................................................................. 217 Table 70: NV-DDR3 Overshoot/Undershoot Parameters ................................................................................. 217 Table 71: Test Conditions for Input Slew Rate ................................................................................................ 219 Table 72: NV-DDR Maximum and Minimum Input Slew Rate ......................................................................... 219 Table 73: Input Slew Rate derating for NV-DDR (VCCQ = 1.7–1.95V) ................................................................. 219 Table 74: NV-DDR2/NV-DDR3 Maximum and Minimum Input Slew Rate ....................................................... 220 Table 75: Input Slew Rate derating for NV-DDR2 single-ended (VCCQ = 1.7–1.95V) .......................................... 221 Table 76: Input Slew Rate derating for NV-DDR2 differential (VCCQ = 1.7–1.95V) ............................................. 221 Table 77: Input Slew Rate derating for NV-DDR3 single-ended (VCCQ = 1.14–1.26V) ......................................... 222 Table 78: Input Slew Rate derating for NV-DDR3 differential (VCCQ = 1.14–1.26V) ............................................ 222 Table 79: Test Conditions for Output Slew Rate .............................................................................................. 227 Table 80: Output Slew Rate for Single-Ended Asynchronous, NV-DDR, or NV-DDR2 (VCCQ = 1.7–1.95V) without ZQ Calibration ........................................................................................................................................... 227 Table 81: Output Slew Rate for Differential NV-DDR2 (VCCQ = 1.7-1.95) without ZQ Calibration ....................... 227 Table 82: Output Slew Rate for Differential NV-DDR2 (VCCQ = 1.7-1.95) with ZQ Calibration ............................ 228 Table 83: Output Slew Rate Matching Ratio for NV-DDR2/NV-DDR3 without ZQ Calibration ........................... 228 Table 84: Output Slew Rate for Single-Ended NV-DDR3 (VCCQ = 1.14–1.26V) with ZQ Calibration ..................... 228 Table 85: Output Slew Rate for Differential NV-DDR3 (VCCQ = 1.14-1.26) with ZQ Calibration ........................... 228 Table 86: Output Slew Rate Matching Ratio for NV-DDR2/NV-DDR3 with ZQ Calibration ................................ 229 Table 87: Power Cycle Requirements ............................................................................................................. 230 Table 88: Absolute Maximum DC Ratings by Device ....................................................................................... 231 Table 89: Recommended Operating Conditions ............................................................................................. 231 Table 90: Valid Blocks per LUN ...................................................................................................................... 231 Table 91: Input Capacitance: 132-Ball BGA Package ....................................................................................... 232 Table 92: Package Electrical Specifications .................................................................................................... 233 Table 93: LUN Pad Specifications .................................................................................................................. 233 Table 94: DC Characteristics and Operating Conditions (Asynchronous Interface) 1.8V VCCQ ........................... 234 Table 95: DC Characteristics and Operating Conditions (NV-DDR, NV-DDR2 Interface) 1.8V VCCQ ................... 236 Table 96: DC Characteristics and Operating Conditions (NV-DDR3 Interface) 1.2V VCCQ ................................. 237 Table 97: Asynchronous/NV-DDR DC Characteristics and Operating Conditions (1.8V VCCQ) .......................... 239 Table 98: NV-DDR2 DC Characteristics and Operating Conditions for Single-Ended signals (1.8V VCCQ) ........... 240 Table 99: NV-DDR2 DC Characteristics and Operating Conditions for Differential signals (1.8V VCCQ) .............. 240 Table 100: NV-DDR3 DC Characteristics and Operating Conditions for Single-Ended signals (1.2V VCCQ) ......... 241 PDF: 09005aef86697e57 B0KB_Fortis_384Gb_768Gb_1HTb_1Tb_3Tb_6Tb_Sync_NAND_Datasheet Rev. E 7/1/16 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 6 1 / 1 / 7 : e s a e l e R

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