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RTL8363SC-VB-CG_DraftDatasheet_v0.3 for ADVCHIP.pdf
1. General Description
2. Features
3. System Applications
4. Application Examples
4.1. 2-Port 1000Base-T Switch
4.2. 2-Port 1000Base-T Router with SGMII/HSGMII
5. Block Diagram
6. Pin Assignments
6.1. Package Identification
6.2. Pin Assignments Table
7. Pin Descriptions
7.1. Media Dependent Interface Pins
7.2. High Speed Serial Interface Pins
7.3. General Purpose Interface Pins
7.4. LED Pins
7.5. Configuration Strapping Pins
7.6. Management Interface Pins
7.7. Miscellaneous Pins
7.8. Embedded Switch Regulator Pins
7.9. Power and GND Pins
8. Physical Layer Functional Overview
8.1. MDI Interface
8.2. 1000Base-T Transmit Function
8.3. 1000Base-T Receive Function
8.4. 100Base-TX Transmit Function
8.5. 100Base-TX Receive Function
8.6. 10Base-T Transmit Function
8.7. 10Base-T Receive Function
8.8. Auto-Negotiation for UTP
8.9. Crossover Detection and Auto Correction
8.10. Polarity Correction
9. General Function Description
9.1. Reset
9.1.1. Hardware Reset
9.1.2. Software Reset
9.1.2.1 CHIP_RESET
9.1.2.2 SOFT_RESET
9.2. IEEE 802.3x Full Duplex Flow Control
9.3. Half Duplex Flow Control
9.3.1. Back-Pressure Mode
9.4. Search and Learning
9.5. SVL and IVL/SVL
9.6. Illegal Frame Filtering
9.7. IEEE 802.3 Reserved Group Addresses Filtering Control
9.8. Broadcast/Multicast/Unknown DA Storm Control
9.9. Port Security Function
9.10. MIB Counters
9.11. Port Mirroring
9.12. VLAN Function
9.12.1. Port-Based VLAN
9.12.2. IEEE 802.1Q Tag-Based VLAN
9.12.3. Protocol-Based VLAN
9.12.4. Port VID
9.13. QoS Function
9.13.1. Input Bandwidth Control
9.13.2. Priority Assignment
9.13.3. Priority Queue Scheduling
9.13.4. IEEE 802.1p/Q and DSCP Remarking
9.13.5. ACL-Based Priority
9.14. IEEE 802.1x Function
9.14.1. Port-Based Access Control
9.14.2. Authorized Port-Based Access Control
9.14.3. Port-Based Access Control Direction
9.14.4. MAC-Based Access Control
9.14.5. MAC-Based Access Control Direction
9.14.6. Optional Unauthorized Behavior
9.15. IEEE 802.1D Function
9.16. Realtek Cable Test (RTCT)
9.17. LED Indicators
9.18. Green Ethernet
9.18.1. Link-On and Cable Length Power Saving
9.18.2. Link-Down Power Saving
9.19. IEEE 802.3az Energy Efficient Ethernet (EEE) Function
9.20. Regulator
10. Interface Descriptions
10.1. I2C Master for EEPROM Auto-load
10.2. Realtek I2C-Like Slave Interface for External CPU to Access RTL8363SC-VB
10.3. Slave MII Management SMI Interface for External CPU to Access RTL8363SC-VB
11. Electrical Characteristics
11.1. Absolute Maximum Ratings
11.2. Recommended Operating Range
11.3. Thermal Characteristics
11.3.1. Assembly Description
11.3.2. Material Properties
11.3.3. Simulation Conditions
11.3.4. Thermal Performance of QFN-56 on PCB Under Still Air Convection
11.4. DC Characteristics
11.5. AC Characteristics
11.5.1. I2C Master for EEPROM Auto-load Interface Timing Characteristics
11.5.2. Realtek I2C-like Slave Mode Timing Characteristics
11.5.3. Slave MII Management SMI for External CPU Access Interface Timing Characteristics
11.5.4. HSGMII Characteristics
11.5.5. SGMII/1000Base-X Characteristics
11.6. Power and Reset Characteristics
12. Mechanical Dimensions
13. Ordering Information
RTL8363SC-VB-CG
LAYER 2 MANAGED 2+1-PORT
10/100/1000M SWITCH CONTROLLER
DRAFT DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 0.3
22 August 2016
Track ID: xxxx-xxxx-xx
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211 Fax: +886-3-577-6047
www.realtek.com
COPYRIGHT
RTL8363SC-VB
Draft Datasheet
©2015 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
RTL8363SC-VB IC.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
Release Date
Summary
0.1
0.2
0.3
2016/07/15
First draft version.
2016/08/16
Revise Table 21. DC Characteristics error.
2016/08/22
Revise Table 21. DC Characteristics description and add note for power consumption.
Layer 2 Managed 2+1-Port 10/100/1000M Switch Controller
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Track ID: xxxx-xxxx-xx Rev. 0.3
Table of Contents
RTL8363SC-VB
Draft Datasheet
1. GENERAL DESCRIPTION .............................................................................................................................................. 1
2.
3.
FEATURES ......................................................................................................................................................................... 3
SYSTEM APPLICATIONS ............................................................................................................................................... 5
4. APPLICATION EXAMPLES ........................................................................................................................................... 5
4.1.
4.2.
2-PORT 1000BASE-T SWITCH ...................................................................................................................................... 5
2-PORT 1000BASE-T ROUTER WITH SGMII/HSGMII ................................................................................................. 6
5.
6.
BLOCK DIAGRAM ........................................................................................................................................................... 7
PIN ASSIGNMENTS ......................................................................................................................................................... 8
6.1.
6.2.
PACKAGE IDENTIFICATION ........................................................................................................................................... 8
PIN ASSIGNMENTS TABLE ............................................................................................................................................ 9
7.
PIN DESCRIPTIONS ...................................................................................................................................................... 11
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
MEDIA DEPENDENT INTERFACE PINS ......................................................................................................................... 11
HIGH SPEED SERIAL INTERFACE PINS ........................................................................................................................ 11
GENERAL PURPOSE INTERFACE PINS ......................................................................................................................... 11
LED PINS ................................................................................................................................................................... 12
CONFIGURATION STRAPPING PINS ............................................................................................................................. 13
MANAGEMENT INTERFACE PINS ................................................................................................................................ 13
MISCELLANEOUS PINS ............................................................................................................................................... 14
EMBEDDED SWITCH REGULATOR PINS ...................................................................................................................... 14
POWER AND GND PINS .............................................................................................................................................. 15
8.
PHYSICAL LAYER FUNCTIONAL OVERVIEW...................................................................................................... 16
8.1.
8.2.
8.3.
8.4.
8.5.
8.6.
8.7.
8.8.
8.9.
8.10.
MDI INTERFACE ........................................................................................................................................................ 16
1000BASE-T TRANSMIT FUNCTION ........................................................................................................................... 16
1000BASE-T RECEIVE FUNCTION .............................................................................................................................. 16
100BASE-TX TRANSMIT FUNCTION ........................................................................................................................... 16
100BASE-TX RECEIVE FUNCTION ............................................................................................................................. 17
10BASE-T TRANSMIT FUNCTION ............................................................................................................................... 17
10BASE-T RECEIVE FUNCTION .................................................................................................................................. 17
AUTO-NEGOTIATION FOR UTP .................................................................................................................................. 17
CROSSOVER DETECTION AND AUTO CORRECTION ..................................................................................................... 18
POLARITY CORRECTION ............................................................................................................................................. 18
9. GENERAL FUNCTION DESCRIPTION ...................................................................................................................... 19
9.1.
9.2.
9.3.
RESET ........................................................................................................................................................................ 19
9.1.1. Hardware Reset .................................................................................................................................................... 19
Software Reset ...................................................................................................................................................... 19
9.1.2.
IEEE 802.3X FULL DUPLEX FLOW CONTROL ............................................................................................................ 19
HALF DUPLEX FLOW CONTROL ................................................................................................................................. 20
9.3.1. Back-Pressure Mode ............................................................................................................................................ 20
SEARCH AND LEARNING ............................................................................................................................................ 21
9.4.
SVL AND IVL/SVL ................................................................................................................................................... 21
9.5.
ILLEGAL FRAME FILTERING ....................................................................................................................................... 21
9.6.
IEEE 802.3 RESERVED GROUP ADDRESSES FILTERING CONTROL ............................................................................. 22
9.7.
BROADCAST/MULTICAST/UNKNOWN DA STORM CONTROL ..................................................................................... 23
9.8.
9.9.
PORT SECURITY FUNCTION ........................................................................................................................................ 23
9.10. MIB COUNTERS ......................................................................................................................................................... 23
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RTL8363SC-VB
Draft Datasheet
9.14.
9.12.1.
9.12.2.
9.12.3.
9.12.4.
9.13.1.
9.13.2.
9.13.3.
9.13.4.
9.13.5.
9.11.
PORT MIRRORING ...................................................................................................................................................... 23
9.12. VLAN FUNCTION ...................................................................................................................................................... 24
Port-Based VLAN ............................................................................................................................................ 24
IEEE 802.1Q Tag-Based VLAN ....................................................................................................................... 24
Protocol-Based VLAN ..................................................................................................................................... 25
Port VID .......................................................................................................................................................... 25
9.13. QOS FUNCTION .......................................................................................................................................................... 26
Input Bandwidth Control ................................................................................................................................. 26
Priority Assignment ......................................................................................................................................... 26
Priority Queue Scheduling............................................................................................................................... 26
IEEE 802.1p/Q and DSCP Remarking ............................................................................................................ 27
ACL-Based Priority ......................................................................................................................................... 27
IEEE 802.1X FUNCTION ............................................................................................................................................. 27
Port-Based Access Control .............................................................................................................................. 27
Authorized Port-Based Access Control ........................................................................................................... 27
Port-Based Access Control Direction .............................................................................................................. 28
MAC-Based Access Control............................................................................................................................. 28
MAC-Based Access Control Direction ............................................................................................................ 28
Optional Unauthorized Behavior ..................................................................................................................... 28
IEEE 802.1D FUNCTION ............................................................................................................................................ 28
9.15.
REALTEK CABLE TEST (RTCT) ................................................................................................................................. 29
9.16.
LED INDICATORS ....................................................................................................................................................... 29
9.17.
9.18. GREEN ETHERNET ...................................................................................................................................................... 30
Link-On and Cable Length Power Saving ....................................................................................................... 30
Link-Down Power Saving ................................................................................................................................ 30
IEEE 802.3AZ ENERGY EFFICIENT ETHERNET (EEE) FUNCTION ............................................................................... 30
REGULATOR ............................................................................................................................................................... 31
9.14.1.
9.14.2.
9.14.3.
9.14.4.
9.14.5.
9.14.6.
9.18.1.
9.18.2.
9.19.
9.20.
10.
INTERFACE DESCRIPTIONS ...................................................................................................................................... 32
10.1.
10.2.
10.3.
I2C MASTER FOR EEPROM AUTO-LOAD .................................................................................................................. 32
REALTEK I2C-LIKE SLAVE INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8363SC-VB ....................................... 33
SLAVE MII MANAGEMENT SMI INTERFACE FOR EXTERNAL CPU TO ACCESS RTL8363SC-VB .............................. 34
11. ELECTRICAL CHARACTERISTICS .......................................................................................................................... 35
11.3.1.
11.3.2.
11.3.3.
11.3.4.
11.1. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................ 35
11.2.
RECOMMENDED OPERATING RANGE .......................................................................................................................... 35
THERMAL CHARACTERISTICS .................................................................................................................................... 36
11.3.
Assembly Description ...................................................................................................................................... 36
Material Properties ......................................................................................................................................... 36
Simulation Conditions ..................................................................................................................................... 36
Thermal Performance of QFN-56 on PCB Under Still Air Convection .......................................................... 36
11.4. DC CHARACTERISTICS ............................................................................................................................................... 37
11.5. AC CHARACTERISTICS ............................................................................................................................................... 38
I2C Master for EEPROM Auto-load Interface Timing Characteristics ........................................................... 38
Realtek I2C-like Slave Mode Timing Characteristics....................................................................................... 39
Slave MII Management SMI for External CPU Access Interface Timing Characteristics .............................. 40
HSGMII Characteristics .................................................................................................................................. 41
SGMII/1000Base-X Characteristics ................................................................................................................ 44
POWER AND RESET CHARACTERISTICS ...................................................................................................................... 46
11.5.1.
11.5.2.
11.5.3.
11.5.4.
11.5.5.
11.6.
12. MECHANICAL DIMENSIONS...................................................................................................................................... 47
13. ORDERING INFORMATION ........................................................................................................................................ 49
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RTL8363SC-VB
Draft Datasheet
List of Tables
TABLE 1. PIN ASSIGNMENTS TABLE .............................................................................................................................................. 9
TABLE 2. MEDIA DEPENDENT INTERFACE PINS ........................................................................................................................... 11
TABLE 3. HIGH SPEED SERIAL INTERFACE PINS .......................................................................................................................... 11
TABLE 4. GENERAL PURPOSE INTERFACES PINS .......................................................................................................................... 11
TABLE 5. LED PINS ..................................................................................................................................................................... 12
TABLE 6. CONFIGURATION STRAPPING PINS ............................................................................................................................... 13
TABLE 7. MANAGEMENT INTERFACE PINS .................................................................................................................................... 13
TABLE 8. MISCELLANEOUS PINS ................................................................................................................................................... 14
TABLE 9. EMBEDDED SWITCH REGULATOR PINS ......................................................................................................................... 14
TABLE 10. POWER AND GND PINS ................................................................................................................................................ 15
TABLE 11. MEDIA DEPENDENT INTERFACE PIN MAPPING ............................................................................................................ 18
TABLE 12. RESERVED MULTICAST ADDRESS CONFIGURATION TABLE ......................................................................................... 22
TABLE 13. LED DEFINITIONS........................................................................................................................................................ 29
TABLE 14. SLAVE MII MANAGEMENT SMI ACCESS FORMAT ....................................................................................................... 34
TABLE 15. ABSOLUTE MAXIMUM RATINGS .................................................................................................................................. 35
TABLE 16. RECOMMENDED OPERATING RANGE ........................................................................................................................... 35
TABLE 17. ASSEMBLY DESCRIPTION ............................................................................................................................................. 36
TABLE 18. MATERIAL PROPERTIES ............................................................................................................................................... 36
TABLE 19. SIMULATION CONDITIONS ........................................................................................................................................... 36
TABLE 20. THERMAL PERFORMANCE OF QFN-56 ON PCB UNDER STILL AIR CONVECTION ........................................................ 36
TABLE 21. DC CHARACTERISTICS ................................................................................................................................................. 37
TABLE 22. MASTER I2C FOR EEPROM AUTO-LOAD TIMING CHARACTERISTICS ......................................................................... 39
TABLE 23. REALTEK I2C-LIKE SLAVE MODE TIMING CHARACTERISTICS ..................................................................................... 40
TABLE 24. MDIO TIMING CHARACTERISTICS AND REQUIREMENT ............................................................................................... 41
TABLE 25. HSGMII DIFFERENTIAL TRANSMITTER CHARACTERISTICS ......................................................................................... 41
TABLE 26. HSGMII DIFFERENTIAL RECEIVER CHARACTERISTICS ............................................................................................... 43
TABLE 27. SGMII/1000BASE-X DIFFERENTIAL TRANSMITTER CHARACTERISTICS ...................................................................... 44
TABLE 28. SGMII/1000BASE-X DIFFERENTIAL RECEIVER CHARACTERISTICS ............................................................................ 45
TABLE 29. POWER AND RESET CHARACTERISTICS ........................................................................................................................ 46
TABLE 30. ORDERING INFORMATION ............................................................................................................................................ 49
List of Figures
FIGURE 1. 2-PORT 1000BASE-T SWITCH ....................................................................................................................................... 5
FIGURE 2. 2-PORT 1000BASE-T ROUTER WITH SGMII/HSGMII .................................................................................................. 6
FIGURE 3. BLOCK DIAGRAM .......................................................................................................................................................... 7
FIGURE 4. PIN ASSIGNMENTS (QFN-56) ........................................................................................................................................ 8
FIGURE 5. CONCEPTUAL EXAMPLE OF POLARITY CORRECTION .................................................................................................. 18
FIGURE 6. PROTOCOL-BASED VLAN FRAME FORMAT AND FLOW CHART .................................................................................. 25
FIGURE 7. PULL-UP AND PULL-DOWN OF LED PINS FOR SINGLE-COLOR LED........................................................................... 30
FIGURE 8. PULL-UP AND PULL-DOWN OF LED PINS FOR BI-COLOR LED ................................................................................... 30
FIGURE 9. I2C START AND STOP COMMAND ............................................................................................................................... 32
FIGURE 10. I2C MASTER FOR EEPROM AUTO-LOAD INTERFACE CONNECTION EXAMPLE .......................................................... 32
FIGURE 11. 16-BIT EEPROM SEQUENTIAL READ ........................................................................................................................ 32
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v
Track ID: xxxx-xxxx-xx Rev. 0.3
RTL8363SC-VB
Draft Datasheet
FIGURE 12. REALTEK I2C-LIKE SLAVE FOR EXTERNAL CPU ACCESS INTERFACE CONNECTION EXAMPLE ................................. 33
FIGURE 13. REALTEK I2C-LIKE SLAVE INTERFACE WRITE COMMAND ......................................................................................... 33
FIGURE 14. REALTEK I2C-LIKE SLAVE INTERFACE READ COMMAND .......................................................................................... 33
FIGURE 15. SLAVE MII MANAGEMENT SMI INTERFACE CONNECTION EXAMPLE......................................................................... 34
FIGURE 16. MASTER I2C FOR EEPROM AUTO-LOAD TIMING CHARACTERISTICS ........................................................................ 38
FIGURE 17. SCK/SDA POWER ON TIMING .................................................................................................................................... 38
FIGURE 18. EEPROM AUTO-LOAD TIMING.................................................................................................................................. 39
FIGURE 19. REALTEK I2C-LIKE SLAVE MODE TIMING CHARACTERISTICS .................................................................................... 39
FIGURE 20. MDIO SOURCED BY THE MASTER .............................................................................................................................. 40
FIGURE 21. MDIO SOURCED BY THE RTL8363SC-VB (SLAVE) .................................................................................................. 40
FIGURE 22. HSGMII DIFFERENTIAL TRANSMITTER EYE DIAGRAM .............................................................................................. 42
FIGURE 23. HSGMII DIFFERENTIAL RECEIVER EYE DIAGRAM .................................................................................................... 43
FIGURE 24. SGMII/1000BASE-X DIFFERENTIAL TRANSMITTER EYE DIAGRAM ........................................................................... 44
FIGURE 25. SGMII/1000BASE-X DIFFERENTIAL RECEIVER EYE DIAGRAM ................................................................................. 45
FIGURE 26. POWER AND RESET CHARACTERISTICS ....................................................................................................................... 46
Layer 2 Managed 2+1-Port 10/100/1000M Switch Controller
vi
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1. General Description
The RTL8363SC-VB-CG is a QFN-56, high-performance 2+1-port 10/100/1000M Ethernet switch
featuring a low-power integrated 2-port Giga-PHY that supports 1000Base-T, 100Base-TX, and 10Base-
T.
RTL8363SC-VB
Draft Datasheet
For specific applications, the RTL8363SC-VB supports one Ser-Des interface that could be configured as
SGMII/HSGMII/1000Base-X/100FX interfaces. The RTL8363SC-VB integrates all the functions of a
high-speed switch system; including SRAM for packet buffering, non-blocking switch fabric, and internal
register management into a single CMOS device. Only a 25MHz crystal is required; an optional
EEPROM is offered for internal register configuration.
The embedded packet storage SRAM in the RTL8363SC-VB features superior memory management
technology to efficiently utilize memory space. The RTL8363SC-VB integrates a 2048-entry look-up
table with a 4-way XOR Hashing algorithm for address searching and learning. The table provides
read/write access from the Slave I2C-like serial Interface, or Slave Media Independent Interface
Management (MIIM) Interface. Each of the entries can be configured as a static entry. Normal entry
aging time is between 200 and 400 seconds. Eight Filtering Databases are used to provide Independent
VLAN Learning and Shared VLAN Learning (IVL/SVL) functions.
The Extension GMAC1 of the RTL8363SC-VB implements a SGMII/HSGMII interfaces. This interface
could be connected to an external PHY, MAC, CPU, or RISC for specific applications. In router
applications, the RTL8363SC-VB supports Port VID (PVID) for each port to insert a PVID in the VLAN
tag on egress. When using this function, VID information carried in the VLAN tag will be changed to
PVID.
The RTL8363SC-VB supports standard 802.3x flow control frames for full duplex, and optional
backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the
availability of system resources, including the packet buffers and transmitting queues. The RTL8363SC-
VB supports broadcast/multicast output dropping, and will forward broadcast/multicast packets to non-
blocked ports only. For IP multicast application, the RTL8363SC-VB supports trapping IPv4 IGMP
v1/v2/v3 and IPv6 MLD v1/v2 to external CPU.
In order to support flexible traffic classification, the RTL8363SC-VB supports 48-entry ACL rule check
and multiple actions options. Each port can optionally enable or disable the ACL rule check function. The
ACL rule key can be based on packet physical port, Layer2, Layer3, and Layer4 information. When an
ACL rule matches, the action taken is configurable to Drop/Permit/Redirect/Mirror, change priority value
in 802.1q/Q tag, force output tag format and rate policing. The rate policing mechanism supports from
8Kbps to 1Gbps (in 8Kbps steps).
In Bridge operation the RTL8363SC-VB supports 16 sets of port configurations: disable, block, learning,
and forwarding for Spanning Tree Protocol and Multiple Spanning Tree Protocol. To meet security and
management application requirements, the RTL8363SC-VB supports IEEE 802.1x Port-based/MAC-
based Access Control. A 1-set Port Mirroring function is configured to mirror traffic (RX, TX, or both)
appearing on one of the switch’s ports. Support is provided on each port for multiple RFC MIB Counters,
for easy debug and diagnostics.
To improve real-time and multimedia networking applications, the RTL8363SC-VB supports eight
priority assignments for each received packet. These are based on (1) Port-based priority; (2) 802.1p/Q
VLAN tag priority; (3) DSCP field in IPv4/IPv6 header; and (4) ACL-assigned priority. Each output port
Layer 2 Managed 2+1-Port 10/100/1000M Switch Controller
1
Track ID: xxxx-xxxx-xx Rev. 0.3
supports a weighted ratio of eight priority queues to fit bandwidth requirements in different applications.
The input bandwidth control function helps limit per-port traffic utilization. There is one leaky bucket for
average packet rate control for each queue of all ports. Queue scheduling algorithm can use Strict Priority
(SP) or Weighted Fair Queue (WFQ) or Weighted Round Robin (WRR) or mixed.
RTL8363SC-VB
Draft Datasheet
The RTL8363SC-VB provides a 4K-entry VLAN table for 802.1Q port-based, tag-based, and protocol-
based VLAN operation to separate logical connectivity from physical connectivity. The RTL8363SC-VB
supports four Protocol-based VLAN configurations that can optionally select EtherType, LLC, and
RFC1042 as the search key. Each port may be set to any topology via EEPROM upon reset, or Slave I2C-
like serial Interface, or Slave Media Independent Interface Management (MIIM) Interface after reset.
In router applications, the router may want to know the input port of the incoming packet. The
RTL8363SC-VB supports an option to insert a VLAN tag with VID=Port VID (PVID) on each egress
port. The RTL8363SC-VB also provides an option to admit VLAN tagged packets with a specific PVID
only. If this function is enabled, the RTL8363SC-VB will drop all non-tagged packets and packets with
an incorrect PVID.
Layer 2 Managed 2+1-Port 10/100/1000M Switch Controller
2
Track ID: xxxx-xxxx-xx Rev. 0.3
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