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IEEE 规范 SystemVerilog 2017年最新版.pdf
IEEE Std 1800-2017 Front cover
Title page
Important Notices and Disclaimers Concerning IEEE Standards Documents
Participants
Introduction
Contents
List of figures
List of tables
List of syntax excerpts
Part One: Design and Verification Constructs
1. Overview
1.1 Scope
1.2 Purpose
1.3 Content summary
1.4 Special terms
1.5 Conventions used in this standard
1.6 Syntactic description
1.7 Use of color in this standard
1.8 Contents of this standard
1.9 Deprecated clauses
1.10 Examples
1.11 Prerequisites
2. Normative references
3. Design and verification building blocks
3.1 General
3.2 Design elements
3.3 Modules
3.4 Programs
3.5 Interfaces
3.6 Checkers
3.7 Primitives
3.8 Subroutines
3.9 Packages
3.10 Configurations
3.11 Overview of hierarchy
3.12 Compilation and elaboration
3.12.1 Compilation units
3.13 Name spaces
3.14 Simulation time units and precision
3.14.1 Time value rounding
3.14.2 Specifying time units and precision
3.14.2.1 The `timescale compiler directive
3.14.2.2 The timeunit and timeprecision keywords
3.14.2.3 Precedence of timeunit, timeprecision, and `timescale
3.14.3 Simulation time unit
4. Scheduling semantics
4.1 General
4.2 Execution of a hardware model and its verification environment
4.3 Event simulation
4.4 Stratified event scheduler
3.4.1 Active region sets and reactive region sets
3.4.2 Simulation regions
4.4.2.1 Preponed events region
4.4.2.2 Active events region
4.4.2.3 Inactive events region
4.4.2.4 NBA events region
4.4.2.5 Observed events region
4.4.2.6 Reactive events region
4.4.2.7 Re-Inactive events region
4.4.2.8 Re-NBA events region
4.4.2.9 Postponed events region
3.4.3 PLI regions
4.4.3.1 Preponed PLI region
4.4.3.2 Pre-Active PLI region
4.4.3.3 Pre-NBA PLI region
4.4.3.4 Post-NBA PLI region
4.4.3.5 Pre-Observed PLI region
4.4.3.6 Post-Observed PLI region
4.4.3.7 Pre-Re-NBA PLI region
4.4.3.8 Post-Re-NBA PLI region
4.4.3.9 Pre-Postponed PLI region
4.4.3.10 Postponed PLI region
4.5 SystemVerilog simulation reference algorithm
4.6 Determinism
4.7 Nondeterminism
4.8 Race conditions
4.9 Scheduling implication of assignments
4.9.1 Continuous assignment
4.9.2 Procedural continuous assignment
4.9.3 Blocking assignment
4.9.4 Nonblocking assignment
4.9.5 Switch (transistor) processing
3.9.6 Port connections
4.9.7 Subroutines
4.10 PLI callback control points
5. Lexical conventions
5.1 General
5.2 Lexical tokens
5.3 White space
5.4 Comments
5.5 Operators
5.6 Identifiers, keywords, and system names
5.6.1 Escaped identifiers
5.6.2 Keywords
5.6.3 System tasks and system functions
5.6.4 Compiler directives
5.7 Numbers
5.7.1 Integer literal constants
5.7.2 Real literal constants
5.8 Time literals
5.9 String literals
5.9.1 Special characters in strings
5.10 Structure literals
5.11 Array literals
5.12 Attributes
5.13 Built-in methods
6. Data types
6.1 General
6.2 Data types and data objects
6.3 Value set
6.3.1 Logic values
6.3.2 Strengths
6.3.2.1 Charge strength
6.3.2.2 Drive strength
6.4 Singular and aggregate types
6.5 Nets and variables
6.6 Net types
6.6.1 Wire and tri nets
6.6.2 Unresolved nets
6.6.3 Wired nets
6.6.4 Trireg net
6.6.4.1 Capacitive networks
6.6.4.2 Ideal capacitive state and charge decay
6.6.5 Tri0 and tri1 nets
6.6.6 Supply nets
6.6.7 User-defined nettypes
6.6.8 Generic interconnect
6.7 Net declarations
6.7.1 Net declarations with built-in net types
6.7.2 Net declarations with user-defined nettypes
6.7.3 Initialization of nets with user-defined nettypes
6.8 Variable declarations
6.9 Vector declarations
6.9.1 Specifying vectors
6.9.2 Vector net accessibility
6.10 Implicit declarations
6.11 Integer data types
6.11.1 Integral types
6.11.2 2-state (two-value) and 4-state (four-value) data types
6.11.3 Signed and unsigned integer types
6.12 Real, shortreal, and realtime data types
6.12.1 Operators and real numbers
6.12.2 Conversion
6.13 Void data type
6.14 Chandle data type
6.15 Class
6.16 String data type
6.16.1 Len()
6.16.2 Putc()
6.16.3 Getc()
6.16.4 Toupper()
6.16.5 Tolower()
6.16.6 Compare()
6.16.7 Icompare()
6.16.8 Substr()
6.16.9 Atoi(), atohex(), atooct(), atobin()
6.16.10 Atoreal()
6.16.11 Itoa()
6.16.12 Hextoa()
6.16.13 Octtoa()
6.16.14 Bintoa()
6.16.15 Realtoa()
6.17 Event data type
6.18 User-defined types
6.19 Enumerations
6.19.1 Defining new data types as enumerated types
6.19.2 Enumerated type ranges
6.19.3 Type checking
6.19.4 Enumerated types in numerical expressions
6.19.5 Enumerated type methods
6.19.5.1 First()
6.19.5.2 Last()
6.19.5.3 Next()
6.19.5.4 Prev()
6.19.5.5 Num()
6.19.5.6 Name()
6.19.5.7 Using enumerated type methods
6.20 Constants
6.20.1 Parameter declaration syntax
6.20.2 Value parameters
6.20.2.1 $ as a parameter value
6.20.3 Type parameters
6.20.4 Local parameters (localparam)
6.20.5 Specify parameters
6.20.6 Const constants
6.21 Scope and lifetime
6.22 Type compatibility
6.22.1 Matching types
6.22.2 Equivalent types
6.22.3 Assignment compatible
6.22.4 Cast compatible
6.22.5 Type incompatible
6.22.6 Matching nettypes
6.23 Type operator
6.24 Casting
6.24.1 Cast operator
6.24.2 $cast dynamic casting
6.24.3 Bit-stream casting
6.25 Parameterized data types
7. Aggregate data types
7.1 General
7.2 Structures
7.2.1 Packed structures
7.2.2 Assigning to structures
7.3 Unions
7.3.1 Packed unions
7.3.2 Tagged unions
7.4 Packed and unpacked arrays
7.4.1 Packed arrays
7.4.2 Unpacked arrays
7.4.3 Operations on arrays
7.4.4 Memories
7.4.5 Multidimensional arrays
7.4.6 Indexing and slicing of arrays
7.5 Dynamic arrays
7.5.1 New[ ]
7.5.2 Size()
7.5.3 Delete()
7.6 Array assignments
7.7 Arrays as arguments to subroutines
7.8 Associative arrays
7.8.1 Wildcard index type
7.8.2 String index
7.8.3 Class index
7.8.4 Integral index
7.8.5 Other user-defined types
7.8.6 Accessing invalid indices
7.8.7 Allocating associative array elements
7.9 Associative array methods
7.9.1 Num() and size()
7.9.2 Delete()
7.9.3 Exists()
7.9.4 First()
7.9.5 Last()
7.9.6 Next()
7.9.7 Prev()
7.9.8 Arguments to traversal methods
7.9.9 Associative array assignment
7.9.10 Associative array arguments
7.9.11 Associative array literals
7.10 Queues
7.10.1 Queue operators
7.10.2 Queue methods
7.10.2.1 Size()
7.10.2.2 Insert()
7.10.2.3 Delete()
7.10.2.4 Pop_front()
7.10.2.5 Pop_back()
7.10.2.6 Push_front()
7.10.2.7 Push_back()
7.10.3 Persistence of references to elements of a queue
7.10.4 Updating a queue using assignment and unpacked array concatenation
7.10.5 Bounded queues
7.11 Array querying functions
7.12 Array manipulation methods
7.12.1 Array locator methods
7.12.2 Array ordering methods
7.12.3 Array reduction methods
7.12.4 Iterator index querying
8. Classes
8.1 General
8.2 Overview
8.3 Syntax
8.4 Objects (class instance)
8.5 Object properties and object parameter data
8.6 Object methods
8.7 Constructors
8.8 Typed constructor calls
8.9 Static class properties
8.10 Static methods
8.11 This
8.12 Assignment, renaming, and copying
8.13 Inheritance and subclasses
8.14 Overridden members
8.15 Super
8.16 Casting
8.17 Chaining constructors
8.18 Data hiding and encapsulation
8.19 Constant class properties
8.20 Virtual methods
8.21 Abstract classes and pure virtual methods
8.22 Polymorphism: dynamic method lookup
8.23 Class scope resolution operator ::
8.24 Out-of-block declarations
8.25 Parameterized classes
8.25.1 Class scope resolution operator for parameterized classes
8.26 Interface classes
8.26.1 Interface class syntax
8.26.2 Extends versus implements
8.26.3 Type access
8.26.4 Type usage restrictions
8.26.5 Casting and object reference assignment
8.26.6 Name conflicts and resolution
8.26.6.1 Method name conflict resolution
8.26.6.2 Parameter and type declaration inheritance conflicts and resolution
8.26.6.3 Diamond relationship
8.26.7 Partial implementation
8.26.8 Method default argument values
8.26.9 Constraint blocks, covergroups, and randomization
8.27 Typedef class
8.28 Classes and structures
8.29 Memory management
9. Processes
9.1 General
9.2 Structured procedures
9.2.1 Initial procedures
9.2.2 Always procedures
9.2.2.1 General purpose always procedure
9.2.2.2 Combinational logic always_comb procedure
9.2.2.2.1 Implicit always_comb sensitivities
9.2.2.2.2 always_comb compared to always @*
9.2.2.3 Latched logic always_latch procedure
9.2.2.4 Sequential logic always_ff procedure
9.2.3 Final procedures
9.3 Block statements
9.3.1 Sequential blocks
9.3.2 Parallel blocks
9.3.3 Statement block start and finish times
9.3.4 Block names
9.3.5 Statement labels
9.4 Procedural timing controls
9.4.1 Delay control
9.4.2 Event control
9.4.2.1 Event OR operator
9.4.2.2 Implicit event_expression list
9.4.2.3 Conditional event controls
9.4.2.4 Sequence events
9.4.3 Level-sensitive event control
9.4.4 Level-sensitive sequence controls
9.4.5 Intra-assignment timing controls
9.5 Process execution threads
9.6 Process control
9.6.1 Wait fork statement
9.6.2 Disable statement
9.6.3 Disable fork statement
9.7 Fine-grain process control
10. Assignment statements
10.1 General
10.2 Overview
10.3 Continuous assignments
10.3.1 The net declaration assignment
10.3.2 The continuous assignment statement
10.3.3 Continuous assignment delays
10.3.4 Continuous assignment strengths
10.4 Procedural assignments
10.4.1 Blocking procedural assignments
10.4.2 Nonblocking procedural assignments
10.5 Variable declaration assignment (variable initialization)
10.6 Procedural continuous assignments
10.6.1 The assign and deassign procedural statements
10.6.2 The force and release procedural statements
10.7 Assignment extension and truncation
10.8 Assignment-like contexts
10.9 Assignment patterns
10.9.1 Array assignment patterns
10.9.2 Structure assignment patterns
10.10 Unpacked array concatenation
10.10.1 Unpacked array concatenations compared with array assignment patterns
10.10.2 Relationship with other constructs that use concatenation syntax
10.10.3 Nesting of unpacked array concatenations
10.11 Net aliasing
11. Operators and expressions
11.1 General
11.2 Overview
11.2.1 Constant expressions
11.2.2 Aggregate expressions
11.3 Operators
11.3.1 Operators with real operands
11.3.2 Operator precedence
11.3.3 Using integer literals in expressions
11.3.4 Operations on logic (4-state) and bit (2-state) types
11.3.5 Operator expression short circuiting
11.3.6 Assignment within an expression
11.4 Operator descriptions
11.4.1 Assignment operators
11.4.2 Increment and decrement operators
11.4.3 Arithmetic operators
11.4.3.1 Arithmetic expressions with unsigned and signed types
11.4.4 Relational operators
11.4.5 Equality operators
11.4.6 Wildcard equality operators
11.4.7 Logical operators
11.4.8 Bitwise operators
11.4.9 Reduction operators
11.4.10 Shift operators
11.4.11 Conditional operator
11.4.12 Concatenation operators
11.4.12.1 Replication operator
11.4.12.2 String concatenation
11.4.13 Set membership operator
11.4.14 Streaming operators (pack/unpack)
11.4.14.1 Concatenation of stream_expressions
11.4.14.2 Re-ordering of the generic stream
11.4.14.3 Streaming concatenation as an assignment target (unpack)
11.4.14.4 Streaming dynamically sized data
11.5 Operands
11.5.1 Vector bit-select and part-select addressing
11.5.2 Array and memory addressing
11.5.3 Longest static prefix
11.6 Expression bit lengths
11.6.1 Rules for expression bit lengths
11.6.2 Example of expression bit-length problem
11.6.3 Example of self-determined expressions
11.7 Signed expressions
11.8 Expression evaluation rules
11.8.1 Rules for expression types
11.8.2 Steps for evaluating an expression
11.8.3 Steps for evaluating an assignment
11.8.4 Handling X and Z in signed expressions
11.9 Tagged union expressions and member access
11.10 String literal expressions
11.10.1 String literal operations
11.10.2 String literal value padding and potential problems
11.10.3 Empty string literal handling
11.11 Minimum, typical, and maximum delay expressions
11.12 Let construct
12. Procedural programming statements
12.1 General
12.2 Overview
12.3 Syntax
12.4 Conditional if–else statement
12.4.1 if–else–if construct
12.4.2 unique-if, unique0-if, and priority-if
12.4.2.1 Violation reports generated by unique-if, unique0-if, and priority-if constructs
12.4.2.2 If statement violation reports and multiple processes
12.5 Case statement
12.5.1 Case statement with do-not-cares
12.5.2 Constant expression in case statement
12.5.3 unique-case, unique0-case, and priority-case
12.5.3.1 Violation reports generated by unique-case, unique0-case, and priority-case constructs
12.5.3.2 Case statement violation reports and multiple processes
12.5.4 Set membership case statement
12.6 Pattern matching conditional statements
12.6.1 Pattern matching in case statements
12.6.2 Pattern matching in if statements
12.6.3 Pattern matching in conditional expressions
12.7 Loop statements
12.7.1 The for-loop
12.7.2 The repeat loop
12.7.3 The foreach-loop
12.7.4 The while-loop
12.7.5 The do...while-loop
12.7.6 The forever-loop
12.8 Jump statements
13. Tasks and functions (subroutines)
13.1 General
13.2 Overview
13.3 Tasks
13.3.1 Static and automatic tasks
13.3.2 Task memory usage and concurrent activation
13.4 Functions
13.4.1 Return values and void functions
13.4.2 Static and automatic functions
13.4.3 Constant functions
13.4.4 Background processes spawned by function calls
13.5 Subroutine calls and argument passing
13.5.1 Pass by value
13.5.2 Pass by reference
13.5.3 Default argument values
13.5.4 Argument binding by name
13.5.5 Optional argument list
13.6 Import and export functions
13.7 Task and function names
13.8 Parameterized tasks and functions
14. Clocking blocks
14.1 General
14.2 Overview
14.3 Clocking block declaration
14.4 Input and output skews
14.5 Hierarchical expressions
14.6 Signals in multiple clocking blocks
14.7 Clocking block scope and lifetime
14.8 Multiple clocking blocks example
14.9 Interfaces and clocking blocks
14.10 Clocking block events
14.11 Cycle delay: ##
14.12 Default clocking
14.13 Input sampling
14.14 Global clocking
14.15 Synchronous events
14.16 Synchronous drives
14.16.1 Drives and nonblocking assignments
14.16.2 Driving clocking output signals
15. Interprocess synchronization and communication
15.1 General
15.2 Overview
15.3 Semaphores
15.3.1 New()
15.3.2 Put()
15.3.3 Get()
15.3.4 Try_get()
15.4 Mailboxes
15.4.1 New()
15.4.2 Num()
15.4.3 Put()
15.4.4 Try_put()
15.4.5 Get()
15.4.6 Try_get()
15.4.7 Peek()
15.4.8 Try_peek()
15.4.9 Parameterized mailboxes
15.5 Named events
15.5.1 Triggering an event
15.5.2 Waiting for an event
15.5.3 Persistent trigger: triggered built-in method
15.5.4 Event sequencing: wait_order()
15.5.5 Operations on named event variables
15.5.5.1 Merging events
15.5.5.2 Reclaiming events
15.5.5.3 Events comparison
16. Assertions
16.1 General
16.2 Overview
16.3 Immediate assertions
16.4 Deferred assertions
16.4.1 Deferred assertion reporting
16.4.2 Deferred assertion flush points
16.4.3 Deferred assertions outside procedural code
16.4.4 Disabling deferred assertions
16.4.5 Deferred assertions and multiple processes
16.5 Concurrent assertions overview
16.5.1 Sampling
16.5.2 Assertion clock
16.6 Boolean expressions
16.7 Sequences
16.8 Declaring sequences
16.8.1 Typed formal arguments in sequence declarations
16.8.2 Local variable formal arguments in sequence declarations
16.9 Sequence operations
16.9.1 Operator precedence
16.9.2 Repetition in sequences
16.9.2.1 Repetition, concatenation, and empty matches
16.9.3 Sampled value functions
16.9.4 Global clocking past and future sampled value functions
16.9.5 AND operation
16.9.6 Intersection (AND with length restriction)
16.9.7 OR operation
16.9.8 First_match operation
16.9.9 Conditions over sequences
16.9.10 Sequence contained within another sequence
16.9.11 Composing sequences from simpler subsequences
16.10 Local variables
16.11 Calling subroutines on match of a sequence
16.12 Declaring properties
16.12.1 Property instantiation
16.12.2 Sequence property
16.12.3 Negation property
16.12.4 Disjunction property
16.12.5 Conjunction property
16.12.6 If-else property
16.12.7 Implication
16.12.8 Implies and iff properties
16.12.9 Followed-by property
16.12.10 Nexttime property
16.12.11 Always property
16.12.12 Until property
16.12.13 Eventually property
16.12.14 Abort properties
16.12.15 Weak and strong operators
16.12.16 Case
16.12.17 Recursive properties
16.12.18 Typed formal arguments in property declarations
16.12.19 Local variable formal arguments in property declarations
16.12.20 Property examples
16.12.21 Finite-length versus infinite-length behavior
16.12.22 Nondegeneracy
16.13 Multiclock support
16.13.1 Multiclocked sequences
16.13.2 Multiclocked properties
16.13.3 Clock flow
16.13.4 Examples
16.13.5 Detecting and using end point of a sequence in multiclock context
16.13.6 Sequence methods
16.13.7 Local variable initialization assignments
16.14 Concurrent assertions
16.14.1 Assert statement
16.14.2 Assume statement
16.14.3 Cover statement
16.14.4 Restrict statement
16.14.5 Using concurrent assertion statements outside procedural code
16.14.6 Embedding concurrent assertions in procedural code
16.14.6.1 Arguments to procedural concurrent assertions
16.14.6.2 Procedural assertion flush points
16.14.6.3 Procedural concurrent assertions and glitches
16.14.6.4 Disabling procedural concurrent assertions
16.14.7 Inferred value functions
16.14.8 Nonvacuous evaluations
16.15 Disable iff resolution
16.16 Clock resolution
16.16.1 Semantic leading clocks for multiclocked sequences and properties
16.17 Expect statement
16.18 Clocking blocks and concurrent assertions
17. Checkers
17.1 Overview
17.2 Checker declaration
17.3 Checker instantiation
17.4 Context inference
17.5 Checker procedures
17.6 Covergroups in checkers
17.7 Checker variables
17.7.1 Checker variable assignments
17.7.2 Checker variable randomization with assumptions
17.7.3 Scheduling semantics
17.8 Functions in checkers
17.9 Complex checker example
18. Constrained random value generation
18.1 General
18.2 Overview
18.3 Concepts and usage
18.4 Random variables
18.4.1 Rand modifier
18.4.2 Randc modifier
18.5 Constraint blocks
18.5.1 External constraint blocks
18.5.2 Constraint inheritance
18.5.3 Set membership
18.5.4 Distribution
18.5.5 Uniqueness constraints
18.5.6 Implication
18.5.7 if–else constraints
18.5.8 Iterative constraints
18.5.8.1 foreach iterative constraints
18.5.8.2 Array reduction iterative constraints
18.5.9 Global constraints
18.5.10 Variable ordering
18.5.11 Static constraint blocks
18.5.12 Functions in constraints
18.5.13 Constraint guards
18.5.14 Soft constraints
18.5.14.1 Soft constraint priorities
18.5.14.2 Discarding soft constraints
18.6 Randomization methods
18.6.1 Randomize()
18.6.2 Pre_randomize() and post_randomize()
18.6.3 Behavior of randomization methods
18.7 In-line constraints—randomize() with
18.7.1 local:: scope resolution
18.8 Disabling random variables with rand_mode()
18.9 Controlling constraints with constraint_mode()
18.10 Dynamic constraint modification
18.11 In-line random variable control
18.11.1 In-line constraint checker
18.12 Randomization of scope variables—std::randomize()
18.12.1 Adding constraints to scope variables—std::randomize() with
18.13 Random number system functions and methods
18.13.1 $urandom
18.13.2 $urandom_range()
18.13.3 srandom()
18.13.4 get_randstate()
18.13.5 set_randstate()
18.14 Random stability
18.14.1 Random stability properties
18.14.2 Thread stability
18.14.3 Object stability
18.15 Manually seeding randomize
18.16 Random weighted case—randcase
18.17 Random sequence generation—randsequence
18.17.1 Random production weights
18.17.2 if–else production statements
18.17.3 Case production statements
18.17.4 Repeat production statements
18.17.5 Interleaving productions—rand join
18.17.6 Aborting productions—break and return
18.17.7 Value passing between productions
19. Functional coverage
19.1 General
19.2 Overview
19.3 Defining the coverage model: covergroup
19.4 Using covergroup in classes
19.5 Defining coverage points
19.5.1 Specifying bins for values
19.5.1.1 Coverpoint bin with covergroup expressions
19.5.1.2 Coverpoint bin set covergroup expressions
19.5.2 Specifying bins for transitions
19.5.3 Automatic bin creation for coverage points
19.5.4 Wildcard specification of coverage point bins
19.5.5 Excluding coverage point values or transitions
19.5.6 Specifying Illegal coverage point values or transitions
19.5.7 Value resolution
19.6 Defining cross coverage
19.6.1 Defining cross coverage bins
19.6.1.1 Example of user-defined cross coverage and select expressions
19.6.1.2 Cross bin with covergroup expressions
19.6.1.3 Cross bin automatically defined types
19.6.1.4 Cross bin set expression
19.6.2 Excluding cross products
19.6.3 Specifying illegal cross products
19.7 Specifying coverage options
19.7.1 Covergroup type options
19.8 Predefined coverage methods
19.8.1 Overriding the built-in sample method
19.9 Predefined coverage system tasks and system functions
19.10 Organization of option and type_option members
19.11 Coverage computation
19.11.1 Coverpoint coverage computation
19.11.2 Cross coverage computation
19.11.3 Type coverage computation
20. Utility system tasks and system functions
20.1 General
20.2 Simulation control system tasks
20.3 Simulation time system functions
20.3.1 $time
20.3.2 $stime
20.3.3 $realtime
20.4 Timescale system tasks
20.4.1 $printtimescale
20.4.2 $timeformat
20.5 Conversion functions
20.6 Data query functions
20.6.1 Type name function
20.6.2 Expression size system function
20.6.3 Range system function
20.7 Array query functions
20.7.1 Queries over multiple variable dimensions
20.8 Math functions
20.8.1 Integer math functions
20.8.2 Real math functions
20.9 Bit vector system functions
20.10 Severity tasks
20.11 Elaboration system tasks
20.12 Assertion control system tasks
20.13 Sampled value system functions
20.14 Coverage system functions
20.15 Probabilistic distribution functions
20.15.1 $random function
20.15.2 Distribution functions
20.16 Stochastic analysis tasks and functions
20.16.1 $q_initialize
20.16.2 $q_add
20.16.3 $q_remove
20.16.4 $q_full
20.16.5 $q_exam
20.16.6 Status codes
20.17 Programmable logic array modeling system tasks
20.17.1 Array types
20.17.2 Array logic types
20.17.3 Logic array personality declaration and loading
20.17.4 Logic array personality formats
20.18 Miscellaneous tasks and functions
20.18.1 $system
21. Input/output system tasks and system functions
21.1 General
21.2 Display system tasks
21.2.1 The display and write tasks
21.2.1.1 Escape sequences for special characters
21.2.1.2 Format specifications
21.2.1.3 Size of displayed data
21.2.1.4 Unknown and high-impedance values
21.2.1.5 Strength format
21.2.1.6 Hierarchical name format
21.2.1.7 Assignment pattern format
21.2.1.8 String format
21.2.2 Strobed monitoring
21.2.3 Continuous monitoring
21.3 File input/output system tasks and system functions
21.3.1 Opening and closing files
21.3.2 File output system tasks
21.3.3 Formatting data to a string
21.3.4 Reading data from a file
21.3.4.1 Reading a character at a time
21.3.4.2 Reading a line at a time
21.3.4.3 Reading formatted data
21.3.4.4 Reading binary data
21.3.5 File positioning
21.3.6 Flushing output
21.3.7 I/O error status
21.3.8 Detecting EOF
21.4 Loading memory array data from a file
21.4.1 Reading packed data
21.4.2 Reading 2-state types
21.4.3 File format considerations for multidimensional unpacked arrays
21.5 Writing memory array data to a file
21.5.1 Writing packed data
21.5.2 Writing 2-state types
21.5.3 Writing addresses to output file
21.6 Command line input
21.7 Value change dump (VCD) files
21.7.1 Creating 4-state VCD file
21.7.1.1 Specifying name of dump file ($dumpfile)
21.7.1.2 Specifying variables to be dumped ($dumpvars)
21.7.1.3 Stopping and resuming the dump ($dumpoff/$dumpon)
21.7.1.4 Generating a checkpoint ($dumpall)
21.7.1.5 Limiting size of dump file ($dumplimit)
21.7.1.6 Reading dump file during simulation ($dumpflush)
21.7.2 Format of 4-state VCD file
21.7.2.1 Syntax of 4-state VCD file
21.7.2.2 Formats of variable values
21.7.2.3 Description of keyword commands
21.7.2.4 4-state VCD file format example
21.7.3 Creating extended VCD file
21.7.3.1 Specifying dump file name and ports to be dumped ($dumpports)
21.7.3.2 Stopping and resuming the dump ($dumpportsoff/$dumpportson)
21.7.3.3 Generating a checkpoint ($dumpportsall)
21.7.3.4 Limiting size of dump file ($dumpportslimit)
21.7.3.5 Reading dump file during simulation ($dumpportsflush)
21.7.3.6 Description of keyword commands
21.7.3.6.1 $vcdclose
21.7.3.7 General rules for extended VCD system tasks
21.7.4 Format of extended VCD file
21.7.4.1 Syntax of extended VCD file
21.7.4.2 Extended VCD node information
21.7.4.3 Value changes
21.7.4.3.1 State characters
21.7.4.3.2 Drivers
21.7.4.4 Extended VCD file format example
21.7.5 VCD SystemVerilog type mappings
22. Compiler directives
22.1 General
22.2 Overview
22.3 `resetall
22.4 `include
22.5 `define, `undef, and `undefineall
22.5.1 `define
22.5.2 `undef
22.5.3 `undefineall
22.6 `ifdef, `else, `elsif, `endif, `ifndef
22.7 `timescale
22.8 `default_nettype
22.9 `unconnected_drive and `nounconnected_drive
22.10 `celldefine and `endcelldefine
22.11 `pragma
22.11.1 Standard pragmas
22.12 `line
22.13 `__FILE__ and `__LINE__
22.14 `begin_keywords, `end_keywords
22.14.1 Examples
22.14.2 IEEE 1364-1995 keywords
22.14.3 IEEE 1364-2001 keywords
22.14.4 IEEE 1364-2001-noconfig keywords
22.14.5 IEEE 1364-2005 keywords
22.14.6 IEEE 1800-2005 keywords
22.14.7 IEEE 1800-2009 keywords
22.14.8 IEEE 1800-2012 keywords
22.14.9 IEEE 1800-2017 keywords
Part Two: Hierarchy Constructs
23. Modules and hierarchy
23.1 General
23.2 Module definitions
23.2.1 Module header definition
23.2.2 Port declarations
23.2.2.1 Non-ANSI style port declarations
23.2.2.2 ANSI style list of port declarations
23.2.2.3 Rules for determining port kind, data type, and direction
23.2.2.4 Default port values
23.2.3 Parameterized modules
23.2.4 Module contents
23.3 Module instances (hierarchy)
23.3.1 Top-level modules and $root
23.3.2 Module instantiation syntax
23.3.2.1 Connecting module instance ports by ordered list
23.3.2.2 Connecting module instance ports by name
23.3.2.3 Connecting module instance using implicit named port connections (.name)
23.3.2.4 Connecting module instances using wildcard named port connections ( .*)
23.3.3 Port connection rules
23.3.3.1 Port coercion
23.3.3.2 Port connection rules for variables
23.3.3.3 Port connection rules for nets with built-in net types
23.3.3.4 Port connection rules for interfaces
23.3.3.5 Unpacked array ports and arrays of instances
23.3.3.6 Single source nets (uwire)
23.3.3.7 Port connections with dissimilar net types (net and port collapsing)
23.3.3.7.1 Port connections with interconnect net types
23.3.3.7.2 Terminal connections with interconnect net types
23.3.3.8 Connecting signed values via ports
23.4 Nested modules
23.5 Extern modules
23.6 Hierarchical names
23.7 Member selects and hierarchical names
23.7.1 Names with package or class scope resolution operator prefixes
23.8 Upwards name referencing
23.8.1 Task and function name resolution
23.9 Scope rules
23.10 Overriding module parameters
23.10.1 defparam statement
23.10.2 Module instance parameter value assignment
23.10.2.1 Parameter value assignment by ordered list
23.10.2.2 Parameter value assignment by name
23.10.3 Parameter dependence
23.10.4 Elaboration considerations
23.10.4.1 Order of elaboration
23.10.4.2 Early resolution of hierarchical names
23.11 Binding auxiliary code to scopes or instances
24. Programs
24.1 General
24.2 Overview
24.3 The program construct
24.3.1 Scheduling semantics of code in program constructs
24.3.2 Operation of program port connections in the absence of clocking blocks
24.4 Eliminating testbench races
24.5 Blocking tasks in cycle/event mode
24.6 Programwide space and anonymous programs
24.7 Program control tasks
25. Interfaces
25.1 General
25.2 Overview
25.3 Interface syntax
25.3.1 Example without using interfaces
25.3.2 Interface example using a named bundle
25.3.3 Interface example using a generic bundle
25.4 Ports in interfaces
25.5 Modports
25.5.1 Example of named port bundle
25.5.2 Example of connecting port bundle
25.5.3 Example of connecting port bundle to generic interface
25.5.4 Modport expressions
25.5.5 Clocking blocks and modports
25.6 Interfaces and specify blocks
25.7 Tasks and functions in interfaces
25.7.1 Example of using tasks in interface
25.7.2 Example of using tasks in modports
25.7.3 Example of exporting tasks and functions
25.7.4 Example of multiple task exports
25.8 Parameterized interfaces
25.9 Virtual interfaces
25.9.1 Virtual interfaces and clocking blocks
25.9.2 Virtual interface modports and clocking blocks
25.10 Access to interface objects
26. Packages
26.1 General
26.2 Package declarations
26.3 Referencing data in packages
26.4 Using packages in module headers
26.5 Search order rules
26.6 Exporting imported names from packages
26.7 The std built-in package
27. Generate constructs
27.1 General
27.2 Overview
27.3 Generate construct syntax
27.4 Loop generate constructs
27.5 Conditional generate constructs
27.6 External names for unnamed generate blocks
28. Gate-level and switch-level modeling
28.1 General
28.2 Overview
28.3 Gate and switch declaration syntax
28.3.1 The gate type specification
28.3.2 The drive strength specification
28.3.3 The delay specification
28.3.4 The primitive instance identifier
28.3.5 The range specification
28.3.6 Primitive instance connection list
28.4 and, nand, nor, or, xor, and xnor gates
28.5 buf and not gates
28.6 bufif1, bufif0, notif1, and notif0 gates
28.7 MOS switches
28.8 Bidirectional pass switches
28.9 CMOS switches
28.10 pullup and pulldown sources
28.11 Logic strength modeling
28.12 Strengths and values of combined signals
28.12.1 Combined signals of unambiguous strength
28.12.2 Ambiguous strengths: sources and combinations
28.12.3 Ambiguous strength signals and unambiguous signals
28.12.4 Wired logic net types
28.13 Strength reduction by nonresistive devices
28.14 Strength reduction by resistive devices
28.15 Strengths of net types
28.15.1 tri0 and tri1 net strengths
28.15.2 trireg strength
28.15.3 supply0 and supply1 net strengths
28.16 Gate and net delays
28.16.1 min:typ:max delays
28.16.2 trireg net charge decay
28.16.2.1 Charge decay process
28.16.2.2 Delay specification for charge decay time
29. User-defined primitives
29.1 General
29.2 Overview
29.3 UDP definition
29.3.1 UDP header
29.3.2 UDP port declarations
29.3.3 Sequential UDP initial statement
29.3.4 UDP state table
29.3.5 Z values in UDP
29.3.6 Summary of symbols
29.4 Combinational UDPs
29.5 Level-sensitive sequential UDPs
29.6 Edge-sensitive sequential UDPs
29.7 Sequential UDP initialization
29.8 UDP instances
29.9 Mixing level-sensitive and edge-sensitive descriptions
29.10 Level-sensitive dominance
30. Specify blocks
30.1 General
30.2 Overview
30.3 Specify block declaration
30.4 Module path declarations
30.4.1 Module path restrictions
30.4.2 Simple module paths
30.4.3 Edge-sensitive paths
30.4.4 State-dependent paths
30.4.4.1 Conditional expression
30.4.4.2 Simple state-dependent paths
30.4.4.3 Edge-sensitive state-dependent paths
30.4.4.4 The ifnone condition
30.4.5 Full connection and parallel connection paths
30.4.6 Declaring multiple module paths in a single statement
30.4.7 Module path polarity
30.4.7.1 Unknown polarity
30.4.7.2 Positive polarity
30.4.7.3 Negative polarity
30.5 Assigning delays to module paths
30.5.1 Specifying transition delays on module paths
30.5.2 Specifying x transition delays
30.5.3 Delay selection
30.6 Mixing module path delays and distributed delays
30.7 Detailed control of pulse filtering behavior
30.7.1 Specify block control of pulse limit values
30.7.2 Global control of pulse limit values
30.7.3 SDF annotation of pulse limit values
30.7.4 Detailed pulse control capabilities
30.7.4.1 On-event versus on-detect pulse filtering
30.7.4.2 Negative pulse detection
31. Timing checks
31.1 General
31.2 Overview
31.3 Timing checks using a stability window
31.3.1 $setup
31.3.2 $hold
31.3.3 $setuphold
31.3.4 $removal
31.3.5 $recovery
31.3.6 $recrem
31.4 Timing checks for clock and control signals
31.4.1 $skew
31.4.2 $timeskew
31.4.3 $fullskew
31.4.4 $width
31.4.5 $period
31.4.6 $nochange
31.5 Edge-control specifiers
31.6 Notifiers: user-defined responses to timing violations
31.7 Enabling timing checks with conditioned events
31.8 Vector signals in timing checks
31.9 Negative timing checks
31.9.1 Requirements for accurate simulation
31.9.2 Conditions in negative timing checks
31.9.3 Notifiers in negative timing checks
31.9.4 Option behavior
32. Backannotation using the standard delay format
32.1 General
32.2 Overview
32.3 The SDF annotator
32.4 Mapping of SDF constructs to SystemVerilog
32.4.1 Mapping of SDF delay constructs to SystemVerilog declarations
32.4.2 Mapping of SDF timing check constructs to SystemVerilog
32.4.3 SDF annotation of specparams
32.4.4 SDF annotation of interconnect delays
32.5 Multiple annotations
32.6 Multiple SDF files
32.7 Pulse limit annotation
32.8 SDF to SystemVerilog delay value mapping
32.9 Loading timing data from an SDF file
33. Configuring the contents of a design
33.1 General
33.2 Overview
33.2.1 Library notation
33.2.2 Basic configuration elements
33.3 Libraries
33.3.1 Specifying libraries—the library map file
33.3.1.1 File path resolution
33.3.2 Using multiple library map files
33.3.3 Mapping source files to libraries
33.4 Configurations
33.4.1 Basic configuration syntax
33.4.1.1 Design statement
33.4.1.2 The default clause
33.4.1.3 The instance clause
33.4.1.4 The cell clause
33.4.1.5 The liblist clause
33.4.1.6 The use clause
33.4.2 Hierarchical configurations
33.4.3 Setting parameters in configurations
33.5 Using libraries and configs
33.5.1 Precompiling in a single-pass use model
33.5.2 Elaboration-time compiling in a single-pass use model
33.5.3 Precompiling using a separate compilation tool
33.5.4 Command line considerations
33.6 Configuration examples
33.6.1 Default configuration from library map file
33.6.2 Using default clause
33.6.3 Using cell clause
33.6.4 Using instance clause
33.6.5 Using hierarchical config
33.7 Displaying library binding information
33.8 Library mapping examples
33.8.1 Using the command line to control library searching
33.8.2 File path specification examples
33.8.3 Resolving multiple path specifications
34. Protected envelopes
34.1 General
34.2 Overview
34.3 Processing protected envelopes
34.3.1 Encryption
34.3.2 Decryption
34.4 Protect pragma directives
34.5 Protect pragma keywords
34.5.1 begin
34.5.1.1 Syntax
34.5.1.2 Description
34.5.2 end
34.5.2.1 Syntax
34.5.2.2 Description
34.5.3 begin_protected
34.5.3.1 Syntax
34.5.3.2 Description
34.5.4 end_protected
34.5.4.1 Syntax
34.5.4.2 Description
34.5.5 author
34.5.5.1 Syntax
34.5.5.2 Description
34.5.6 author_info
34.5.6.1 Syntax
34.5.6.2 Description
34.5.7 encrypt_agent
34.5.7.1 Syntax
34.5.7.2 Description
34.5.8 encrypt_agent_info
34.5.8.1 Syntax
34.5.8.2 Description
34.5.9 encoding
34.5.9.1 Syntax
34.5.9.2 Description
34.5.10 data_keyowner
34.5.10.1 Syntax
34.5.10.2 Description
34.5.11 data_method
34.5.11.1 Syntax
34.5.11.2 Description
34.5.12 data_keyname
34.5.12.1 Syntax
34.5.12.2 Description
34.5.13 data_public_key
34.5.13.1 Syntax
34.5.13.2 Description
34.5.14 data_decrypt_key
34.5.14.1 Syntax
34.5.14.2 Description
34.5.15 data_block
34.5.15.1 Syntax
34.5.15.2 Description
34.5.16 digest_keyowner
34.5.16.1 Syntax
34.5.16.2 Description
34.5.17 digest_key_method
34.5.17.1 Syntax
34.5.17.2 Description
34.5.18 digest_keyname
34.5.18.1 Syntax
34.5.18.2 Description
34.5.19 digest_public_key
34.5.19.1 Syntax
34.5.19.2 Description
34.5.20 digest_decrypt_key
34.5.20.1 Syntax
34.5.20.2 Description
34.5.21 digest_method
34.5.21.1 Syntax
34.5.21.2 Description
34.5.22 digest_block
34.5.22.1 Syntax
34.5.22.2 Description
34.5.23 key_keyowner
34.5.23.1 Syntax
34.5.23.2 Description
34.5.24 key_method
34.5.24.1 Syntax
34.5.24.2 Description
34.5.25 key_keyname
34.5.25.1 Syntax
34.5.25.2 Description
34.5.26 key_public_key
34.5.26.1 Syntax
34.5.26.2 Description
34.5.27 key_block
34.5.27.1 Syntax
34.5.27.2 Description
34.5.28 decrypt_license
34.5.28.1 Syntax
34.5.28.2 Description
34.5.29 runtime_license
34.5.29.1 Syntax
34.5.29.2 Description
34.5.30 comment
34.5.30.1 Syntax
34.5.30.2 Description
34.5.31 reset
34.5.31.1 Syntax
34.5.31.2 Description
34.5.32 viewport
34.5.32.1 Syntax
34.5.32.2 Description
Part Three: Application Programming Interfaces
35. Direct programming interface
35.1 General
35.2 Overview
35.2.1 Tasks and functions
35.2.2 Data types
35.2.2.1 Data representation
35.3 Two layers of DPI
35.3.1 DPI SystemVerilog layer
35.3.2 DPI foreign language layer
35.4 Global name space of imported and exported functions
35.5 Imported tasks and functions
35.5.1 Required properties of imported tasks and functions—semantic constraints
35.5.1.1 Instant completion of imported functions
35.5.1.2 input, output, and inout arguments
35.5.1.3 Special properties pure and context
35.5.1.4 Memory management
35.5.1.5 Reentrancy of imported tasks
35.5.1.6 C++ exceptions
35.5.2 Pure functions
35.5.3 Context tasks and functions
35.5.4 Import declarations
35.5.5 Function result
35.5.6 Types of formal arguments
35.5.6.1 Open arrays
35.6 Calling imported functions
35.6.1 Argument passing
35.6.1.1 WYSIWYG principle
35.6.2 Value changes for output and inout arguments
35.7 Exported functions
35.8 Exported tasks
35.9 Disabling DPI tasks and functions
36. Programming language interface (PLI/VPI) overview
36.1 General
36.2 PLI purpose and history
36.3 User-defined system task and system function names
36.3.1 Defining system task and system function names
36.3.2 Overriding built-in system task and system function names
36.4 User-defined system task and system function arguments
36.5 User-defined system task and system function types
36.6 User-supplied PLI applications
36.7 PLI include files
36.8 VPI sizetf, compiletf, and calltf routines
36.8.1 sizetf VPI application routine
36.8.2 compiletf VPI application routine
36.8.3 calltf VPI application routine
36.8.4 Arguments to sizetf, compiletf, and calltf application routines
36.9 PLI mechanism
36.9.1 Registering user-defined system tasks and system functions
36.9.2 Registering simulation callbacks
36.10 VPI access to SystemVerilog objects and simulation objects
36.10.1 Error handling
36.10.2 Function availability
36.10.3 Traversing expressions
36.11 List of VPI routines by functional category
36.12 VPI backwards compatibility features and limitations
36.12.1 VPI Incompatibilities with other standard versions
36.12.2 VPI Mechanisms to deal with incompatibilities
36.12.2.1 Mechanism 1: Compile-based binding to a compatibility mode
36.12.2.2 Mechanism 2: Selection of default VPI compatibility mode run by host simulator
36.12.3 Limitations of VPI compatibility mechanisms
37. VPI object model diagrams
37.1 General
37.2 VPI Handles
37.2.1 Handle creation
37.2.2 Handle release
37.2.3 Handle comparison
37.2.4 Validity of handles
37.3 VPI object classifications
37.3.1 Accessing object relationships and properties
37.3.2 Object type properties
37.3.3 Object file and line properties
37.3.4 Delays and values
37.3.5 Expressions with side effects
37.3.6 Object protection properties
37.3.7 Lifetimes of objects
37.3.8 Managing transient objects
37.4 Key to data model diagrams
37.4.1 Diagram key for objects and classes
37.4.2 Diagram key for accessing properties
37.4.3 Diagram key for traversing relationships
37.5 Module
37.6 Interface
37.7 Modport
37.8 Interface task or function declaration
37.9 Program
37.10 Instance
37.11 Instance arrays
37.12 Scope
37.13 IO declaration
37.14 Ports
37.15 Reference objects
37.16 Nets
37.17 Variables
37.18 Packed array variables
37.19 Variable select
37.20 Memory
37.21 Variable drivers and loads
37.22 Object Range
37.23 Typespec
37.24 Structures and unions
37.25 Named events
37.26 Parameter, spec param, def param, param assign
37.27 Virtual interface
37.28 Interface typespec
37.29 Class definition
37.30 Class typespec
37.31 Class variables and class objects
37.32 Constraint, constraint ordering, distribution
37.33 Primitive, prim term
37.34 UDP
37.35 Intermodule path
37.36 Constraint expression
37.37 Module path, path term
37.38 Timing check
37.39 Task and function declaration
37.40 Task and function call
37.41 Frames
37.42 Threads
37.43 Delay terminals
37.44 Net drivers and loads
37.45 Continuous assignment
37.46 Clocking block
37.47 Assertion
37.48 Concurrent assertions
37.49 Property declaration
37.50 Property specification
37.51 Sequence declaration
37.52 Sequence expression
37.53 Immediate assertions
37.54 Multiclock sequence expression
37.55 Let
37.56 Simple expressions
37.57 Expressions
37.58 Atomic statement
37.59 Dynamic prefixing
37.60 Event statement
37.61 Process
37.62 Assignment
37.63 Event control
37.64 While, repeat
37.65 Waits
37.66 Delay control
37.67 Repeat control
37.68 Forever
37.69 If, if–else
37.70 Case, pattern
37.71 Expect
37.72 For
37.73 Do-while, foreach
37.74 Alias statement
37.75 Disables
37.76 Return statement
37.77 Assign statement, deassign, force, release
37.78 Callback
37.79 Time queue
37.80 Active time format
37.81 Attribute
37.82 Iterator
37.83 Generates
38. VPI routine definitions
38.1 General
38.2 vpi_chk_error()
38.3 vpi_compare_objects()
38.4 vpi_control()
38.5 vpi_flush()
38.6 vpi_get()
38.7 vpi_get64()
38.8 vpi_get_cb_info()
38.9 vpi_get_data()
38.10 vpi_get_delays()
38.11 vpi_get_str()
38.12 vpi_get_systf_info()
38.13 vpi_get_time()
38.14 vpi_get_userdata()
38.15 vpi_get_value()
38.16 vpi_get_value_array()
38.17 vpi_get_vlog_info()
38.18 vpi_handle()
38.19 vpi_handle_by_index()
38.20 vpi_handle_by_multi_index()
38.21 vpi_handle_by_name()
38.22 vpi_handle_multi()
38.23 vpi_iterate()
38.24 vpi_mcd_close()
38.25 vpi_mcd_flush()
38.26 vpi_mcd_name()
38.27 vpi_mcd_open()
38.28 vpi_mcd_printf()
38.29 vpi_mcd_vprintf()
38.30 vpi_printf()
38.31 vpi_put_data()
38.32 vpi_put_delays()
38.33 vpi_put_userdata()
38.34 vpi_put_value()
38.35 vpi_put_value_array()
38.36 vpi_register_cb()
38.36.1 Simulation event callbacks
38.36.1.1 Callbacks on individual statements
38.36.1.2 Behavior by statement type
38.36.1.3 Registering callbacks on module-wide basis
38.36.2 Simulation time callbacks
38.36.3 Simulator action or feature callbacks
38.37 vpi_register_systf()
38.37.1 System task and system function callbacks
38.37.2 Initializing VPI system task or system function callbacks
38.37.3 Registering multiple system tasks and system functions
38.38 vpi_release_handle()
38.39 vpi_remove_cb()
38.40 vpi_scan()
38.41 vpi_vprintf()
39. Assertion API
39.1 General
39.2 Overview
39.3 Static information
39.3.1 Obtaining assertion handles
39.3.2 Obtaining static assertion information
39.4 Dynamic information
39.4.1 Placing assertion system callbacks
39.4.2 Placing assertions callbacks
39.4.2.1 Placing callbacks for assertions with global clocking future sampled value functions
39.5 Control functions
39.5.1 Assertion system control
39.5.2 Assertion control
39.5.3 VPI functions on deferred assertions and procedural concurrent assertions
40. Code coverage control and API
40.1 General
40.2 Overview
40.2.1 SystemVerilog coverage API
40.2.2 Nomenclature
40.3 SystemVerilog real-time coverage access
40.3.1 Predefined coverage constants in SystemVerilog
40.3.2 Built-in coverage access system functions
40.3.2.1 $coverage_control
40.3.2.2 $coverage_get_max
40.3.2.3 $coverage_get
40.3.2.4 $coverage_merge
40.3.2.5 $coverage_save
40.4 FSM recognition
40.4.1 Specifying signal that holds current state
40.4.2 Specifying part-select that holds current state
40.4.3 Specifying concatenation that holds current state
40.4.4 Specifying signal that holds next state
40.4.5 Specifying current and next state signals in same declaration
40.4.6 Specifying possible states of FSM
40.4.7 Pragmas in one-line comments
40.4.8 Example
40.5 VPI coverage extensions
40.5.1 VPI entity/relation diagrams related to coverage
40.5.2 Extensions to VPI enumerations
40.5.3 Obtaining coverage information
40.5.4 Controlling coverage
41. Data read API
Part Four: Annexes
Annex A (normative) Formal syntax
A.1 Source text
A.1.1 Library source text
A.1.2 SystemVerilog source text
A.1.3 Module parameters and ports
A.1.4 Module items
A.1.5 Configuration source text
A.1.6 Interface items
A.1.7 Program items
A.1.8 Checker items
A.1.9 Class items
A.1.10 Constraints
A.1.11 Package items
A.2 Declarations
A.2.1 Declaration types
A.2.1.1 Module parameter declarations
A.2.1.2 Port declarations
A.2.1.3 Type declarations
A.2.2 Declaration data types
A.2.2.1 Net and variable types
A.2.2.2 Strengths
A.2.2.3 Delays
A.2.3 Declaration lists
A.2.4 Declaration assignments
A.2.5 Declaration ranges
A.2.6 Function declarations
A.2.7 Task declarations
A.2.8 Block item declarations
A.2.9 Interface declarations
A.2.10 Assertion declarations
A.2.11 Covergroup declarations
A.2.12 Let declarations
A.3 Primitive instances
A.3.1 Primitive instantiation and instances
A.3.2 Primitive strengths
A.3.3 Primitive terminals
A.3.4 Primitive gate and switch types
A.4 Instantiations
A.4.1 Instantiation
A.4.1.1 Module instantiation
A.4.1.2 Interface instantiation
A.4.1.3 Program instantiation
A.4.1.4 Checker instantiation
A.4.2 Generated instantiation
A.5 UDP declaration and instantiation
A.5.1 UDP declaration
A.5.2 UDP ports
A.5.3 UDP body
A.5.4 UDP instantiation
A.6 Behavioral statements
A.6.1 Continuous assignment and net alias statements
A.6.2 Procedural blocks and assignments
A.6.3 Parallel and sequential blocks
A.6.4 Statements
A.6.5 Timing control statements
A.6.6 Conditional statements
A.6.7 Case statements
A.6.7.1 Patterns
A.6.8 Looping statements
A.6.9 Subroutine call statements
A.6.10 Assertion statements
A.6.11 Clocking block
A.6.12 Randsequence
A.7 Specify section
A.7.1 Specify block declaration
A.7.2 Specify path declarations
A.7.3 Specify block terminals
A.7.4 Specify path delays
A.7.5 System timing checks
A.7.5.1 System timing check commands
A.7.5.2 System timing check command arguments
A.7.5.3 System timing check event definitions
A.8 Expressions
A.8.1 Concatenations
A.8.2 Subroutine calls
A.8.3 Expressions
A.8.4 Primaries
A.8.5 Expression left-side values
A.8.6 Operators
A.8.7 Numbers
A.8.8 Strings
A.9 General
A.9.1 Attributes
A.9.2 Comments
A.9.3 Identifiers
A.9.4 White space
A.10 Footnotes (normative)
Annex B (normative) Keywords
Annex C (normative) Deprecation
C.1 General
C.2 Constructs that have been deprecated
C.2.1 PLI TF and ACC routine libraries
C.2.2 $sampled with a clocking event argument
C.2.3 ended sequence method
C.2.4 vpi_free_object()
C.2.5 Data read API
C.2.6 Linked lists
C.2.7 always statement in checkers
C.2.8 Operator overloading
C.3 Accellera SystemVerilog 3.1a-compatible access to packed data
C.4 Constructs identified for deprecation
C.4.1 Defparam statements
C.4.2 Procedural assign and deassign statements
C.4.3 VPI definitions
Annex D (informative) Optional system tasks and system functions
D.1 General
D.2 $countdrivers
D.3 $getpattern
D.4 $input
D.5 $key and $nokey
D.6 $list
D.7 $log and $nolog
D.8 $reset, $reset_count, and $reset_value
D.9 $save, $restart, and $incsave
D.10 $scale
D.11 $scope
D.12 $showscopes
D.13 $showvars
D.14 $sreadmemb and $sreadmemh
Annex E (informative) Optional compiler directives
E.1 General
E.2 `default_decay_time
E.3 `default_trireg_strength
E.4 `delay_mode_distributed
E.5 `delay_mode_path
E.6 `delay_mode_unit
E.7 `delay_mode_zero
Annex F (normative) Formal semantics of concurrent assertions
F.1 General
F.2 Overview
F.3 Abstract syntax
F.3.1 Clock control
F.3.2 Abstract grammars
F.3.3 Notations
F.3.4 Derived forms
F.3.4.1 Derived assertion statements
F.3.4.2 Derived sequence operators
F.3.4.2.1 Derived consecutive repetition operators
F.3.4.2.2 Derived delay and concatenation operators
F.3.4.2.3 Derived nonconsecutive repetition operators
F.3.4.2.4 Other derived operators
F.3.4.3 Derived property operators
F.3.4.3.1 Derived sequential property
F.3.4.3.2 Derived Boolean operators
F.3.4.3.3 Derived nonoverlapping implication operator
F.3.4.3.4 Derived conditional operators
F.3.4.3.5 Derived case operators
F.3.4.3.6 Derived followed_by operators
F.3.4.3.7 Derived abort operators
F.3.4.3.8 Derived unbounded temporal operators
F.3.4.3.9 Derived bounded temporal operators
F.3.4.4 Derived sampled value functions
F.3.4.5 Other derived operators
F.3.4.6 Free checker variable assignment
F.4 Rewriting algorithms
F.4.1 Rewriting sequence and property instances
F.4.1.1 The rewriting algorithm
F.4.2 Rewriting checkers
F.4.2.1 The rewriting algorithm
F.4.3 Rewriting local variable declaration assignments
F.5 Semantics
F.5.1 Rewrite rules for clocks
F.5.1.1 Rewrite rules for sequences
F.5.1.2 Rewrite rules for properties
F.5.2 Tight satisfaction without local variables
F.5.3 Satisfaction without local variables
F.5.3.1 Neutral satisfaction
F.5.3.2 Weak and strong satisfaction by finite words
F.5.3.3 Vacuity
F.5.4 Local variable flow
F.5.5 Tight satisfaction with local variables
F.5.6 Satisfaction with local variables
F.5.6.1 Neutral satisfaction
F.5.6.2 Weak and strong satisfaction by finite words
F.5.6.3 Vacuity
F.6 Extended expressions
F.6.1 Extended Booleans
F.6.2 Past
F.6.3 Future
F.7 Recursive properties
Annex G (normative) Std package
G.1 General
G.2 Overview
G.3 Semaphore
G.4 Mailbox
G.5 Randomize
G.6 Process
Annex H (normative) DPI C layer
H.1 General
H.2 Overview
H.3 Naming conventions
H.4 Portability
H.5 svdpi.h include file
H.6 Semantic constraints
H.6.1 Types of formal arguments
H.6.2 Input arguments
H.6.3 Output arguments
H.6.4 Value changes for output and inout arguments
H.6.5 Context and noncontext tasks and functions
H.6.6 Memory management
H.7 Data types
H.7.1 Limitations
H.7.2 Duality of types: SystemVerilog types versus C types
H.7.3 Data representation
H.7.4 Basic types
H.7.5 Normalized and linearized ranges
H.7.6 Mapping between SystemVerilog ranges and C ranges
H.7.7 Canonical representation of packed arrays
H.7.8 Unpacked aggregate arguments
H.8 Argument passing modes
H.8.1 Overview
H.8.2 Calling SystemVerilog tasks and functions from C
H.8.3 Argument passing by value
H.8.4 Argument passing by reference
H.8.5 Allocating actual arguments for SystemVerilog-specific types
H.8.6 Argument passing by handle—open arrays
H.8.7 Input arguments
H.8.8 Inout and output arguments
H.8.9 Function result
H.8.10 String arguments
H.8.10.1 String types in aggregate arguments
H.9 Context tasks and functions
H.9.1 Overview of DPI and VPI context
H.9.2 Context of imported and exported tasks and functions
H.9.3 Working with DPI context tasks and functions in C code
H.9.4 Example 1—Using DPI context functions
H.9.5 Relationship between DPI and VPI
H.10 Include files
H.10.1 Include file svdpi.h
H.10.1.1 Scalars of type bit and logic
H.10.1.2 Canonical representation of packed arrays
H.10.1.3 Implementation-dependent representation
H.10.2 Example 2—Simple packed array application
H.10.3 Example 3—Application with complex mix of types
H.11 Arrays
H.11.1 Example 4—Using packed 2-state arguments
H.11.2 Multidimensional arrays
H.11.3 Example 5—Using packed struct and union arguments
H.11.4 Direct access to unpacked arrays
H.11.5 Utility functions for working with the canonical representation
H.12 Open arrays
H.12.1 Actual ranges
H.12.2 Array querying functions
H.12.3 Access functions
H.12.4 Access to actual representation
H.12.5 Access to elements via canonical representation
H.12.6 Access to scalar elements (bit and logic)
H.12.7 Access to array elements of other types
H.12.8 Example 6—Two-dimensional open array
H.12.9 Example 7—Open array
H.12.10 Example 8—Access to packed arrays
H.13 SV3.1a-compatible access to packed data (deprecated functionality)
H.13.1 Determining the compatibility level of an implementation
H.13.2 svdpi.h definitions for SV3.1a-style packed data processing
H.13.3 Source-level compatibility include file svdpi_src.h
H.13.4 Example 9—Deprecated SV3.1a binary-compatible application
H.13.5 Example 10—Deprecated SV3.1a source-compatible application
H.13.6 Example 11—Deprecated SV3.1a binary-compatible calls of export functions
Annex I (normative) svdpi.h
I.1 General
I.2 Overview
I.3 Source code
Annex J (normative) Inclusion of foreign language code
J.1 General
J.2 Overview
J.3 Location independence
J.4 Object code inclusion
J.4.1 Bootstrap file
J.4.2 Examples
Annex K (normative) vpi_user.h
K.1 General
K.2 Source code
Annex L (normative) vpi_compatibility.h
L.1 General
L.2 Source code
Annex M (normative) sv_vpi_user.h
M.1 General
M.2 Source code
Annex N (normative) Algorithm for probabilistic distribution functions
N.1 General
N.2 Source code
Annex O (informative) Encryption/decryption flow
O.1 General
O.2 Overview
O.3 Tool vendor secret key encryption system
O.3.1 Encryption input
O.3.2 Encryption output
O.4 IP author secret key encryption system
O.4.1 Encryption input
O.4.2 Encryption output
O.5 Digital envelopes
O.5.1 Encryption input
O.5.2 Encryption output
Annex P (informative) Glossary
Annex Q (informative) Bibliography
Back cover
IEEE Standard for SystemVerilog—
Unified Hardware Design,
Specification, and Verification
Language
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Design Automation Standards Committee
Sponsored by the
IEEE
3 Park Avenue
New York, NY 10016-5997
USA
IEEE Std 1800™-2017
(Revision of
IEEE Std 1800-2012)
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IEEE Std 1800™-2017
(Revision of
IEEE Std 1800-2012)
IEEE Standard for SystemVerilog—
Unified Hardware Design,
Specification, and Verification
Language
Sponsor
Design Automation Standards Committee
of the
IEEE Computer Society
and the
IEEE Standards Association Corporate Advisory Group
Approved 6 December 2017
IEEE-SA Standards Board
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Abstract: The definition of the language syntax and semantics for SystemVerilog, which is a unified
hardware design, specification, and verification language, is provided. This standard includes
support for modeling hardware at the behavioral, register transfer level (RTL), and gate-level
abstraction levels, and for writing testbenches using coverage, assertions, object-oriented
programming, and constrained random verification. The standard also provides application
programming interfaces (APIs) to foreign programming languages.
Keywords: assertions, design automation, design verification, hardware description language,
HDL, HDVL, IEEE 1800™, PLI, programming language interface, SystemVerilog, Verilog®, VPI
The Institute of Electrical and Electronics Engineers, Inc.
3 Park Avenue, New York, NY 10016-5997, USA
Copyright © 2018 by The Institute of Electrical and Electronics Engineers, Inc.
All rights reserved. Published 21 February 2018. Printed in the United States of America.
IEEE, 802, and POSIX are registered trademarks in the U.S. Patent & Trademark Office, owned by The Institute of
Electrical and Electronics Engineers, Incorporated.
Verilog is a registered trademark of Cadence Design Systems, Inc.
Print:
PDF:
ISBN 978-1-5044-4510-8
ISBN 978-1-5044-4509-2
STDPD22888
STDGT22888
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Copyright © 2018 IEEE. All rights reserved.
2
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Participants
The SystemVerilog Language Working Group is entity based. At the time this standard was completed,
the SystemVerilog Working Group had the following membership:
Karen Pieper, Accellera Systems Initiative, Chair
Neil Korpusik, Oracle Corporation, Vice Chair, Technical Chair
Dennis Brophy, Mentor, a Siemens Business, Secretary
Shalom Bresticker, Accellera Systems Initiative, Editor
Dave Rich, Mentor, a Siemens Business
Dmitry Korchemny, Synopsys, Inc.
Michiel Ligthart, Design Automation, Inc.
Matt Maidment, Intel Corporation
Scott Little, Mentor, a Siemens Business
Charles Dawson, Cadence Design Systems, Inc.
Work on this standard was divided among primary committees.
The Design and Testbench Committee (SV-BC) was responsible for the specification of the design and
testbench features of SystemVerilog.
Matt Maidment, Intel Corporation, Chair
Brad Pierce, Synopsys, Inc., Co-Chair
Shalom Bresticker, Accellera Systems Initiative
Jonathan Bromley, Oracle Corporation
Eric Coffin, Mentor, a Siemens Business
Mark Hartoog, Synopsys, Inc.
Neil Korpusik, Oracle Corporation
Francoise Martinolle, Cadence Design Systems, Inc.
C. Venkat Ramana Rao, Mentor, a Siemens Business
Justin Refice, NVIDIA Corporation
Dave Rich, Mentor, a Siemens Business
Ray Ryan, Mentor, a Siemens Business
Arturo Salz, Synopsys, Inc.
Steven Sharp, Cadence Design Systems, Inc.
Mark Strickland, Cisco Systems, Inc.
Brandon Tipp, Intel Corporation
The Assertions Committee (SV-AC) was responsible for the specification of the assertion features of
SystemVerilog.
Dmitry Korchemny, Synopsys, Inc., Chair
Erik Seligman, Intel Corporation, Co-Chair
Mehbub Ali, Intel Corporation
Shalom Bresticker, Accellera Systems Initiative
Eduard Cerny, Synopsys, Inc.
Ang Boon Chong, Intel Corporation
Ben Cohen, Accellera Systems Initiative
Manisha Kulshrestha, Mentor Graphics Corporation
Anupam Prabhakar, Mentor Graphics Corporation
Samik Sengupta, Synopsys, Inc.
The Discrete Committee (SV-DC) was responsible for defining features to support modeling of analog/
mixed-signal circuit components in the discrete domain.
Scott Little, Mentor, a Siemens Business, Chair
Scott Cranston, Cadence Design Systems, Inc., Co-Chair
Kevin Cameron, Samsung
Shekar Chetput, Cadence Design Systems, Inc.
Dave Cronauer, Synopsys, Inc.
Mark Hartoog, Synopsys, Inc.
Arturo Salz, Synopsys, Inc.
Aaron Spratt, Cadence Design Systems, Inc.
Martin Vlach, Mentor, a Siemens Business
Gordon Vreugdenhil, Mentor, a Siemens Business
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The following members of the entity balloting committee voted on this standard. Balloters may have voted
for approval, disapproval, or abstention.
Accellera Systems Initiative, Inc.
Cadence Design Systems, Inc.
Cisco Systems, Inc.
Intel Corporation
Oracle, Inc.
Siemens Corporation
Synopsys, Inc.
Verific Design Automation, Inc.
When the IEEE-SA Standards Board approved this standard on 6 December 2017, it had the following
membership:
Jean-Philippe Faure, Chair
Gary Hoffman, Vice Chair
John D. Kulick, Past Chair
Konstantinos Karachalios, Secretary
Chuck Adams
Masayuki Ariyoshi
Ted Burse
Stephen Dukes
Doug Edwards
J. Travis Griffith
Michael Janezic
*Member Emeritus
Thomas Koshy
Joseph L. Koepfinger*
Kevin Lu
Daleep Mohla
Damir Novosel
Ronald C. Petersen
Annette D. Reilly
Robby Robson
Dorothy Stanley
Adrian Stephens
Mehmet Ulema
Phil Wennblom
Howard Wolfman
Yu Yuan
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