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xilinx 10G mac.pdf
10 Gigabit Ethernet Subsystem v3.1
Table of Contents
IP Facts
Ch. 1: Overview
10G Ethernet MAC
10GBASE-R
10GBASE-KR
Feature Summary
Applications
Unsupported Features
Licensing and Ordering
License Checkers
License Type
Ch. 2: Product Specification
Standards
Performance
Resource Utilization
Latency
32-bit Datapath
Transmit Path Latency
Receive Path Latency
64-bit Datapath
Transmit Path Latency
Receive Path Latency
Port Descriptions
AXI4-Stream Transmit Interface
AXI4-Stream Receive Interface
Flow Control Interface (IEEE 802.3)
Priority Flow Control Interface (802.1Qbb)
Serial Data Ports
Optical Module Interface Ports
Clock and Reset Ports
Shared Logic Included in Example Design
Shared Logic Included in Core
Tx Buffer Bypass Manual Phase Alignment Ports
10GBASE-KR Training Interface
DRP Interface Ports
Zynq-7000, Virtex-7, and Kintex-7 Devices
UltraScale Architecture
PCS/PMA Miscellaneous Ports
Speeding up Simulation
Transceiver Debug Ports
AXI4-Lite Management Interface Ports
10G Ethernet MAC Configuration and Status Signals
Statistics Vector Signals
Transmit Statistics Vector
Receive Statistics Vector
PCS/PMA Configuration and Status Signals
BASE-R
BASE-KR
Interrupt Signal
IEEE 1588 Transmitted Timestamp Ports
IEEE 1588 Received Timestamp Ports
IEEE 1588 System Timer Ports
Time-of-Day (ToD) System Timer Format
Correction Field System Timer Format
Register Space
Statistics Counters
10G Ethernet MAC Configuration Registers
MDIO Control Registers
Interrupt Output Registers
PCS/PMA Register Map
MDIO Register 1.0: PMA/PMD Control 1
MDIO Register 1.1: PMA/PMD Status 1
MDIO Register 1.4: PMA/PMD Speed Ability
MDIO Registers 1.5 and 1.6: PMA/PMD Devices in Package
MDIO Register 1.7: 10G PMA/PMD Control 2
MDIO Register 1.8: 10G PMA/PMD Status 2
MDIO Register 1.9: 10G PMD Transmit Disable
MDIO Register 1.10: 10G PMD Signal Receive OK
MDIO Register 1.150: 10GBASE-KR PMD Control
MDIO Register 1.151: 10GBASE-KR PMD Status
MDIO Register 1.152: 10GBASE-KR LP Coefficient Update
MDIO Register 1.153: 10GBASE-KR LP Status
MDIO Register 1.154: 10GBASE-KR LD Coefficient Update
MDIO Register 1.155: 10GBASE-KR LD Status
MDIO Register 1.170: 10GBASE-R FEC Ability
MDIO Register 1.171: 10GBASE-R FEC Control
MDIO Register 1.172: 10GBASE-R FEC Corrected Blocks (Lower)
MDIO Register 1.173: 10GBASE-R FEC Corrected Blocks (Upper)
MDIO Register 1.174: 10GBASE-R FEC Uncorrected Blocks (Lower)
MDIO Register 1.175: 10GBASE-R FEC Uncorrected Blocks (Upper)
MDIO Register: 1.65520: Vendor-Specific LD Training
MDIO Register 1.65535: Core Version Info for 10G PCS/PMA Subcore
MDIO Register 3.0: PCS Control 1
MDIO Register 3.1: PCS Status 1
MDIO Register 3.4: PCS Speed Ability
MDIO Registers 3.5 and 3.6: PCS Devices in Package
MDIO Register 3.7: 10G PCS Control 2
MDIO Register 3.8: 10G PCS Status 2
MDIO Register 3.32: 10GBASE-R Status 1
MDIO Register 3.33: 10GBASE-R Status 2
MDIO Register 3.34–37: 10GBASE-R Test Pattern Seed A0–3
MDIO Register 3.38–41: 10GBASE-R Test Pattern Seed B0–3
MDIO Register 3.42: 10GBASE-R Test Pattern Control
MDIO Register 3.43: 10GBASE-R Test Pattern Error Counter
MDIO Register 3.65520: IEEE1588 Control
MDIO Register 3.65521: RX Fixed Latency, Integer ns
MDIO Register 3.65522: RX Fixed Latency, Fractional ns
MDIO Register 3.65535: 125 Microsecond Timer Control
MDIO Register 7.0: AN Control
MDIO Register 7.1: AN Status
MDIO Register 7.16:17:18: AN Advertisement
MDIO Register 7.19, 20, 21: AN LP Base Page Ability
MDIO Register 7.22, 23, 24: AN XNP Transmit
MDIO Register 7.25, 26, 27: AN LP XNP Ability
MDIO Register 7.48: Backplane Ethernet Status
Ch. 3: Designing with the Subsystem
Clocking
Resets
7 Series Clocking and Shared Logic
Shared Logic
Core Level Logic
UltraScale Device Clocking and Shared Logic Using the RX Elastic Buffer
GTHE3/GTYE3 (32-bit Datapath)
Shared Logic
Core Level Logic
GTHE3 with the 64-bit Datapath
UltraScale Device Clocking and Shared Logic Omitting the RX Elastic Buffer
Shared Logic
Core Level Logic
Shared Logic for 7 Series IEEE 1588 Support
Ethernet Protocol Description
Ethernet Sublayer Architecture
MAC and MAC CONTROL Sublayer
Physical Sublayers PCS, PMA, and PMD
Ethernet Data Format
Preamble
Start of Frame Delimiter
MAC Address Fields
MAC Address
Destination Address
Source Address
Length/Type
Data
Pad
FCS
Frame Transmission and Interframe Gap
Deficit Idle Count
Connecting the Data Interfaces
Transmit AXI4-Stream Interface
Normal Frame Transmission
In-Band Ethernet Frame Fields
Padding
Transmission with In-Band FCS Passing
Aborting a Transmission
Back-to-Back Continuous Transfers
Transmission of Custom Preamble
VLAN Tagged Frames
Transmitter Maximum Permitted Frame Length
Interframe Gap Adjustment
Deficit Idle Count (DIC)
Transmission of Frames During Local/Remote Fault or Link Interruption Reception
Receive AXI4-Stream Interface
Normal Frame Reception
Timing for a Good or a Bad Frame
Frame Reception with Errors
Reception with In-Band FCS Passing
Reception of Custom Preamble
VLAN Tagged Frames
Receiver Maximum Permitted Frame Length
Length/Type Field Error Checks
Enabled
Disabled
IEEE 1588 Timestamping
Transmit
Frame-by-Frame Timestamping Operation
Transmitter Latency and Timestamp Adjustment
Transmit – Providing the Command Field In-band
Transmit - Providing the Command Field Out-of-Band
Receive
Receiver Latency and Timestamp Adjustment
Receive – Timestamp In Line With Frame Reception
Connecting the Management Interface
MDIO Interface
MDIO Transaction Types
Set Address Transaction
Write Transaction
Read Transaction
Post-Read-Increment-Address Transaction
Using the AXI4-Lite Interface to Access PHY Registers over MDIO
IEEE 802.3 Flow Control
Flow Control Requirement
Flow Control Basics
IEEE 802.3 Pause Control Frames
Transmitting a Pause Control Frame
Core-Initiated Pause Request
XON/XOFF Extended Functionality
Client-Initiated Pause Request
Receiving a Pause Control Frame
Core-Initiated Response to a Pause Request
Client-Initiated Response to a Pause Request
Flow Control Implementation Example
Method
Operation
Priority Flow Control
Priority Flow Control Requirement
Priority-Based Flow Control Frames
Transmitting a PFC Frame
Core-Initiated Request
Client-Initiated Request
Receiving a PFC Frame
Core-Initiated Response to a PFC request
PFC Frame Reception Disabled
Pause Frame Reception Enabled
Client-Initiated Response to a Pause Request
PFC Implementation Example
Method
Operation
Receiver Termination
Special Design Considerations
Connecting Multiple Subsystem Instances (No IEEE 1588 Support)
Zynq-7000, Virtex-7, and Kintex-7 Devices
UltraScale Devices
Using Training and Auto-Negotiation with the Management Interface
Using Training and Auto-Negotiation with No Management Interface
Using FEC in the Subsystem with Auto-Negotiation
Using FIFOs in IP Integrator
Ch. 4: Design Flow Steps
Customizing and Generating the Subsystem
Component Name
Ethernet Standard
PCS/PMA Standard
AXI4-Stream datapath width
MAC Options
AXI4-Lite for Configuration and Status
AXI4-Lite Frequency (MHz)
Statistics Gathering
IEEE802.1Qbb Priority-based Flow Control
PCS/PMA Options
Auto-Negotiation
Forward Error Correction (FEC)
Exclude RX Elastic Buffer
DRP Clocking
Transceiver Type
Transceiver Location
Transceiver RefClk Location
Reference Clock Frequency (MHz)
IEEE 1588 Options
IEEE 1588 Hardware Timestamping Support
1588 Timer Format
Shared Logic
User Parameters
Output Generation
Constraining the Subsystem
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Synthesis and Implementation
Ch. 5: Example Design
Ethernet FIFO
RX FIFO
TX FIFO
Basic Pattern Generator Module
Address Swap
Pattern Generator
Pattern Checker
AXI4-Lite Control State Machine
Shared Logic and the Support Layer
Ch. 6: Test Bench 重要
DEMO Mode
BIST Mode
Changing the Test Bench
Changing Frame Data in Demo Mode
Changing Frame Length
Changing Frame Error Status
Appx. A: Upgrading
Migrating to the Vivado Design Suite
Upgrading in the Vivado Design Suite
Parameter Changes
Port Changes in Version 2.0
Ports Added in Version 3.0
Ports Changed in Version 3.0
Ports Changed in Version 3.1
Appx. B: Debugging
Finding Help on Xilinx.com
Documentation
Solution Centers
Answer Records
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Hardware Debug
General Checks
What Can Cause a Local or Remote Fault?
Local Fault
Remote Fault
Link Bring Up – Basic
High Level Link Up (10GBASE-R or 10GBASE-KR with Auto-Negotiation + Training Disabled)
Stage 1: Device A Powered Up, but Device B Powered Down
Stage 2: Device B Powers Up and Resets
Stage 3: Device A Receives Idle Sequence
Stage 4: Normal Operation
Link Bring Up—BASE-KR
Using the Configuration Vector for Link Bring-Up
Using the MDIO interface for Link Bring-Up
What Can Cause Block Lock to Fail?
What Can Cause the 10Gb PCS/PMA Core to Insert Errors?
Transceiver Specific Checks
Link Training
Appx. C: Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices
10 Gigabit Ethernet
Subsystem v3.1
LogiCORE IP Product Guide
Vivado Design Suite
PG157 October 4, 2017
Table of Contents
Chapter 1: Overview
Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Unsupported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 2: Product Specification
Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Chapter 3: Designing with the Subsystem
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
7 Series Clocking and Shared Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
UltraScale Device Clocking and Shared Logic Using the RX Elastic Buffer . . . . . . . . . . . . . . . . . . . . 92
UltraScale Device Clocking and Shared Logic Omitting the RX Elastic Buffer . . . . . . . . . . . . . . . . . 97
Shared Logic for 7 Series IEEE 1588 Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Ethernet Protocol Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Connecting the Data Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
IEEE 1588 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Connecting the Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
IEEE 802.3 Flow Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Priority Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Receiver Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Special Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Chapter 4: Design Flow Steps
Customizing and Generating the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Constraining the Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
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Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 5: Example Design
Shared Logic and the Support Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Chapter 6: Test Bench
Appendix A: Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Appendix B: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Hardware Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
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IP Facts
Facts Table
Subsystem Specifics
10GBASE-R: UltraScale™
Zynq®-7000 All Programmable SoC
Virtex®-7, Kintex®-7(3)
10GBASE-KR: UltraScale™,
Virtex-7(4)
AXI4-Lite, AXI4-Stream
Performance and Resource Utilization web page
Provided with Subsystem
Encrypted RTL
Verilog
Verilog
Xilinx Design Constraint (XDC)
Verilog or VHDL source HDL Model
Linux
Supported
Device
Family(1) (2)
Supported User
Interfaces
Resources
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
S/W Driver
Tested Design Flows(5)
Design Entry
Simulation
Synthesis
Vivado® Design Suite
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide.
Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog. For new designs in the UltraScale/
UltraScale+™ portfolio, see the 10G/25G Ethernet Subsystem
webpage.
2. For the listed 7 series families, only a -2 speed grade or faster
is supported.
3. -2, -2L or -3.
4. GTHE2 transceivers only.
5. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.
‘‘
Introduction
The 10 Gigabit Ethernet subsytem provides a
10 Gigabit Ethernet MAC and PCS/PMA in
10GBASE-R/KR modes to provide a 10 Gigabit
Ethernet port. The transmit and receive data
interfaces use AXI4-Stream interfaces. An
optional AXI4-Lite interface is used for the
control interface to internal registers.
Features
• Designed to 10 Gigabit Ethernet specification
IEEE Standard 802.3-2012
• AXI4-Stream protocol support on client TX
and RX interfaces. 64-bit AXI4-Stream is
available for all permutations. For
10GBASE-R in supported devices, 32-bit
AXI4-Stream is available to provide lower
latency and utilization.
•
• Configured and monitored through an
optional AXI4-Lite Management Data
interface or using status and configuration
vectors
Supports 10GBASE-SR, -LR and -ER optical
links in Zynq-7000, UltraScale™, Virtex-7,
and Kintex-7 devices (LAN mode only)
Supports 10GBASE-KR backplane
linksincluding Auto-Negotiation (AN),
Training and Forward Error Correction (FEC)
Supports Deficit Idle Count
•
•
• Comprehensive statistics gathering
•
•
• Custom Preamble mode
•
Supports 802.3 and 802.1Qbb flow control
Supports VLAN and jumbo frames
Independent TX and RX Maximum
Transmission Unit (MTU) frame length
Supports high accuracy IEEE Standard
1588-2008 1-step and 2-step timestamping
on a 10GBASE-R network interface
•
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Chapter 1
Overview
The 10G Ethernet subsystem provides 10 Gb/s Ethernet MAC, Physical Coding Sublayer
(PCS) and Physical Medium Attachment (PMA) transmit and receive functionality over an
AXI4-Stream interface. The subsystem is designed to interface with a 10GBASE-R
Physical-Side Interface (PHY) or a 10GBASE-KR backplane and is designed to the IEEE
Standard 802.3-2012, Carrier Sense Multiple Access with Collision Detection (CSMA/CD)
Access Method and Physical Layer Specifications (IEEE Std 802.3) [Ref 1].
The 10GBASE-KR subsystem is distinguished from the 10GBASE-R subsystem by the
addition of a Link Training block as well as optional Auto-Negotiation (AN) and Forward
Error Correction (FEC) features, to support a 10 Gb/s data stream across a backplane.
The subsystem also provides an optional high accuracy timestamping capability compatible
with IEEE Std 1588-2008 (also known as IEEE1588v2). This is available for the 10GBASE-R
standard. Figure 1-1 shows the block diagram of the 10G Ethernet MAC subsystem.
X-Ref Target - Figure 1-1
Optional AXI4-Lite
Management
Interface
AXI4-Stream
10 Gigabit Ethernet
MAC
Internal
XGMII
10 Gigabit Ethernet
PCS/PMA
(10GBASE-R or
10GBASE-KR)
Serial
Timer Sync
(optional for 1588)
Timer Sync
(optional for 1588)
System Timer
X13598
Figure 1-1:
10G Ethernet MAC Block Diagram
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Chapter 1: Overview
10G Ethernet MAC
X-Ref Target - Figure 1-2
Figure 1-2:
10G Ethernet MAC Block Diagram
Figure 1-2 illustrates the 10G Ethernet MAC block diagram. The major functional blocks
include the following:
•
•
•
•
Transmit Engine which formats the frame and interframe gap
Receive Engine which decodes frames and performs error checking on them
Flow Control, either 802.3 legacy mode or 802.1Qbb priority flow control
Reconciliation Sublayer which interfaces the MAC to the connected
10GBASE-R/10GBASE-KR core
• Optional Management Block which provides an AXI4-Lite interface for configuration,
access to internal statistical counters, and to the MDIO registers of the connected
10GBASE-R/10GBASE-KR core
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Chapter 1: Overview
10GBASE-R
For Zynq®-7000, UltraScale™, Virtex®-7, and Kintex®-7 devices, all of the PCS and
management blocks illustrated are implemented in logic, except for part of the Gearbox and
SERDES. Figure 1-3 shows the architecture.
X-Ref Target - Figure 1-3
Elastic
Buffer
64b66b
Decode
10-
Gigabit
Ethernet
MAC
PCS
64b66b
Encode
XGMII (SDR)
Fabric
Test
Pattern
Check
Test
Pattern
Generate
MDIO
GT
Descramble
Block
Sync
rxn,p
BER Mon
SERDES
Scramble
Phase
FIFO
Gearbox
txn,p
Control
+
Status
PCS/PMA
Registers
X12649
Figure 1-3:
10GBASE-R Block Diagram
The major functional blocks include the following:
•
•
•
Transmit path, including scrambler, 64b/66b encoder and Gearbox
Receive path, including block synchronization, descrambler, decoder and BER (Bit Error
Rate) monitor
Elastic buffer in the receive datapath.
The elastic buffer is 32 words deep (1 word = 64bits data + 8 control). If the buffer
empties, local fault codes are inserted instead of data. This allows you to collect up to 64
clock correction (CC) sequences before the buffer overflows (and words are dropped).
The buffer normally fills up to one half and then deletes CC sequences when over half
full, and inserts CC sequences when under one half full. So from a half-full state, you can
(conservatively) accept an extra 360 KB of data (that is, receiving at +200 ppm) without
dropping any. From a half-full state you can cope with another 360 KB of data without
inserting local faults (for –200 ppm).
Test pattern generation and checking
Serial interface to optics
•
•
• Management registers (PCS/PMA) with optional MDIO interface
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Chapter 1: Overview
10GBASE-KR
Figure 1-4 illustrates a block diagram of the 10GBASE-KR implementation. The major
functional blocks include the following:
•
•
•
Transmit path, including scrambler, 64b/66b encoder, FEC, AN and Training
Receive path, including block synchronization, descrambler, decoder and BER (Bit Error
Rate) monitor, FEC, AN and Training
Elastic buffer in the receive datapath.
The elastic buffer is 32 words deep (1 word = 64bits data + 8 control). If the buffer
empties, local fault codes are inserted instead of data. This allows you to collect up to 64
clock correction (CC) sequences before the buffer overflows (and words are dropped).
The buffer normally fills up to one half and then deletes CC sequences when over half
full, and inserts CC sequences when under one half full. So from a half-full state, you can
(conservatively) accept an extra 360 KB of data (that is, receiving at +200 ppm) without
dropping any. From a half-full state you can cope with another 360 KB of data without
inserting local faults (for –200 ppm).
Test pattern generation and checking
Serial interface to backplane connector
•
•
• Management registers (PCS/PMA) with optional MDIO interface
X-Ref Target - Figure 1-4
10-Gigabit
Ethernet
MAC
Elastic
Buffer
Fabric
GT
PCS
FEC
AN
TRAIN
SERDES
rxn,p
txn,p
XGMII
(SDR)
MDIO
Control
+
Status
PCS/PMA
Registers
Figure 1-4: BASE-KR Block Diagram
Feature Summary
The subsystem performs the Link function of the Ethernet standard. The subsystem
supports both 802.3 and, optionally, 802.1Qbb (priority-based) flow control in both
10Gb Ethernet v3.1
PG157 October 4, 2017
www.xilinx.com
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