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USB ULPI 协议.pdf
Introduction
General
Naming Convention
Acronyms and Terms
References
Generic Low Pin Interface
General
Signals
Protocol
Bus Ownership
Transferring Data
Aborting Data
UTMI+ Low Pin Interface
General
Signals
Block Diagram
ULPI PHY Wrapper
Crystal Oscillator and PLL
General Biasing
DrvVbusExternal and ExternalVbusIndicator
Power-On-Reset
Carkit Option
Modes
Power On and Reset
Interrupt Event Notification
Timing
Clock
Output Clock
Input Clock (optional)
Input Clock Jitter
Control and Data
4-bit Data Clocking (optional)
Synchronous Mode
ULPI Command Bytes
Transmit Command Byte (TX CMD)
Receive Command Byte (RX CMD)
When to send an RX CMD
USB Packets
USB Data Transmit (NOPID)
USB Packet Transmit (PID)
USB Transmit Error
USB Packet Receive
USB Receive Error
USB Packet Timing
USB Inter-packet delay and Packet timeout
PHY Pipeline Delays
Link Decision Time
Inter-packet Timing Diagrams
Register Operations
Immediate Register Read and Write
Immediate Register Read and Write Aborted by USB Receive
Back-to-back Immediate Register Read/Write and USB Receive
Extended Register Read and Write
Extended Register Read aborted by and back-to-back with USB Receive
Aborting ULPI Transfers
Link aborted by PHY
PHY aborted by Link
USB Operations
Hi-Speed Detection Handshake (Chirp)
Preamble
USB Suspend and Resume
Low Speed Suspend and Resume
Full Speed Suspend and Resume
Hi-Speed Suspend and Resume
Remote Wake-up
Low Speed Remote Wake-up
Full Speed Remote Wake-up
Hi-Speed Remote Wake-up
AutoResume
Peripheral Connect and Disconnect Detection
No SYNC and EOP Generation (OpMode 11b) (Optional)
Vbus Power Control (internal and external)
OTG Operations
Session Request Protocol (SRP)
Host Negotiation Protocol (HNP) (Optional)
VBUS Comparator Thresholds
Threshold Range
Typical Application
RxCmd VBUS Valid source
SessEnd
Low Power Mode
Data Line Definition For Low Power Mode
Entering Low Power Mode
Exiting Low Power Mode
False Resume Rejection
Full Speed / Low Speed Serial Mode (Optional)
Data Line Definition For FsLsSerialMode
Entering FsLsSerialMode
Exiting FsLsSerialMode
Carkit Mode (Optional)
Safeguarding PHY Input Signals
Registers
Register Map
Immediate Register Set
Vendor ID and Product ID
Function Control
Interface Control
OTG Control
USB Interrupt Enable Rising
USB Interrupt Enable Falling
USB Interrupt Status
USB Interrupt Latch
Debug
Scratch Register
Carkit Control
Carkit Interrupt Delay
Carkit Interrupt Enable
Carkit Interrupt Status
Carkit Interrupt Latch
Carkit Pulse Control
Transmit Positive Width
Transmit Negative Width
Receive Polarity Recovery
Reserved
Access Extended Register Set
Vendor-specific
Extended Register Set
Register Settings for all Upstream and Downstream signalling modes
T&MT Connector
General
Daughter-card (UUT) Specification
UTMI+ Low Pin Interface (ULPI)
Specification
Revision 1.1
October 20, 2004
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
Revision History
Revision
Issue Date
0.9
1.0rc1
November 12, 2003
January 3, 2004
1.0rc2
January 13, 2004
1.0rc3
January 19, 2004
Comment
Pre-release.
Introduce PHY interface “modes”.
Update interface timings. Clarify 4-bit data clocking.
Clarify sending of RX CMD’s and interrupts.
Introduce AutoResume feature.
Route int pin to data(3) during 6-pin Serial Mode.
Explain VBUS thresholds.
Add T&MT diagram and updated text.
Add new section to explain how PHY is aborted by Link.
Various clarifications.
Add block diagram.
Tighten interface timing.
Modify suspend protocol to more closely resemble UTMI.
Add SPKR_L and SPKR_MIC to signal list and T&MT
connector.
Various clarifications.
Specify that PHY must send RX CMD after Reset.
Link + PHY clock startup time of no more than 5.6ms for a
peripheral is now mandatory.
PHY output delay reduced from 10ns to 9ns.
Added link decision time numbers for low speed.
Various Clarifications.
1.0
February 2, 2004
1.0rc3 adopted as 1.0 release.
1.1rc1
September 1, 2004
Various clarifications and fixes to hold time numbers, sending
RXCMDs, FsLsSerialMode, Vbus control and monitoring,
Test_J and Tesk_K signalling, Low Power Mode,
Hostdisconnect, ID detection, HS SOF packets, interrupts,
Carkit Mode, interface protection, No SYNC/EOP mode,
linestate filtering, and AutoResume.
1.1rc2
1.1
October 4, 2004
Re-arranged text in section 3.8.7.3. Updated contributors list.
October 20, 2004
1.1rc2 adopted as 1.1 release.
The present Specification has been circulated for the sole benefit of legally-recognized Promoters,
Adopters and Contributors of the Specification. All rights are expressly reserved, including but not
limited to intellectual property rights under patents, trademarks, copyrights and trade secrets. The
respective Promoter's, Adopter's or Contributor's agreement entered into by Promoters, Adopters
and Contributors sets forth their conditions of use of the Specification.
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UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
Philips
Philips
TransDimension
Cypress
ARC
ARC
Philips
Philips
Philips
Philips
TransDimension
SMSC
Philips
Conexant
Synopsys
Conexant
TransDimension
Motorola
Mentor
TransDimension
Philips
Mentor
Promoters
ARC International Inc.
Conexant Systems, Inc.
Mentor Graphics Corporation
Philips
SMSC
TransDimension, Inc.
Contributors
Bart Vertenten
Batuhan Okur
Bill Anderson
Bill McInerney
Brian Booker
Chris Belanger
Chris Kolb
Chris Schell
Chung Wing Yan
Dave Sroka
David Wang
David Wooten
Eric Kawamoto
Farran Mackay
Frank Frazier
Fred Roberts
Hassan Farooq
Hyun Lee
Ian Parr
Jay Standiford
Jerome Tjia
Mark Saunders
Mohamed Benromdhane Conexant
Morgan Monks
Nabil Takla
Peter Tengstrand
Ramanand Mandayam
Rob Douglas
Saleem Mohamed
Shaun Reemeyer
Simon Nguyen
Subramanyam Sankaran Philips
Sue Vining
Terry Remple
Timothy Chen
Vincent Chang
Questions should be emailed to lpcwg@boardrooms.org.
Mentor
Synopsys
Philips (Author)
Cypress
Qualcomm
Conexant
Conexant
SMSC
ISI
ARC
Conexant
Texas Instruments
iii
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
Table of Contents
1.
Introduction..............................................................................................................................................1
1.1 General...........................................................................................................................................1
1.2 Naming Convention........................................................................................................................1
1.3 Acronyms and Terms .....................................................................................................................1
1.4 References .....................................................................................................................................1
2. Generic Low Pin Interface ......................................................................................................................2
2.1 General...........................................................................................................................................2
2.2 Signals............................................................................................................................................2
2.3 Protocol ..........................................................................................................................................3
2.3.1 Bus Ownership..................................................................................................................3
2.3.2 Transferring Data ..............................................................................................................3
2.3.3 Aborting Data ....................................................................................................................4
3. UTMI+ Low Pin Interface.........................................................................................................................5
3.1 General...........................................................................................................................................5
3.2 Signals............................................................................................................................................6
3.3 Block Diagram ................................................................................................................................7
3.4 Modes.............................................................................................................................................9
3.5 Power On and Reset....................................................................................................................10
3.6
Interrupt Event Notification...........................................................................................................10
3.7 Timing...........................................................................................................................................11
3.7.1 Clock ...............................................................................................................................11
3.7.2 Control and Data .............................................................................................................13
3.8 Synchronous Mode ......................................................................................................................15
3.8.1 ULPI Command Bytes.....................................................................................................15
3.8.2 USB Packets ...................................................................................................................18
3.8.3 Register Operations ........................................................................................................30
3.8.4 Aborting ULPI Transfers..................................................................................................37
3.8.5 USB Operations ..............................................................................................................39
3.8.6 Vbus Power Control (internal and external)....................................................................52
3.8.7 OTG Operations..............................................................................................................52
Low Power Mode..........................................................................................................................55
3.9.1 Data Line Definition For Low Power Mode .....................................................................55
3.9.2 Entering Low Power Mode ..............................................................................................55
3.9.3 Exiting Low Power Mode.................................................................................................56
3.9.4 False Resume Rejection .................................................................................................57
3.10 Full Speed / Low Speed Serial Mode (Optional)..........................................................................58
3.10.1 Data Line Definition For FsLsSerialMode .......................................................................58
3.10.2 Entering FsLsSerialMode................................................................................................59
3.10.3 Exiting FsLsSerialMode ..................................................................................................60
3.11 Carkit Mode (Optional) .................................................................................................................61
3.12 Safeguarding PHY Input Signals..................................................................................................62
4. Registers ................................................................................................................................................65
4.1 Register Map ................................................................................................................................65
Immediate Register Set................................................................................................................67
4.2
4.2.1 Vendor ID and Product ID ...............................................................................................67
4.2.2 Function Control..............................................................................................................68
4.2.3
Interface Control..............................................................................................................69
4.2.4 OTG Control ....................................................................................................................71
4.2.5 USB Interrupt Enable Rising ...........................................................................................72
4.2.6 USB Interrupt Enable Falling...........................................................................................73
4.2.7 USB Interrupt Status .......................................................................................................74
4.2.8 USB Interrupt Latch.........................................................................................................75
4.2.9 Debug..............................................................................................................................76
4.2.10 Scratch Register..............................................................................................................76
4.2.11 Carkit Control ..................................................................................................................77
4.2.12 Carkit Interrupt Delay ......................................................................................................77
3.9
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UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
4.2.13 Carkit Interrupt Enable ....................................................................................................78
4.2.14 Carkit Interrupt Status .....................................................................................................78
4.2.15 Carkit Interrupt Latch.......................................................................................................79
4.2.16 Carkit Pulse Control ........................................................................................................79
4.2.17 Transmit Positive Width ..................................................................................................80
4.2.18 Transmit Negative Width.................................................................................................80
4.2.19 Receive Polarity Recovery ..............................................................................................80
4.2.20 Reserved .........................................................................................................................81
4.2.21 Access Extended Register Set........................................................................................81
4.2.22 Vendor-specific................................................................................................................81
4.3 Extended Register Set .................................................................................................................81
4.4 Register Settings for all Upstream and Downstream signalling modes.......................................81
5. T&MT Connector ...................................................................................................................................83
5.1 General.........................................................................................................................................83
5.2 Daughter-card (UUT) Specification..............................................................................................83
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UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
Figures
Figure 1 – LPI generic data bus ownership......................................................................................................3
Figure 2 – LPI generic data transmit followed by data receive ........................................................................3
Figure 3 – Link asserts stp to halt receive data................................................................................................4
Figure 4 – Creating a ULPI system using wrappers.........................................................................................5
Figure 5 – Block diagram of ULPI PHY............................................................................................................7
Figure 6 – Jitter measurement planes............................................................................................................12
Figure 7 – ULPI timing diagram......................................................................................................................13
Figure 8 – Clocking of 4-bit data interface compared to 8-bit interface .........................................................14
Figure 9 – Sending of RX CMD......................................................................................................................17
Figure 10 – USB data transmit (NOPID) ........................................................................................................18
Figure 11 – USB data transmit (PID)..............................................................................................................19
Figure 12 – PHY drives an RX CMD to indicate EOP (FS/LS LineState timing not to scale)........................20
Figure 13 – Forcing a full/low speed USB transmit error (timing not to scale)...............................................21
Figure 14 – USB receive while dir was previously low...................................................................................22
Figure 15 – USB receive while dir was previously high .................................................................................23
Figure 16 – USB receive error detected mid-packet......................................................................................24
Figure 17 – USB receive error during the last byte ........................................................................................25
Figure 18 – USB HS, FS, and LS bit lengths with respect to clock................................................................26
Figure 19 – HS transmit-to-transmit packet timing.........................................................................................29
Figure 20 – HS receive-to-transmit packet timing. .........................................................................................29
Figure 21 – Register write ..............................................................................................................................30
Figure 22 – Register read...............................................................................................................................31
Figure 23 – Register read or write aborted by USB receive during TX CMD byte.........................................31
Figure 24 – Register read turnaround cycle or Register write data cycle aborted by USB receive...............32
Figure 25 – USB receive in same cycle as register read data. USB receive is delayed................................33
Figure 26 – Register read followed immediately by a USB receive ...............................................................33
Figure 27 – Register write followed immediately by a USB receive during stp assertion..............................34
Figure 28 – Register read followed by a USB receive ...................................................................................34
Figure 29 – Extended register write ...............................................................................................................35
Figure 30 – Extended register read................................................................................................................35
Figure 31 – Extended register read aborted by USB receive during extended address cycle ......................36
Figure 32 – PHY aborted by Link asserting stp. Link performs register write or USB transmit. ....................37
Figure 33 – PHY aborted by Link asserting stp. Link performs register read. ...............................................38
Figure 34 – Link aborts PHY. Link fails to drive a TX CMD. PHY re-asserts dir............................................38
Figure 35 – Hi-Speed Detection Handshake (Chirp) sequence (timing not to scale) ....................................40
Figure 36 – Preamble sequence (D+/D- timing not to scale).........................................................................41
Figure 37 – LS Suspend and Resume (timing not to scale) ..........................................................................43
Figure 38 – FS Suspend and Resume (timing not to scale) ..........................................................................44
Figure 39 – HS Suspend and Resume (timing not to scale)..........................................................................46
Figure 40 – Low Speed Remote Wake-Up from Low Power Mode (timing not to scale) ..............................47
Figure 41 – Full Speed Remote Wake-Up from Low Power Mode (timing not to scale) ...............................48
Figure 42 – Hi-Speed Remote Wake-Up from Low Power Mode (timing not to scale) .................................49
Figure 43 – Automatic resume signalling (timing not to scale) ......................................................................50
Figure 44 – USB packet transmit when OpMode is set to 11b. .....................................................................51
Figure 45 – RX CMD VA_VBUS_VLD ≤ Vbus indication source ........................................................................54
Figure 46 – Entering low power mode............................................................................................................55
Figure 47 – Exiting low power mode when PHY provides output clock.........................................................56
Figure 48 – Exiting low power mode when Link provides input clock............................................................56
Figure 49 – PHY stays in Low Power Mode when stp de-asserts before clock starts...................................57
Figure 50 – PHY re-enters Low Power Mode when stp de-asserts before dir de-asserts.............................57
Figure 51 – Interface behaviour when entering Serial Mode and clock is powered down.............................59
Figure 52 – Interface behaviour when entering Serial Mode and clock remains powered............................59
Figure 53 – Interface behaviour when exiting Serial Mode and clock is not running.....................................60
Figure 54 – Interface behaviour when exiting Serial Mode and clock is running...........................................60
Figure 55 – PHY interface protected when the clock is running ....................................................................62
Figure 56 – Power up sequence when PHY powers up before the link. Interface is protected.....................63
Figure 57 – PHY automatically exits Low Power Mode with interface protected...........................................63
Figure 58 – Link resumes driving ULPI bus and asserts stp because clock is not running...........................64
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UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
Figure 59 – Power up sequence when link powers up before PHY (ULPI 1.0 compliant links) ....................64
Figure 60 – Recommended daughter-card configuration (not to scale) ........................................................83
vii
UTMI+ Low Pin Interface Specification, Revision 1.1
October 20, 2004
Tables
Table 1 – LPI generic interface signals ............................................................................................................2
Table 2 – PHY interface signals .......................................................................................................................6
Table 3 – Mode summary.................................................................................................................................9
Table 4 – Clock timing parameters.................................................................................................................11
Table 5 – ULPI interface timing ......................................................................................................................13
Table 6 – Transmit Command (TX CMD) byte format ...................................................................................15
Table 7 – Receive Command (RX CMD) byte format....................................................................................16
Table 8 – USB specification inter-packet timings...........................................................................................26
Table 9 – PHY pipeline delays .......................................................................................................................27
Table 10 – Link decision times .......................................................................................................................28
Table 11 – OTG Control Register power control bits .....................................................................................52
Table 12 – Vbus comparator thresholds ........................................................................................................52
Table 13 – RX CMD VbusValid over-current conditions ................................................................................53
Table 14 – Vbus indicators in the RX CMD required for typical applications.................................................54
Table 15 – Interface signal mapping during Low Power Mode ......................................................................55
Table 16 – Serial Mode signal mapping for 6-pin FsLsSerialMode ...............................................................58
Table 17 – Serial Mode signal mapping for 3-pin FsLsSerialMode ...............................................................58
Table 18 – Carkit signal mapping...................................................................................................................61
Table 19 – Register map ................................................................................................................................66
Table 20 – Register access legend................................................................................................................67
Table 21 – Vendor ID and Product ID register description ............................................................................67
Table 22 – Function Control register..............................................................................................................68
Table 23 – Interface Control register..............................................................................................................70
Table 24 – OTG Control register ....................................................................................................................71
Table 25 – USB Interrupt Enable Rising register ...........................................................................................72
Table 26 – USB Interrupt Enable Falling register...........................................................................................73
Table 27 – USB Interrupt Status register .......................................................................................................74
Table 28 – USB Interrupt Latch register.........................................................................................................75
Table 29 – Rules for setting Interrupt Latch register bits ...............................................................................75
Table 30 – Debug register..............................................................................................................................76
Table 31 – Scratch register ............................................................................................................................76
Table 32 – Carkit Control Register .................................................................................................................77
Table 33 – Carkit Interrupt Delay register ......................................................................................................77
Table 34 – Carkit Interrupt Enable register ....................................................................................................78
Table 35 – Carkit Interrupt Status Register....................................................................................................78
Table 36 – Carkit Interrupt Latch register.......................................................................................................79
Table 37 – Carkit Pulse Control .....................................................................................................................79
Table 38 – Transmit Positive Width................................................................................................................80
Table 39 – Transmit Negative Width ..............................................................................................................80
Table 40 – Receive Polarity Recovery ...........................................................................................................81
Table 41 – Upstream and downstream signalling modes ..............................................................................82
Table 42 – T&MT connector pin view.............................................................................................................84
Table 43 – T&MT connector pin allocation.....................................................................................................84
Table 44 – T&MT pin description ...................................................................................................................85
viii
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