Revision History
Section 1 Introduction
1.1 Introduction
1.2 Features
1.3 Block Diagram
Section 2 Signal Description
2.1 Introduction
2.2 Package Pinout Summary
2.2.1 Signal Properties Summary
2.3 Signal Descriptions
2.3.1 Reset Signals
2.3.1.1 Power-On Reset In ( por)
2.3.2 Edge Port Signals
2.3.2.1 gint[1]/gint[3]
2.3.3 SD Signals
2.3.3.1 SD clock (sd_clk)
2.3.3.2 SD Command/Response (sd_cmd)
2.3.3.3 SD data (sd_dat[3:0])
2.3.4 USI Signals(USI1)
2.3.4.1 Smart Card Data Input/Output (isodat)
2.3.4.2 Smart Card Clock Signal (isoclk)
2.3.4.3 Smart Card Reset Signal (isorst)
2.3.5 Serial Peripheral Interface Module(SPI1/3)
2.3.5.1 Master Out/Slave In (mosi1)
2.3.5.2 Master In/Slave Out (miso1)
2.3.5.3 Serial Clock (sck1)
2.3.5.4 Slave Select (ss1)
2.3.6 Power Control
2.3.6.1 VCCQWKx
2.3.7 SWP IO
2.3.7.1 swio
2.3.8 Power and Ground Signals
2.3.8.1 VCCQ
2.3.8.2 VCC
2.3.8.3 VSS
2.3.8.4 VDD(1.1V)
2.3.8.5 VDD1P8V(1.8V)
2.3.8.6 VCC_SDIO(3.3/1.8V)
Section 3 System Memory Map
3.1 Introduction
3.2 Address Map
Appendix A Preliminary Electrical Characteristic
A.1 General
A.2 Absolute Maximum Ratings
A.3 Electrostatic Discharge (ESD) Protection
A.4 DC Electrical Specifications
Appendix B Production Parameters
B.1 General
B.2 POD of Package QFN32
B.3 Device Marking Information
B.3.1 Part Marking
B.3.2 Part Marking Line Descriptions
B.4 Package Reliability
B.5 Packing For Shippment
B.5.1 Carrier Tape
B.5.2 REEL
B.5.3 Inner Carton
B.5.4 Outer Carton
B.6 Storage Condition
B.7 SMT Jointing Temperature
B.8 Layout solder paste package Description
Appendix C Circuit principium
C.1 Referenced Design Diagram
C.2 Notice
Appendix D Chip Power Consumption
D.1 Chip Static and Dynamic Power Consumption