MT41J128M16HA-15E.pdf

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Automotive DDR3 SDRAM

Features

FBGA Part Marking Decoder

State Diagram

Functional Description

Automotive Industrial Temperature

Automotive Temperature

General Notes

Functional Block Diagrams

Ball Assignments and Descriptions

Package Dimensions

Electrical Specifications

Absolute Ratings

Input/Output Capacitance

Thermal Characteristics

Electrical Specifications – IDD Specifications and Conditions

Electrical Characteristics – IDD Specifications

Electrical Specifications – DC and AC

DC Operating Conditions

Input Operating Conditions

AC Overshoot/Undershoot Specification

Slew Rate Definitions for Single-Ended Input Signals

Slew Rate Definitions for Differential Input Signals

ODT Characteristics

ODT Resistors

ODT Sensitivity

ODT Timing Definitions

Output Driver Impedance

34 Ohm Output Driver Impedance

34 Ohm Driver

34 Ohm Output Driver Sensitivity

Alternative 40 Ohm Driver

40 Ohm Output Driver Sensitivity

Output Characteristics and Operating Conditions

Reference Output Load

Slew Rate Definitions for Single-Ended Output Signals

Slew Rate Definitions for Differential Output Signals

Speed Bin Tables

Electrical Characteristics and AC Operating Conditions

Command and Address Setup, Hold, and Derating

Data Setup, Hold, and Derating

Commands – Truth Tables

Commands

DESELECT

NO OPERATION

ZQ CALIBRATION LONG

ZQ CALIBRATION SHORT

ACTIVATE

READ

WRITE

PRECHARGE

REFRESH

SELF REFRESH

DLL Disable Mode

Input Clock Frequency Change

Write Leveling

Write Leveling Procedure

Write Leveling Mode Exit Procedure

Initialization

Mode Registers

Mode Register 0 (MR0)

Burst Length

Burst Type

DLL RESET

Write Recovery

Precharge Power-Down (Precharge PD)

CAS Latency (CL)

Mode Register 1 (MR1)

DLL ENABLE/DISABLE

Output Drive Strength

OUTPUT ENABLE/DISABLE

TDQS ENABLE

On-Die Termination (ODT)

WRITE LEVELING

Posted CAS Additive Latency (AL)

Mode Register 2 (MR2)

CAS WRITE Latency (CWL)

AUTO SELF REFRESH (ASR)

SELF REFRESH TEMPERATURE (SRT)

SRT versus ASR

Dynamic On-Die Termination (ODT)

Mode Register 3 (MR3)

MULTIPURPOSE REGISTER (MPR)

MPR Functional Description

MPR Address Definitions and Bursting Order

MPR Read Predefined Pattern

MODE REGISTER SET (MRS) Command

ZQ CALIBRATION Operation

ACTIVATE Operation

READ Operation

WRITE Operation

DQ Input Timing

PRECHARGE Operation

SELF REFRESH Operation

Extended Temperature Usage

Power-Down Mode

RESET Operation

On-Die Termination (ODT)

Functional Representation of ODT

Nominal ODT

Dynamic ODT

Dynamic ODT Special Use Case

Functional Description

Synchronous ODT Mode

ODT Latency and Posted ODT

Timing Parameters

ODT Off During READs

Asynchronous ODT Mode

Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry)

Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit)

Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)

2Gb: x8, x16 Automotive DDR3 SDRAM Features Automotive DDR3 SDRAM MT41J256M8 – 32 Meg x 8 x 8 Banks MT41J128M16 – 16 Meg x 16 x 8 Banks Options1 • Configuration – 256 Meg x 8 – 128 Meg x 16 • FBGA package (Pb-free) – x8 – 78-ball (9mm x 11.5mm) Rev. D • FBGA package (Pb-free) – x16 – 96-ball (9mm x 14mm) Rev. D • Timing – cycle time – 1.07ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) • Operating temperature – Industrial (–40°C ≤ TC ≤ +95°C) – Automotive (–40°C ≤ TC ≤ +105°C) • Revision Marking 256M8 128M16 HX HA -107 -125 -15E -187E AIT AAT :D Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Features • Industrial and automotive temperature compliant • VDD = VDDQ = 1.5V ±0.075V • 1.5V center-terminated push/pull I/O • Differential bidirectional data strobe • 8n-bit prefetch architecture • Differential clock inputs (CK, CK#) • 8 internal banks • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Programmable CAS READ latency (CL) • Posted CAS additive latency (AL) • Programmable CAS WRITE latency (CWL) based on tCK • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • TC of –40°C to +95°C/+105°C – 64ms, 8192 cycle refresh at 0°C to +85°C – 32ms, 8192 cycle refresh at +85°C to +95°C/ +105°C • Self refresh temperature (SRT) • Write leveling • Multipurpose register • Output driver calibration • AEC-Q100 • PPAP submission • 8D response time Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL tRCD (ns) tRP (ns) -1071, 2 -1251, 2 -15E1 -187E 1866 1600 1333 1066 13-13-13 11-11-11 9-9-9 7-7-7 13.91 13.75 13.5 13.1 13.91 13.75 13.5 13.1 CL (ns) 13.91 13.75 13.5 13.1 Notes: 1. Backward compatible to 1066, CL = 7 (-187E). 2. Backward compatible to 1333, CL = 9 (-15E). PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN Products and specifications discussed herein are subject to change by Micron without notice. 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features Table 2: Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Page size Figure 1: DDR3 Part Numbers 256 Meg x 8 32 Meg x 8 x 8 banks 128 Meg x 16 16 Meg x 16 x 8 banks 8K 32K (A[14:0]) 8 (BA[2:0]) 1K (A[9:0]) 1KB 8K 16K (A[13:0]) 8 (BA[2:0]) 1K (A[9:0]) 2KB Example Part Number: MT41J256M8JE-15:M MT41J Configuration Package Speed Revision - : Configuration 256 Meg x 8 128 Meg x 16 256M8 128M16 { :D Revision Temperature Automotive Industrial temperature Automotive temperature AIT AAIT Package 78-ball 9mm x 11.5mm FBGA 96-ball 9mm x 14mm FBGA HX HA -107 -125 -15E -187E Speed Grade tCK = 1.07ns, CL = 13 tCK = 1.25ns, CL = 11 tCK = 1.5ns, CL = 9 tCK = 1.87ns, CL = 7 Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features Contents State Diagram ................................................................................................................................................ 11 Functional Description ................................................................................................................................... 12 Automotive Industrial Temperature ............................................................................................................. 12 Automotive Temperature ............................................................................................................................ 12 General Notes ............................................................................................................................................ 13 Functional Block Diagrams ............................................................................................................................. 14 Ball Assignments and Descriptions ................................................................................................................. 16 Package Dimensions ....................................................................................................................................... 22 Electrical Specifications .................................................................................................................................. 24 Absolute Ratings ......................................................................................................................................... 24 Input/Output Capacitance .......................................................................................................................... 25 Thermal Characteristics .................................................................................................................................. 26 Electrical Specifications – IDD Specifications and Conditions ............................................................................ 27 Electrical Characteristics – IDD Specifications .................................................................................................. 38 Electrical Specifications – DC and AC .............................................................................................................. 40 DC Operating Conditions ........................................................................................................................... 40 Input Operating Conditions ........................................................................................................................ 40 AC Overshoot/Undershoot Specification ..................................................................................................... 43 Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 47 Slew Rate Definitions for Differential Input Signals ...................................................................................... 49 ODT Characteristics ....................................................................................................................................... 50 ODT Resistors ............................................................................................................................................ 50 ODT Sensitivity .......................................................................................................................................... 52 ODT Timing Definitions ............................................................................................................................. 52 Output Driver Impedance ............................................................................................................................... 56 34 Ohm Output Driver Impedance .............................................................................................................. 57 34 Ohm Driver ............................................................................................................................................ 58 34 Ohm Output Driver Sensitivity ................................................................................................................ 59 Alternative 40 Ohm Driver .......................................................................................................................... 60 40 Ohm Output Driver Sensitivity ................................................................................................................ 60 Output Characteristics and Operating Conditions ............................................................................................ 62 Reference Output Load ............................................................................................................................... 64 Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 65 Slew Rate Definitions for Differential Output Signals .................................................................................... 66 Speed Bin Tables ............................................................................................................................................ 67 Electrical Characteristics and AC Operating Conditions ................................................................................... 71 Command and Address Setup, Hold, and Derating ........................................................................................... 90 Data Setup, Hold, and Derating ....................................................................................................................... 98 Commands – Truth Tables ............................................................................................................................. 105 Commands ................................................................................................................................................... 108 DESELECT ................................................................................................................................................ 108 NO OPERATION ........................................................................................................................................ 108 ZQ CALIBRATION LONG ........................................................................................................................... 108 ZQ CALIBRATION SHORT .......................................................................................................................... 108 ACTIVATE ................................................................................................................................................. 108 READ ........................................................................................................................................................ 108 WRITE ...................................................................................................................................................... 109 PRECHARGE ............................................................................................................................................. 110 REFRESH .................................................................................................................................................. 110 SELF REFRESH .......................................................................................................................................... 111 PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features DLL Disable Mode ..................................................................................................................................... 112 Input Clock Frequency Change ...................................................................................................................... 116 Write Leveling ............................................................................................................................................... 118 Write Leveling Procedure ........................................................................................................................... 120 Write Leveling Mode Exit Procedure ........................................................................................................... 122 Initialization ................................................................................................................................................. 123 Mode Registers .............................................................................................................................................. 125 Mode Register 0 (MR0) ................................................................................................................................... 126 Burst Length ............................................................................................................................................. 126 Burst Type ................................................................................................................................................. 127 DLL RESET ................................................................................................................................................ 128 Write Recovery .......................................................................................................................................... 128 Precharge Power-Down (Precharge PD) ...................................................................................................... 129 CAS Latency (CL) ....................................................................................................................................... 129 Mode Register 1 (MR1) ................................................................................................................................... 130 DLL ENABLE/DISABLE .............................................................................................................................. 130 Output Drive Strength ............................................................................................................................... 131 OUTPUT ENABLE/DISABLE ...................................................................................................................... 131 TDQS ENABLE .......................................................................................................................................... 131 On-Die Termination (ODT) ........................................................................................................................ 132 WRITE LEVELING ..................................................................................................................................... 132 Posted CAS Additive Latency (AL) ............................................................................................................... 132 Mode Register 2 (MR2) ................................................................................................................................... 134 CAS WRITE Latency (CWL) ........................................................................................................................ 134 AUTO SELF REFRESH (ASR) ....................................................................................................................... 135 SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 135 SRT versus ASR .......................................................................................................................................... 136 Dynamic On-Die Termination (ODT) ......................................................................................................... 136 Mode Register 3 (MR3) ................................................................................................................................... 137 MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 137 MPR Functional Description ...................................................................................................................... 138 MPR Address Definitions and Bursting Order .............................................................................................. 139 MPR Read Predefined Pattern .................................................................................................................... 144 MODE REGISTER SET (MRS) Command ........................................................................................................ 144 ZQ CALIBRATION Operation ......................................................................................................................... 145 ACTIVATE Operation ..................................................................................................................................... 146 READ Operation ............................................................................................................................................ 148 WRITE Operation .......................................................................................................................................... 159 DQ Input Timing ....................................................................................................................................... 167 PRECHARGE Operation ................................................................................................................................. 169 SELF REFRESH Operation .............................................................................................................................. 169 Extended Temperature Usage ........................................................................................................................ 171 Power-Down Mode ........................................................................................................................................ 172 RESET Operation ........................................................................................................................................... 180 On-Die Termination (ODT) ............................................................................................................................ 182 Functional Representation of ODT ............................................................................................................. 182 Nominal ODT ............................................................................................................................................ 182 Dynamic ODT ............................................................................................................................................... 184 Dynamic ODT Special Use Case ................................................................................................................. 184 Functional Description .............................................................................................................................. 184 Synchronous ODT Mode ................................................................................................................................ 190 ODT Latency and Posted ODT .................................................................................................................... 190 PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features Timing Parameters .................................................................................................................................... 190 ODT Off During READs .............................................................................................................................. 193 Asynchronous ODT Mode .............................................................................................................................. 195 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 197 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 199 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 201 PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features List of Figures Figure 1: DDR3 Part Numbers .......................................................................................................................... 2 Figure 2: Simplified State Diagram ................................................................................................................. 11 Figure 3: 256 Meg x 8 Functional Block Diagram ............................................................................................. 14 Figure 4: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15 Figure 5: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16 Figure 6: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17 Figure 7: 78-Ball FBGA – x8 (HX) .................................................................................................................... 22 Figure 8: 96-Ball FBGA – x16 (HA) .................................................................................................................. 23 Figure 9: Thermal Measurement Point ........................................................................................................... 26 Figure 10: Input Signal .................................................................................................................................. 42 Figure 11: Overshoot ..................................................................................................................................... 43 Figure 12: Undershoot ................................................................................................................................... 43 Figure 13: VIX for Differential Signals .............................................................................................................. 45 Figure 14: Single-Ended Requirements for Differential Signals ........................................................................ 45 Figure 15: Definition of Differential AC-Swing and tDVAC ............................................................................... 46 Figure 16: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 48 Figure 17: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 49 Figure 18: ODT Levels and I-V Characteristics ................................................................................................ 50 Figure 19: ODT Timing Reference Load .......................................................................................................... 53 Figure 20: tAON and tAOF Definitions ............................................................................................................ 54 Figure 21: tAONPD and tAOFPD Definitions ................................................................................................... 54 Figure 22: tADC Definition ............................................................................................................................. 55 Figure 23: Output Driver ................................................................................................................................ 56 Figure 24: DQ Output Signal .......................................................................................................................... 63 Figure 25: Differential Output Signal .............................................................................................................. 64 Figure 26: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 64 Figure 27: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 65 Figure 28: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 66 Figure 29: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) .............................................. 94 Figure 30: Nominal Slew Rate for tIH (Command and Address – Clock) ............................................................ 95 Figure 31: Tangent Line for tIS (Command and Address – Clock) ..................................................................... 96 Figure 32: Tangent Line for tIH (Command and Address – Clock) ..................................................................... 97 Figure 33: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 101 Figure 34: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 102 Figure 35: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 103 Figure 36: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 104 Figure 37: Refresh Mode ............................................................................................................................... 111 Figure 38: DLL Enable Mode to DLL Disable Mode ........................................................................................ 113 Figure 39: DLL Disable Mode to DLL Enable Mode ........................................................................................ 114 Figure 40: DLL Disable tDQSCK .................................................................................................................... 115 Figure 41: Change Frequency During Precharge Power-Down ........................................................................ 117 Figure 42: Write Leveling Concept ................................................................................................................. 118 Figure 43: Write Leveling Sequence ............................................................................................................... 121 Figure 44: Write Leveling Exit Procedure ....................................................................................................... 122 Figure 45: Initialization Sequence ................................................................................................................. 124 Figure 46: MRS to MRS Command Timing (tMRD) ......................................................................................... 125 Figure 47: MRS to nonMRS Command Timing (tMOD) .................................................................................. 126 Figure 48: Mode Register 0 (MR0) Definitions ................................................................................................ 127 Figure 49: READ Latency .............................................................................................................................. 129 Figure 50: Mode Register 1 (MR1) Definition ................................................................................................. 130 PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features Figure 51: READ Latency (AL = 5, CL = 6) ....................................................................................................... 133 Figure 52: Mode Register 2 (MR2) Definition ................................................................................................. 134 Figure 53: CAS WRITE Latency ...................................................................................................................... 135 Figure 54: Mode Register 3 (MR3) Definition ................................................................................................. 137 Figure 55: MPR Block Diagram ...................................................................................................................... 138 Figure 56: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 140 Figure 57: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 141 Figure 58: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 142 Figure 59: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 143 Figure 60: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 145 Figure 61: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 146 Figure 62: Example: tFAW ............................................................................................................................. 147 Figure 63: READ Latency .............................................................................................................................. 148 Figure 64: Consecutive READ Bursts (BL8) .................................................................................................... 150 Figure 65: Consecutive READ Bursts (BC4) .................................................................................................... 150 Figure 66: Nonconsecutive READ Bursts ....................................................................................................... 151 Figure 67: READ (BL8) to WRITE (BL8) .......................................................................................................... 151 Figure 68: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 152 Figure 69: READ to PRECHARGE (BL8) .......................................................................................................... 152 Figure 70: READ to PRECHARGE (BC4) ......................................................................................................... 153 Figure 71: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 153 Figure 72: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 153 Figure 73: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 155 Figure 74: Data Strobe Timing – READs ......................................................................................................... 156 Figure 75: Method for Calculating tLZ and tHZ ............................................................................................... 157 Figure 76: tRPRE Timing ............................................................................................................................... 157 Figure 77: tRPST Timing ............................................................................................................................... 158 Figure 78: tWPRE Timing .............................................................................................................................. 160 Figure 79: tWPST Timing .............................................................................................................................. 160 Figure 80: WRITE Burst ................................................................................................................................ 161 Figure 81: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 162 Figure 82: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF ............................................................ 162 Figure 83: Nonconsecutive WRITE to WRITE ................................................................................................. 163 Figure 84: WRITE (BL8) to READ (BL8) .......................................................................................................... 163 Figure 85: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 164 Figure 86: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 165 Figure 87: WRITE (BL8) to PRECHARGE ........................................................................................................ 166 Figure 88: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 166 Figure 89: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 167 Figure 90: Data Input Timing ........................................................................................................................ 168 Figure 91: Self Refresh Entry/Exit Timing ...................................................................................................... 170 Figure 92: Active Power-Down Entry and Exit ................................................................................................ 174 Figure 93: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 175 Figure 94: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 175 Figure 95: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 176 Figure 96: Power-Down Entry After WRITE .................................................................................................... 176 Figure 97: Power-Down Entry After WRITE with Auto Precharge (WRAP) ........................................................ 177 Figure 98: REFRESH to Power-Down Entry .................................................................................................... 177 Figure 99: ACTIVATE to Power-Down Entry ................................................................................................... 178 Figure 100: PRECHARGE to Power-Down Entry ............................................................................................. 178 Figure 101: MRS Command to Power-Down Entry ......................................................................................... 179 Figure 102: Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 179 PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

2Gb: x8, x16 Automotive DDR3 SDRAM Features Figure 103: RESET Sequence ......................................................................................................................... 181 Figure 104: On-Die Termination ................................................................................................................... 182 Figure 105: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 187 Figure 106: Dynamic ODT: Without WRITE Command .................................................................................. 187 Figure 107: Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 188 Figure 108: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 189 Figure 109: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 189 Figure 110: Synchronous ODT ...................................................................................................................... 191 Figure 111: Synchronous ODT (BC4) ............................................................................................................. 192 Figure 112: ODT During READs .................................................................................................................... 194 Figure 113: Asynchronous ODT Timing with Fast ODT Transition .................................................................. 196 Figure 114: Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 198 Figure 115: Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 200 Figure 116: Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 202 Figure 117: Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 202 PDF: 09005aef84799800 2gb_ddr3_ait_aat_sdram.pdf – Rev. A 8/11 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2006 Micron Technology, Inc. All rights reserved.

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