xHCI_Specification_for_USB.pdf

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Table of Contents

Table of Figures

Table of Tables

1 Preface

1.1 Objective of Specification

1.2 Scope of Document

1.3 Document Organization

1.4 References

1.5 Index

1.6 Terms and Abbreviations

1.7 Documentation Conventions

1.7.1 Capitalization

1.7.2 Italic Text

1.7.3 Numbers and Number Bases

1.7.4 Implementation Notes

1.7.5 Word Usage

1.7.6 Pseudo Code

1.7.7 Other Notation

2 Introduction

2.1 Motivation

2.1.1 Goals

2.2 Key features

2.3 xHCI Product Compliance

3 Architectural Overview

3.1 Interface Architecture

3.2 xHCI Data Structures

3.2.1 Device Context Base Address Array

3.2.2 Device Context

3.2.3 Slot Context

3.2.4 Endpoint Context

3.2.4.1 Stream Context Array

3.2.4.1.1 Stream Context

3.2.5 Input Context

3.2.5.1 Input Control Context

3.2.6 Rings

3.2.6.1 Transfer Ring Example

3.2.7 Transfer Request Block

3.2.7.1 Operation

3.2.7.2 Other Rings

3.2.8 Scatter/Gather Transfers

3.2.9 Control Transfers

3.2.10 Bulk and Interrupt Transfers

3.2.11 Isoch Transfers

3.3 Command Interface

3.3.1 No Op

3.3.2 Enable Slot

3.3.3 Disable Slot

3.3.4 Address Device

3.3.5 Configure Endpoint

3.3.6 Evaluate Context

3.3.7 Reset Endpoint

3.3.8 Stop Endpoint

3.3.9 Set TR Dequeue Pointer

3.3.10 Reset Device

3.3.11 Force Event

3.3.12 Negotiate Bandwidth

3.3.13 Set Latency Tolerance Value

3.3.14 Get Port Bandwidth

3.3.15 Force Header

3.4 General Information

3.5 Root Hub Management

3.6 xHCI Device Enumeration

4 Operational Model

4.1 Command Operation

4.2 Host Controller Initialization

4.3 USB Device Initialization

4.3.1 Resetting a Root Hub Port

4.3.2 Device Slot Assignment

4.3.3 Device Slot Initialization

4.3.4 Address Assignment

4.3.5 Device Configuration

4.3.6 Setting Alternate Interfaces

4.3.7 Low-Speed/Full-Speed Device Support

4.3.8 Bandwidth Management

4.4 Device Detach

4.5 Device Slot Management

4.5.1 Device Context Index

4.5.2 Slot Context Initialization

4.5.3 Slot States

4.5.3.1 Device Slot State Codes

4.5.3.2 Disabled

4.5.3.3 Enabled

4.5.3.4 Default

4.5.3.5 Addressed

4.5.3.6 Configured

4.5.4 USB Standard Device Request to xHCI Command Mapping

4.5.4.1 SET_ADDRESS Request

4.5.4.2 SET_CONFIGURATION Request

4.5.4.3 SET_INTERFACE Request

4.6 Command Interface

4.6.1 Command Ring Operation

4.6.1.1 Stopping the Command Ring

4.6.1.2 Aborting a Command

4.6.2 No Op

4.6.3 Enable Slot

4.6.4 Disable Slot

4.6.5 Address Device

4.6.6 Configure Endpoint

4.6.7 Evaluate Context

4.6.8 Reset Endpoint

4.6.8.1 Soft Retry

4.6.9 Stop Endpoint

4.6.10 Set TR Dequeue Pointer

4.6.11 Reset Device

4.6.12 Force Event (Optional Normative)

4.6.13 Negotiate Bandwidth (Optional Normative)

4.6.14 Set Latency Tolerance Value (LTV) (Optional Normative)

4.6.15 Get Port Bandwidth

4.6.16 Force Header

4.7 Doorbells

4.8 Endpoint

4.8.1 Endpoint Addressing

4.8.2 Endpoint Context Initialization

4.8.2.1 Default Control Endpoint 0

4.8.2.2 Control Endpoints

4.8.2.3 Bulk Endpoints

4.8.2.4 Isoch or Interrupt Endpoints

4.8.3 Endpoint Context State

4.9 TRB Ring

4.9.1 Transfer Descriptors

4.9.2 Transfer Ring Management

4.9.2.1 Segmented Rings

4.9.2.2 Pointer Advancement

4.9.2.3 Enlarging a Transfer Ring

4.9.2.4 Shrinking a Transfer Ring

4.9.3 Command Ring Management

4.9.4 Event Ring Management

4.9.4.1 Changing the size of an Event Ring

4.9.4.2 Shrinking an Event Ring

4.9.4.3 Primary and Secondary Event Rings

4.10 Host Controller TRB Handling

4.10.1 Transfer TRBs

4.10.1.1 Short Transfers

4.10.2 Errors

4.10.2.1 Stall Error

4.10.2.1.1 Non-Control Endpoints

4.10.2.1.2 Control Endpoints

4.10.2.2 TRB Error

4.10.2.3 USB Transaction Error

4.10.2.4 Babble Detected Error

4.10.2.4.1 USB2 Protocol

4.10.2.4.2 USB3 Protocol

4.10.2.5 Data Buffer Error

4.10.2.6 Host System Errors

4.10.2.7 Bus Error Counter

4.10.2.8 Isoch Endpoint Error Handling

4.10.3 Events

4.10.3.1 Ring Overrun and Underrun

4.10.3.2 Missed Service Error

4.10.3.3 Split Transaction Error

4.10.3.4 Short Packet

4.11 TRBs

4.11.1 TRB Template

4.11.1.1 Command and Transfer TRB Components

4.11.1.2 Event TRB Components

4.11.2 Transfer TRBs

4.11.2.1 Normal TRB

4.11.2.2 Setup Stage, Data Stage, and Status Stage TRBs

4.11.2.3 Isoch TRB

4.11.2.4 TD Size

4.11.2.5 Frame ID

4.11.3 Event TRBs

4.11.3.1 Transfer Event TRB

4.11.4 Command TRBs

4.11.4.1 No Op Command TRB

4.11.4.2 Enable Slot Command TRB

4.11.4.3 Disable Slot Command TRB

4.11.4.4 Address Device Command TRB

4.11.4.5 Configure Endpoint Command TRB

4.11.4.6 Evaluate Context Command TRB

4.11.4.7 Reset Endpoint Command TRB

4.11.4.8 Stop Endpoint Command TRB

4.11.4.9 Set TR Dequeue Pointer Command TRB

4.11.4.10 Reset Device Command TRB

4.11.4.11 Force Event Command TRB (Optional Normative)

4.11.4.12 Negotiate Bandwidth Command TRB (Optional Normative)

4.11.4.13 Set Latency Tolerance Value Command TRB (Optional Normative)

4.11.4.14 Get Port Bandwidth Command TRB

4.11.4.15 Force Header Command TRB

4.11.5 Other TRBs

4.11.5.1 Link TRB

4.11.5.2 Event Data TRB

4.11.6 Vendor Defined TRB Types

4.11.7 TD Usage Rules

4.11.7.1 TD Fragments

4.12 Streams

4.12.1 xHCI Stream Protocol

4.12.1.1 Host Initiated Data Move

4.12.2 Stream ID Management

4.12.2.1 Stream Array Bounds Checking

4.12.3 Evaluate Next TRB (ENT)

4.13 Device Notifications

4.13.1 Latency Tolerance Message Handling

4.13.2 Function Wake

4.14 Managing Transfer Rings

4.14.1 General Scheduling Model

4.14.1.1 System Bus Bandwidth Scheduling

4.14.2 Periodic Transfer Ring Scheduling

4.14.2.1 Isochronous Transfer Ring Scheduling

4.14.2.1.1 High-speed endpoints

4.14.2.1.2 Full-speed or High-speed endpoints

4.14.2.1.3 SuperSpeed endpoints

4.14.2.1.4 Isochronous Scheduling Threshold

4.14.3 Interrupt Transfer Ring Scheduling

4.14.3.1 Low-, Full-, and High-speed Endpoints

4.14.3.2 SuperSpeed Endpoints

4.14.4 Asynchronous Transfer Ring Scheduling

4.14.4.1 SuperSpeed Burst Transactions

4.15 Suspend-Resume

4.15.1 Port Suspend

4.15.1.1 Selective Suspend

4.15.1.2 Function Suspend

4.15.2 Port Resume

4.15.2.1 Device Initiated

4.15.2.2 Host Initiated

4.15.2.3 Wakeup Events

4.16 Bandwidth Management

4.16.1 Bandwidth Negotiation

4.16.2 Bandwidth Domains

4.17 Interrupters

4.17.1 Interrupter Mapping

4.17.2 Interrupt Moderation

4.17.3 Interrupt Pin Support

4.17.4 Interrupter Target Identification

4.17.5 Interrupt Blocking

4.18 Transfer Definition and Attributes

4.18.1 No snoop

4.18.2 No Snoop and Relaxed Ordering for USB Traffic

4.18.2.1 No Snoop option for payload

4.18.2.2 No Snoop option for Scratchpad references

4.19 Root Hub

4.19.1 Root Hub Port State Machines

4.19.1.1 USB2 Root Hub Port

4.19.1.1.1 Powered-off

4.19.1.1.2 Disconnected

4.19.1.1.3 Disabled

4.19.1.1.4 Reset

4.19.1.1.5 Test Mode

4.19.1.1.6 Enabled

4.19.1.1.7 U0

4.19.1.1.8 U2Entry

4.19.1.1.9 U2

4.19.1.1.10 U2Exit

4.19.1.1.11 U3Entry

4.19.1.1.12 U3

4.19.1.1.13 Resume

4.19.1.1.14 RExit

4.19.1.2 USB3 Root Hub Port

4.19.1.2.1 Disabled

4.19.1.2.2 Powered-off

4.19.1.2.3 Disconnected

4.19.1.2.4 Polling

4.19.1.2.4.1 Training

4.19.1.2.4.2 CfgExcg

4.19.1.2.4.3 DbC

4.19.1.2.4.3.1 DbC Disconnected

4.19.1.2.4.3.2 DbC Disabled

4.19.1.2.4.3.3 DbC Powered-off

4.19.1.2.5 Reset

4.19.1.2.6 Error

4.19.1.2.7 Compliance

4.19.1.2.8 Loopback

4.19.1.2.9 Enabled

4.19.1.2.10 U0

4.19.1.2.11 U1’

4.19.1.2.11.1 U1_Rx

4.19.1.2.11.2 U1_Tx

4.19.1.2.11.3 U1

4.19.1.2.12 U2’

4.19.1.2.12.1 U2_Rx

4.19.1.2.12.2 U2_Tx

4.19.1.2.12.3 U2

4.19.1.2.13 U3’

4.19.1.2.13.1 U3Entry

4.19.1.2.13.2 U3

4.19.1.2.13.3 Resume

4.19.1.2.13.4 RExit

4.19.1.2.13.5 U3Exit

4.19.1.2.14 Recovery

4.19.2 Port Status Change Generation

4.19.3 Connect Status Change Reporting

4.19.4 Port Power

4.19.4.1 Enabled U0 States

4.19.5 Port Reset

4.19.5.1 Warm Port Reset

4.19.6 Port Test Modes

4.19.7 Port Routing and Control

4.19.8 Cold Attach Status

4.20 Scratchpad Buffers

4.21 PCI Express

4.21.1 Configuration sharing among PCI functions

4.21.2 Bus Master Enable (BME)

4.22 xHCI Extended Capabilities

4.22.1 Pre-OS to OS Handoff Synchronization

4.22.2 Debug Capability Operational Model

4.22.3 Virtualization

4.23 Power Management

4.23.1 Power Wells

4.23.2 xHCI Power Management

4.23.2.1 Save and Restore Operations

4.23.3 PCI Power Management

4.23.3.1 Standard PCI Power Management

4.23.3.2 PCI Extended Power Management

4.23.4 USB Power Management

4.23.4.1 USB2

4.23.4.2 USB3

4.23.5 USB Link Power Management

4.23.5.1 Root Hub Port LPM Support

4.23.5.1.1 USB2 LPM Support

4.23.5.1.1.1 Hardware Controlled LMP

4.23.5.2 Max Exit Latency

4.23.5.2.1 No Ping Response Error

4.23.5.2.2 Max Exit Latency Too Large Error

4.24 Host Controller Management

4.24.1 Internal Errors

4.24.2 Port to Connector Mapping

4.24.2.1 Root Hub Port to External Port Assignment

4.24.2.2 External Port to USB Connector mapping

4.24.2.3 Mapping Example

5 Register Interface

5.1 Register Conventions

5.1.1 Attributes

5.1.2 Power Well Considerations

5.2 PCI Configuration Registers (USB)

5.2.1 Type 0 PCI Header

5.2.2 Class Code Register

5.2.3 Serial Bus Release Number Register (SBRN)

5.2.4 Frame Length Adjustment Register (FLADJ)

5.2.5 PCI Power Management Interface

5.2.5.1 PCI Power Management Registers

5.2.6 Message Signaled Interrupts (MSI & MSI-X) Capability

5.2.6.1 MSI configuration

5.2.6.2 MSI-X configuration

5.2.6.3 MSI-X Table

5.2.6.4 MSI-X PBA

5.2.6.5 Accessing the MSI-X Table and MSI-X PBA

5.2.7 PCI Express Capability

5.2.8 SR-IOV Extended Capability

5.3 Host Controller Capability Registers

5.3.1 Capability Registers Length (CAPLENGTH)

5.3.2 Host Controller Interface Version Number (HCIVERSION)

5.3.3 Structural Parameters 1 (HCSPARAMS1)

5.3.4 Structural Parameters 2 (HCSPARAMS2)

5.3.5 Structural Parameters 3 (HCSPARAMS3)

5.3.6 Capability Parameters (HCCPARAMS)

5.3.7 Doorbell Offset (DBOFF)

5.3.8 Runtime Register Space Offset (RTSOFF)

5.4 Host Controller Operational Registers

5.4.1 USB Command Register (USBCMD)

5.4.1.1 Run/Stop (R/S)

5.4.2 USB Status Register (USBSTS)

5.4.3 Page Size Register (PAGESIZE)

5.4.4 Device Notification Control Register (DNCTRL)

5.4.5 Command Ring Control Register (CRCR)

5.4.6 Device Context Base Address Array Pointer Register (DCBAAP)

5.4.7 Configure Register (CONFIG)

5.4.8 Port Status and Control Register (PORTSC)

5.4.8.1 USB2 to USB3 Port State Mapping

5.4.9 Port PM Status and Control Register (PORTPMSC)

5.4.9.1 USB3 Protocol PORTPMSC Definition

5.4.9.2 USB2 Protocol PORTPMSC Definition

5.4.10 Port Link Info Register (PORTLI)

5.4.10.1 USB3 Protocol PORTLI Definition

5.4.10.2 USB2 Protocol PORTLI Definition

5.5 Host Controller Runtime Registers

5.5.1 Microframe Index Register (MFINDEX)

5.5.2 Interrupter Register Set

5.5.2.1 Interrupter Management Register (IMAN)

5.5.2.2 Interrupter Moderation Register (IMOD)

5.5.2.3 Event Ring Registers

5.5.2.3.1 Event Ring Segment Table Size Register (ERSTSZ)

5.5.2.3.2 Event Ring Segment Table Base Address Register (ERSTBA)

5.5.2.3.3 Event Ring Dequeue Pointer Register (ERDP)

5.6 Doorbell Registers

6 Data Structures

6.1 Device Context Base Address Array

6.2 Contexts

6.2.1 Device Context

6.2.2 Slot Context

6.2.2.1 Address Device Command Usage

6.2.2.2 Configure Endpoint Command Usage

6.2.2.3 Evaluate Context Command Usage

6.2.3 Endpoint Context

6.2.3.1 Address Device Command Usage

6.2.3.2 Configure Endpoint Command Usage

6.2.3.3 Evaluate Context Command Usage

6.2.3.4 Max Burst Size

6.2.3.5 Max Packet Size

6.2.3.6 Interval

6.2.4 Stream Context Array

6.2.4.1 Stream Context

6.2.5 Input Context

6.2.5.1 Input Control Context

6.2.6 Port Bandwidth Context

6.3 TRB Ring

6.4 Transfer Request Block (TRB)

6.4.1 Transfer TRBs

6.4.1.1 Normal TRB

6.4.1.2 Control TRBs

6.4.1.2.1 Setup Stage TRB

6.4.1.2.2 Data Stage TRB

6.4.1.2.3 Status Stage TRB

6.4.1.3 Isoch TRB

6.4.1.4 No Op TRB

6.4.2 Event TRBs

6.4.2.1 Transfer Event TRB

6.4.2.2 Command Completion Event TRB

6.4.2.3 Port Status Change Event TRB

6.4.2.4 Bandwidth Request Event TRB

6.4.2.5 Doorbell Event TRB

6.4.2.6 Host Controller Event TRB

6.4.2.7 Device Notification Event TRB

6.4.2.8 MFINDEX Wrap Event TRB

6.4.3 Command TRBs

6.4.3.1 No Op Command TRB

6.4.3.2 Enable Slot Command TRB

6.4.3.3 Disable Slot Command TRB

6.4.3.4 Address Device Command TRB

6.4.3.5 Configure Endpoint Command TRB

6.4.3.6 Evaluate Context Command TRB

6.4.3.7 Reset Endpoint Command TRB

6.4.3.8 Stop Endpoint Command TRB

6.4.3.9 Set TR Dequeue Pointer Command TRB

6.4.3.10 Reset Device Command TRB

6.4.3.11 Force Event Command TRB (Optional Normative)

6.4.3.12 Negotiate Bandwidth Command TRB (Optional Normative)

6.4.3.13 Set Latency Tolerance Value (LTV) Command TRB (Optional Normative)

6.4.3.14 Get Port Bandwidth Command TRB

6.4.3.15 Force Header Command TRB

6.4.4 Other TRBs

6.4.4.1 Link TRB

6.4.4.2 Event Data TRB

6.4.5 TRB Completion Codes

6.4.6 TRB Types

6.5 Event Ring Segment Table

6.6 Scratchpad Buffer Array

6.6.1 PSZ

7 xHCI Extended Capabilities

7.1 USB Legacy Support Capability

7.1.1 USB Legacy Support Capability (USBLEGSUP)

7.1.2 USB Legacy Support Control/Status (USBLEGCTLSTS)

7.2 xHCI Supported Protocol Capability

7.2.1 Protocol Speed ID (PSI)

7.2.2 Supported Protocols

7.2.2.1 USB Protocols

7.2.2.1.1 Default USB Speed ID Mapping

7.2.2.1.2 Protocol Speed ID Count (PSIC) field

7.2.2.1.3 Protocol Defined field

7.2.2.1.3.1 USB3

7.2.2.1.3.2 USB2

7.3 xHCI Extended Power Management Capability

7.4 xHCI Extended Message Interrupt Capability

7.5 xHCI Message Interrupt Capability

7.6 Debug Capability (DbC)

7.6.1 Debugging Topologies

7.6.2 Debug Stacks

7.6.2.1 Debug Software Startup

7.6.3 Memory Map

7.6.3.1 ERST and Event Ring

7.6.3.2 Endpoint Contexts and Transfer Rings

7.6.4 Operational Model

7.6.4.1 Debug Capability Initialization

7.6.4.2 Event Generation

7.6.4.3 Halted DbC Endpoints

7.6.5 Port Routing and Control

7.6.6 DbC Port State Machine

7.6.6.1 DbC-Off

7.6.6.2 DbC-Disconnected

7.6.6.3 DbC-Enabled

7.6.6.4 DbC-Configured

7.6.6.5 DbC-Resetting

7.6.6.6 DbC-Disabled

7.6.6.7 DbC-Error

7.6.7 The USB Debug Device

7.6.7.1 Enumeration Mode

7.6.7.2 Run Mode

7.6.7.2.1 Data Transfers

7.6.7.3 Event Generation

7.6.7.3.1 Data Transfers

7.6.7.3.2 Debug Capability Status Changes

7.6.7.4 Port Reset

7.6.8 Debug Capability Structure

7.6.8.1 Debug Capability ID Register (DCID)

7.6.8.2 Debug Capability Doorbell Register (DCDB)

7.6.8.3 Debug Capability Event Ring Registers

7.6.8.3.1 Debug Capability Event Ring Segment Table Size Reg (DCERSTSZ)

7.6.8.3.2 Debug Capability Event Ring Segment Table Base Address Register (DCERSTBA)

7.6.8.3.3 Debug Capability Event Ring Dequeue Pointer Register (DCERDP)

7.6.8.4 Debug Capability Control Register (DCCTRL)

7.6.8.5 Debug Capability Status Register (DCST)

7.6.8.6 Debug Capability Port Status and Control Register (DCPORTSC)

7.6.8.7 Debug Capability Context Pointer Register (DCCP)

7.6.8.8 Debug Capability Device Descriptor Info Register 1 (DCDDI1)

7.6.8.9 Debug Capability Device Descriptor Info Register 2 (DCDDI2)

7.6.9 Data Structures

7.6.9.1 Debug Capability Info Context (DbCIC)

7.6.9.2 Debug Capability Endpoint Context

7.6.10 USB Descriptors for Debug Class Device

7.6.10.1 Device Descriptor

7.6.10.2 Configuration Descriptor

7.6.10.3 Interface Descriptor

7.6.10.4 Endpoint Descriptor 1 (Bulk OUT)

7.6.10.5 SuperSpeed Endpoint Companion Descriptor 1 (Bulk OUT)

7.6.10.6 Endpoint Descriptor 2 (Bulk IN)

7.6.10.7 SuperSpeed Endpoint Companion Descriptor 2 (Bulk IN)

7.6.10.8 Binary Object Store (BOS) Descriptor

7.6.10.9 String Descriptors

7.7 xHCI I/O Virtualization (xHCI-IOV) Capability

7.7.1 Capability Header

7.7.2 VF Interrupter Range Registers

7.7.3 VF Device Slot Assignment Registers

7.8 xHCI Local Memory Capability

8 Virtualization

8.1 Operation

8.1.1 Resource Assignment

8.1.1.1 MMIO Space

8.1.1.2 Device Slots

8.1.1.3 Interrupters

8.1.2 Device Enumeration and Handoff

8.1.2.1 Root Hub Attach Emulation

8.1.2.2 External Hub Attach Emulation

8.2 SR-IOV Extended Capability

8.2.1 SR-IOV Extended Capability Structure

8.2.2 xHCI-IOV Extended Capability Structure

8.3 Doorbell Registers and Virtualization

8.3.1 Direct-Assigned Device Slot

8.3.2 Emulated Device Slot

8.4 Interrupter Mapping

8.5 Register Space Emulation

Appendix A - xHCI PCI Power Management Interface

A.1 PCI Power Management Register Interface

A.1.1 Power State Transitions

A.1.2 Power State Definitions

A.2 PCI PME# Signal

Appendix B - High Bandwidth Isochronous Rules

B.1 High-speed

Appendix C - Stream Usage Models

Appendix D - Port to Connector Mapping

D.1 Example

D.1.1 ACPI Code Example

Appendix E - State Machine Notation

Appendix F - SS Bus Access Constraints

F.2 Interrupt Transfer Bus Access Constraints

F.3 Isochronous Transfer Bus Access Constraints

Appendix G - 0.96 Exceptions

G.1 Skip Link TRB IOC flag

G.2 Force Stopped Event Optional

G.3 Secondary Bandwidth Domain Reporting Optional

G.4 USB2 L1 Capability Optional

eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Revision 1.0 5/21/10 1

eXtensible Host Controller Interface Revision 1.0 NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. CONTACT INTEL ON FURTHER LICENSING AGREEMENTS AND REQUIREMENTS. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2008-2010 Intel Corporation. All rights reserved. 2

eXtensible Host Controller Interface Revision 1.0 Revision History Revision 0.96 1.0 Issue Date 5/8/2009 5/21/10 • Comments Refer to Errata files. Please send comments via electronic mail to: xhcisupport@intel.com 3

eXtensible Host Controller Interface Revision 1.0 Contributors Randy Aull Martin Borve Brent Chartrand Huimin Chen Eric DeHaemer Vidyadhari Dharmaraju Paul Diefenbaugh Bob Dunstan Nobuo Furuya John Garney Charlie Guy Dave Harriman David Hines Brad Hosler John S. Howard Rahman Ismail Surya Kareenahalli Michael Kentley Piotr Kwidzinski Philip Lantz Brian Lounsbery Ben Lunt Mark Masak Steve McGowan Nobuyuki Mizukoshi Saleem Mohammad Anoop Mukker Jie Ni Hajime Nozaki Jake Oshins Fizal Peermohamed Tomaz Pielaszkiewicz Georg Potthast Diane Rose Hiro Sakamoto Nitin Sarangdhar Makoto Sato Joe Schaefer Sarah Sharp Glen Slick Gary Solomon Kevin Beow Ee Tan 4 Microsoft Corporation Microsoft Corporation Intel Corporation Intel Corporation Intel Corporation Intel Corporation Intel Corporation Intel Corporation NEC Corporation MCCI Corporation Avsys Corporation Intel Corporation Intel Corporation Intel Corporation Intel Corporation Intel Corporation Intel Corporation High Desert Design Center Intel Corporation Intel Corporation Intel Corporation Forever Young Software Microsoft Corporation Intel Corporation NEC Corporation Synopsys, Inc. Intel Corporation Fresco Logic, Inc. NEC Corporation Microsoft Corporation Microsoft Corporation Intel Corporation Independent contractor Specwerkz LLC NEC Corporation Intel Corporation NEC Corporation Intel Corporation Intel Corporation Microsoft Corporation Intel Corporation Intel Corporation

eXtensible Host Controller Interface Revision 1.0 “Peter” Chu Tin Teng Jay Tseng Karthi Vadivelu Krishnan Venkataraman Jim Walsh Jennifer Wang Eric Wittmayer Steven E. Zawid Kevin Zhenyu Zhu NEC Corporation VIA Technologies, Inc. Intel Corporation Moschip Semiconductor Tech. Ltd. Intel Corporation Intel Corporation Fresco Logic, Inc. Intel Corporation Intel Corporation 5

eXtensible Host Controller Interface Revision 1.0 Dedication The xHCI Specification is dedicated to the memory of Brad Hosler, a good friend and the impact of whose accomplishments have made the Universal Serial Bus one of the most successful technology innovations of the Personal Computer era. - The xHCI Architecture Team 6

eXtensible Host Controller Interface Revision 1.0 Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1 PREFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 OBJECTIVE OF SPECIFICATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.1 1.2 SCOPE OF DOCUMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DOCUMENT ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.3 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 1.4 INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.5 1.6 TERMS AND ABBREVIATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DOCUMENTATION CONVENTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.7 Capitalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.7.1 Italic Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.7.2 1.7.3 Numbers and Number Bases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Implementation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.7.4 Word Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.7.5 Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 1.7.6 1.7.7 Other Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2 MOTIVATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.1 2.1.1 Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.2 2.3 XHCI PRODUCT COMPLIANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3 ARCHITECTURAL OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INTERFACE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1 3.2 XHCI DATA STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Device Context Base Address Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.1 3.2.2 Device Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Slot Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.2.3 Endpoint Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.4 Stream Context Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.4.1 3.2.4.1.1 Stream Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Input Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2.5 Input Control Context. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.5.1 Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.2.6 Transfer Ring Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2.6.1 3.2.7 Transfer Request Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2.7.1 Other Rings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.7.2 Scatter/Gather Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.2.8 3.2.9 Control Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Bulk and Interrupt Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.10 Isoch Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.2.11 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.3 3.3.1 No Op. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Enable Slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.2 Disable Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.3 Address Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.3.4 3.3.5 Configure Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7

eXtensible Host Controller Interface Revision 1.0 Evaluate Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.3.6 Reset Endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.7 Stop Endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.8 Set TR Dequeue Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.9 Reset Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.10 Force Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 3.3.11 Negotiate Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.12 Set Latency Tolerance Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.13 Get Port Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.14 Force Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.3.15 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.4 ROOT HUB MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.5 3.6 XHCI DEVICE ENUMERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4 OPERATIONAL MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 COMMAND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.1 HOST CONTROLLER INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.2 4.3 USB DEVICE INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Resetting a Root Hub Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4.3.1 Device Slot Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.2 Device Slot Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.3.3 4.3.4 Address Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.3.5 Setting Alternate Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.3.6 Low-Speed/Full-Speed Device Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 4.3.7 4.3.8 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DEVICE DETACH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.4 DEVICE SLOT MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.5 Device Context Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.5.1 4.5.2 Slot Context Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Slot States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.5.3 Device Slot State Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.3.1 Disabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.3.2 4.5.3.3 Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.3.4 Addressed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.5.3.5 Configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.3.6 4.5.4 USB Standard Device Request to xHCI Command Mapping . . . . . . . . . . . . . . . . . . . . . . . . 84 SET_ADDRESS Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.4.1 SET_CONFIGURATION Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.5.4.2 SET_INTERFACE Request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4.5.4.3 4.6 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Command Ring Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.6.1 Stopping the Command Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.1 Aborting a Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.6.1.2 4.6.2 No Op. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Enable Slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 4.6.3 Disable Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.6.4 Address Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.6.5 4.6.6 Configure Endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Evaluate Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.6.7 Reset Endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.6.8 Soft Retry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.6.8.1 4.6.9 Stop Endpoint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8

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