STM32F405RGT6尺寸数据64引脚.pdf

发布时间：2022-06-01 发布人：admin 分类：说明书资料大小：0.37M 资料格式：pdf 举报版权申诉

xl__max-10742314-4744302543411626084.pdf-第1页.png

第1页 / 共3页

xl__max-10742314-4744302543411626084.pdf-第2页.png

第2页 / 共3页

xl__max-10742314-4744302543411626084.pdf-第3页.png

第3页 / 共3页

Table 1. Device summary

1 Introduction

2 Description

Table 2. STM32F405xx and STM32F407xx: features and peripheral counts (continued)

2.1 Full compatibility throughout the family

2.2 Device overview

2.2.1 ARM® Cortex®-M4 core with FPU and embedded Flash and SRAM

2.2.2 Adaptive real-time memory accelerator (ART Accelerator™)

2.2.3 Memory protection unit

2.2.4 Embedded Flash memory

2.2.5 CRC (cyclic redundancy check) calculation unit

2.2.6 Embedded SRAM

2.2.7 Multi-AHB bus matrix

2.2.8 DMA controller (DMA)

2.2.9 Flexible static memory controller (FSMC)

2.2.10 Nested vectored interrupt controller (NVIC)

2.2.11 External interrupt/event controller (EXTI)

2.2.12 Clocks and startup

2.2.13 Boot modes

2.2.14 Power supply schemes

2.2.15 Power supply supervisor

2.2.16 Voltage regulator

2.2.17 Regulator ON/OFF and internal reset ON/OFF availability

Table 3. Regulator ON/OFF and internal reset ON/OFF availability

2.2.18 Real-time clock (RTC), backup SRAM and backup registers

2.2.19 Low-power modes

2.2.20 VBAT operation

2.2.21 Timers and watchdogs

Table 4. Timer feature comparison

2.2.22 Inter-integrated circuit interface (I²C)

2.2.23 Universal synchronous/asynchronous receiver transmitters (USART)

Table 5. USART feature comparison

2.2.24 Serial peripheral interface (SPI)

2.2.25 Inter-integrated sound (I2S)

2.2.26 Audio PLL (PLLI2S)

2.2.27 Secure digital input/output interface (SDIO)

2.2.28 Ethernet MAC interface with dedicated DMA and IEEE 1588 support

2.2.29 Controller area network (bxCAN)

2.2.30 Universal serial bus on-the-go full-speed (OTG_FS)

2.2.31 Universal serial bus on-the-go high-speed (OTG_HS)

2.2.32 Digital camera interface (DCMI)

2.2.33 Random number generator (RNG)

2.2.34 General-purpose input/outputs (GPIOs)

2.2.35 Analog-to-digital converters (ADCs)

2.2.36 Temperature sensor

2.2.37 Digital-to-analog converter (DAC)

2.2.38 Serial wire JTAG debug port (SWJ-DP)

2.2.39 Embedded Trace Macrocell™

3 Pinouts and pin description

Table 6. Legend/abbreviations used in the pinout table

Table 7. STM32F40xxx pin and ball definitions

Table 8. FSMC pin definition

Table 9. Alternate function mapping

4 Memory mapping

Table 10. register boundary addresses

5 Electrical characteristics

5.1 Parameter conditions

5.1.1 Minimum and maximum values

5.1.2 Typical values

5.1.3 Typical curves

5.1.4 Loading capacitor

5.1.5 Pin input voltage

5.1.6 Power supply scheme

5.1.7 Current consumption measurement

5.2 Absolute maximum ratings

Table 11. Voltage characteristics

Table 12. Current characteristics

Table 13. Thermal characteristics

5.3 Operating conditions

5.3.1 General operating conditions

Table 14. General operating conditions

Table 15. Limitations depending on the operating power supply range

5.3.2 VCAP_1/VCAP_2 external capacitor

Table 16. VCAP_1/VCAP_2 operating conditions

5.3.3 Operating conditions at power-up / power-down (regulator ON)

Table 17. Operating conditions at power-up / power-down (regulator ON)

5.3.4 Operating conditions at power-up / power-down (regulator OFF)

Table 18. Operating conditions at power-up / power-down (regulator OFF)

5.3.5 Embedded reset and power control block characteristics

Table 19. Embedded reset and power control block characteristics

5.3.6 Supply current characteristics

Table 20. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator enabled) or RAM

Table 21. Typical and maximum current consumption in Run mode, code with data processing running from Flash memory (ART accelerator disabled)

Table 22. Typical and maximum current consumption in Sleep mode

Table 23. Typical and maximum current consumptions in Stop mode

Table 24. Typical and maximum current consumptions in Standby mode

Table 25. Typical and maximum current consumptions in VBAT mode

Table 26. Typical current consumption in Run mode, code with data processing running from Flash memory, regulator ON (ART accelerator enabled except prefetch), VDD = 1.8 V

Table 27. Switching output I/O current consumption

Table 28. Peripheral current consumption

5.3.7 Wakeup time from low-power mode

Table 29. Low-power mode wakeup timings

5.3.8 External clock source characteristics

Table 30. High-speed external user clock characteristics

Table 31. Low-speed external user clock characteristics

Table 32. HSE 4-26 MHz oscillator characteristics

Table 33. LSE oscillator characteristics (fLSE = 32.768 kHz)

5.3.9 Internal clock source characteristics

Table 34. HSI oscillator characteristics

Table 35. LSI oscillator characteristics

5.3.10 PLL characteristics

Table 36. Main PLL characteristics

Table 37. PLLI2S (audio PLL) characteristics

5.3.11 PLL spread spectrum clock generation (SSCG) characteristics

Table 38. SSCG parameters constraint

5.3.12 Memory characteristics

Table 39. Flash memory characteristics

Table 40. Flash memory programming

Table 41. Flash memory programming with VPP

Table 42. Flash memory endurance and data retention

5.3.13 EMC characteristics

Table 43. EMS characteristics

Table 44. EMI characteristics

5.3.14 Absolute maximum ratings (electrical sensitivity)

Table 45. ESD absolute maximum ratings

Table 46. Electrical sensitivities

5.3.15 I/O current injection characteristics

Table 47. I/O current injection susceptibility

5.3.16 I/O port characteristics

Table 48. I/O static characteristics

Table 49. Output voltage characteristics

Table 50. I/O AC characteristics

5.3.17 NRST pin characteristics

Table 51. NRST pin characteristics

5.3.18 TIM timer characteristics

Table 52. Characteristics of TIMx connected to the APB1 domain

Table 53. Characteristics of TIMx connected to the APB2 domain

5.3.19 Communications interfaces

Table 54. I2C analog filter characteristics

Table 55. SPI dynamic characteristics

Table 56. I2S dynamic characteristics

Table 57. USB OTG FS startup time

Table 58. USB OTG FS DC electrical characteristics

Table 59. USB OTG FS electrical characteristics

Table 60. USB HS DC electrical characteristics

Table 61. USB HS clock timing parameters

Table 62. ULPI timing

Table 63. Ethernet DC electrical characteristics

Table 64. Dynamic characteristics: Eternity MAC signals for SMI

Table 65. Dynamic characteristics: Ethernet MAC signals for RMII

Table 66. Dynamic characteristics: Ethernet MAC signals for MII

5.3.20 CAN (controller area network) interface

5.3.21 12-bit ADC characteristics

Table 67. ADC characteristics

Table 68. ADC accuracy at fADC = 30 MHz

5.3.22 Temperature sensor characteristics

Table 69. Temperature sensor characteristics

Table 70. Temperature sensor calibration values

5.3.23 VBAT monitoring characteristics

Table 71. VBAT monitoring characteristics

5.3.24 Embedded reference voltage

Table 72. Embedded internal reference voltage

Table 73. Internal reference voltage calibration values

5.3.25 DAC electrical characteristics

Table 74. DAC characteristics

5.3.26 FSMC characteristics

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

Table 76. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

Table 77. Asynchronous multiplexed PSRAM/NOR read timings

Table 78. Asynchronous multiplexed PSRAM/NOR write timings

Table 79. Synchronous multiplexed NOR/PSRAM read timings

Table 80. Synchronous multiplexed PSRAM write timings

Table 81. Synchronous non-multiplexed NOR/PSRAM read timings

Table 82. Synchronous non-multiplexed PSRAM write timings

Table 83. Switching characteristics for PC Card/CF read and write cycles in attribute/common space

Table 84. Switching characteristics for PC Card/CF read and write cycles in I/O space

Table 85. Switching characteristics for NAND Flash read cycles

Table 86. Switching characteristics for NAND Flash write cycles

5.3.27 Camera interface (DCMI) timing specifications

Table 87. DCMI characteristics

5.3.28 SD/SDIO MMC card host interface (SDIO) characteristics

Table 88. Dynamic characteristics: SD / MMC characteristics

5.3.29 RTC characteristics

Table 89. RTC characteristics

6 Package information

6.1 WLCSP90 package information

Table 90. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale package mechanical data

Table 91. WLCSP90 recommended PCB design rules

6.2 LQFP64 package information

Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data

6.3 LQPF100 package information

Table 93. LQPF100 – 100-pin, 14 x 14 mm low-profile quad flat package mechanical data

6.4 LQFP144 package information

Table 94. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data

6.5 UFBGA176+25 package information

Table 95. UFBGA176+25 ball, 10 × 10 × 0.65 mm pitch, ultra thin fine pitch ball grid array mechanical data

Table 96. UFBGA176+2 recommended PCB design rules (0.65 mm pitch BGA)

6.6 LQFP176 package information

Table 97. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package mechanical data

6.7 Thermal characteristics

Table 98. Package thermal characteristics

7 Part numbering

Table 99. Ordering information scheme

Appendix A Application block diagrams

A.1 USB OTG full speed (FS) interface solutions

A.2 USB OTG high speed (HS) interface solutions

A.3 Ethernet interface solutions

8 Revision history

Table 100. Document revision history (continued)

STM32F405RGT6 Package information 6.2 LQFP64 package information Figure 78. LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package outline 1. Drawing is not to scale. DocID022152 Rev 8

STM32F405RGT6 Package information Table 92. LQFP64 – 64-pin 10 x 10 mm low-profile quad flat package mechanical data Symbol A A1 A2 b c D D1 D3 E E1 E3 e K L L1 ccc Min - 0.050 1.350 0.170 0.090 - - - - - - - 0° 0.450 - - millimeters inches(1) Typ - - 1.400 0.220 - 12.000 10.000 7.500 12.000 10.000 7.500 0.500 3.5° 0.600 1.000 - Max 1.600 0.150 1.450 0.270 0.200 - - - - - - - 7° Min - 0.0020 0.0531 0.0067 0.0035 - - - - - - - 0° 0.750 - 0.080 0.0177 - - Typ - - 0.0551 0.0087 - 0.4724 0.3937 0.2953 0.4724 0.3937 0.2953 0.0197 3.5° 0.0236 0.0394 - Max 0.0630 0.0059 0.0571 0.0106 0.0079 - - - - - - - 7° 0.0295 - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID022152 Rev 8

STM32F405xx, STM32F407xx Package information Figure 79. LQFP64 – 64-pin, 10 x 10 mm low-profile quad flat package recommended footprint 1. Dimensions are in millimeters. DocID022152 Rev 8

分享到：

赞收藏

资料库

STM32F405RGT6尺寸数据64引脚.pdf

相关推荐

行业

热门标签

最新资料