ARM Cortex-M7 内核编程技术说明文档(英文).pdf

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ARM Cortex-M7 Processor Technical Reference Manual

Contents

Preface

About this book

Product revision status

Intended audience

Using this book

Glossary

Conventions

Additional reading

Feedback

Feedback on this product

Feedback on content

1: Introduction

1.1 About the Cortex-M7 processor

1.1.1 Features

1.1.2 Interfaces

1.1.3 Configuration options

1.2 Component blocks

1.2.1 Data Processing Unit

1.2.2 Prefetch Unit

1.2.3 Load Store Unit

1.2.4 Floating Point Unit

1.2.5 Nested Vectored Interrupt Controller

1.2.6 Wake-up Interrupt Controller

1.2.7 Memory System

1.2.8 Store Buffer

1.2.9 Memory Protection Unit

1.2.10 Cortex-M7 Processor and PPB ROM tables

1.2.11 Cross Trigger Interface Unit

1.2.12 ETM

1.2.13 Debug and trace components

1.3 Interfaces

1.3.1 AHBP interface

1.3.2 AHBS interface

1.3.3 AHBD interface

1.3.4 External Private Peripheral Bus

1.3.5 ATB interfaces

1.3.6 TCM interface

1.3.7 Cross Trigger interface

1.3.8 MBIST interface

1.3.9 AXIM interface

1.4 Supported standards

1.4.1 ARM architecture

1.4.2 Bus architecture

1.4.3 Debug

1.4.4 Embedded Trace Macrocell

1.4.5 Floating Point Unit

1.5 Design process

1.6 Documentation

1.7 Product revisions

2: Programmers Model

2.1 About the programmers model

2.2 Modes of operation and execution

2.2.1 Operating modes

2.2.2 Operating states

2.2.3 Privileged access and unprivileged User access

2.3 Instruction set summary

2.3.1 Binary compatibility with other Cortex processors

2.4 System address map

2.4.1 Private peripheral bus

2.4.2 Unaligned accesses that cross regions

2.5 Exclusive monitor

2.6 Processor core registers

2.7 Exceptions

2.7.1 Exception handling

3: System Control

3.1 About system control

3.2 Register summary

3.3 Register descriptions

3.3.1 Auxiliary Control Register

3.3.2 CPUID Base Register

3.3.3 Cache Level ID Register

3.3.4 Cache Size ID Register

3.3.5 Cache Size Selection Register

3.3.6 Instruction and Data Tightly-Coupled Memory Control Registers

3.3.7 AHBP Control Register

3.3.8 L1 Cache Control Register

3.3.9 Auxiliary Bus Fault Status Register

3.3.10 Instruction Error bank Register 0-1

3.3.11 Data Error bank Register 0-1

3.3.12 AHB Slave Control Register

4: Initialization

4.1 About Initialization

4.1.1 Initializing the MPU

4.1.2 Initializing the FPU

4.1.3 Initializing and enabling the L1 cache

4.1.4 Disabling cache error checking and correction

4.1.5 Enabling the TCM

4.1.6 Preloading TCM

4.1.7 Enabling the TCM retry and read-modify-write

4.1.8 Enabling the AHBP interface

5: Memory System

5.1 About the memory system

5.2 Fault handling

5.2.1 Faults

5.2.2 Usage models

5.3 Memory types and memory system behavior

5.4 AXIM interface

5.4.1 AXI attributes and transactions

5.4.2 Identifiers for AXIM interface accesses

5.4.3 AXI privilege information

5.4.4 Write response

5.4.5 AXI extensions

5.4.6 Memory system implications for AXI accesses

5.4.7 AXIM interface transfers

5.5 AHB peripheral interface

5.5.1 AHBP interface transfers

5.5.2 AHBP semaphores

5.6 AHB slave interface

5.6.1 Memory map

5.6.2 Restrictions on AHBS transactions

5.6.3 AHBS interface arbitration

5.7 TCM interfaces

5.7.1 TCM attributes and permissions

5.7.2 TCM configuration

5.7.3 TCM arbitration

5.7.4 TCM interface protocol

5.7.5 TCM read modify write

5.7.6 Booting from TCM

5.7.7 Integration with Flash memory

5.7.8 System access to TCM

5.8 L1 caches

5.8.1 Dynamic read allocate mode

5.8.2 Store buffer

5.8.3 Cache maintenance operations

5.8.4 Cache interaction with memory system

6: Memory Protection Unit

6.1 About the MPU

6.2 MPU functional description

6.3 MPU programmers model

7: Nested Vectored Interrupt Controller

7.1 About the NVIC

7.2 NVIC functional description

7.2.1 Low power modes

7.2.2 Level versus pulse interrupts

7.3 NVIC programmers model

7.3.1 Interrupt Controller Type Register

8: Floating Point Unit

8.1 About the FPU

8.2 FPU functional description

8.2.1 Modes of operation

8.2.2 Compliance with the IEEE 754 standard

8.2.3 Exceptions

8.3 FPU programmers model

9: Debug

9.1 About debug

9.1.1 Cortex-M7 Processor ROM table identification and entries

9.1.2 Cortex-M7 PPB ROM table identification and entries

9.1.3 System Control Space

9.1.4 Debug register summary

9.2 About the AHBD interface

9.3 About the FPB

9.3.1 FPB functional description

9.3.2 FPB programmers model

10: Cross Trigger Interface

10.1 About the CTI

10.2 Cortex-M7 CTI functional description

10.3 CTI programmers model

11: Data Watchpoint and Trace Unit

11.1 About the DWT

11.2 DWT functional description

11.3 DWT programmers model

12: Instrumentation Trace Macrocell Unit

12.1 About the ITM

12.2 ITM functional description

12.3 ITM programmers model

12.3.1 ITM Trace Privilege Register

13: Fault detection and handling

13.1 About fault detection and handling

13.1.1 RAM and logic protection

13.1.2 Analysis of errors

13.2 Cache RAM protection

13.2.1 Protection method

13.2.2 RAM protection summary

13.2.3 ECC codes

13.2.4 RAM configuration

13.2.5 Performance impact

13.3 Logic protection

A: Revisions

ARM Cortex-M7 Processor Technical Reference Manual Copyright © 2014, 2015 ARM. All rights reserved. Release Information The following changes have been made to this book. Change history Date Issue Confidentiality Change 25 April 2014 05 December 2014 19 March 2015 07 July 2015 A B C D Confidential First release for r0p0 Non-Confidential First release for r0p2 Non-Confidential First release for r1p0 Non-Confidential First release for r1p1 Proprietary Notice This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated. Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents. THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights. This document may include technical inaccuracies or typographical errors. TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice. If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail. Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited or its affiliates in the EU and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow ARM’s trademark usage guidelines at http://www.arm.com/about/trademark-usage-guidelines.php Copyright © 2015, ARM Limited or its affiliates. All rights reserved. ARM Limited. Company 02557590 registered in England. 110 Fulbourn Road, Cambridge, England CB1 9NJ. ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential ii

Confidentiality Status This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to. Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential iii

Contents ARM Cortex-M7 Processor Technical Reference Manual Chapter 1 Chapter 2 Chapter 3 Preface About this book .......................................................................................................... vii Feedback .................................................................................................................... xi Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 About the Cortex-M7 processor ............................................................................... 1-2 Component blocks ................................................................................................... 1-6 Interfaces ............................................................................................................... 1-11 Supported standards ............................................................................................. 1-13 Design process ...................................................................................................... 1-14 Documentation ....................................................................................................... 1-15 Product revisions ................................................................................................... 1-16 Programmers Model 2.1 2.2 2.3 2.4 2.5 2.6 2.7 About the programmers model ................................................................................ 2-2 Modes of operation and execution ........................................................................... 2-3 Instruction set summary ........................................................................................... 2-4 System address map ............................................................................................... 2-5 Exclusive monitor ..................................................................................................... 2-7 Processor core registers .......................................................................................... 2-8 Exceptions ............................................................................................................... 2-9 System Control 3.1 3.2 3.3 About system control ............................................................................................... 3-2 Register summary .................................................................................................... 3-3 Register descriptions ............................................................................................... 3-6 ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential iv

Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Contents Initialization 4.1 About Initialization .................................................................................................... 4-2 Memory System 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 About the memory system ....................................................................................... 5-2 Fault handling .......................................................................................................... 5-3 Memory types and memory system behavior .......................................................... 5-5 AXIM interface ......................................................................................................... 5-6 AHB peripheral interface ........................................................................................ 5-22 AHB slave interface ............................................................................................... 5-30 TCM interfaces ...................................................................................................... 5-33 L1 caches .............................................................................................................. 5-37 Memory Protection Unit 6.1 6.2 6.3 About the MPU ........................................................................................................ 6-2 MPU functional description ...................................................................................... 6-3 MPU programmers model ........................................................................................ 6-4 Nested Vectored Interrupt Controller 7.1 7.2 7.3 About the NVIC ........................................................................................................ 7-2 NVIC functional description ..................................................................................... 7-3 NVIC programmers model ....................................................................................... 7-4 Floating Point Unit 8.1 8.2 8.3 About the FPU ......................................................................................................... 8-2 FPU functional description ....................................................................................... 8-3 FPU programmers model ........................................................................................ 8-5 Debug 9.1 9.2 9.3 About debug ............................................................................................................ 9-2 About the AHBD interface ........................................................................................ 9-7 About the FPB ......................................................................................................... 9-8 Cross Trigger Interface 10.1 10.2 10.3 About the CTI ......................................................................................................... 10-2 Cortex-M7 CTI functional description .................................................................... 10-3 CTI programmers model ........................................................................................ 10-5 Data Watchpoint and Trace Unit 11.1 11.2 11.3 About the DWT ...................................................................................................... 11-2 DWT functional description .................................................................................... 11-3 DWT programmers model ..................................................................................... 11-4 Instrumentation Trace Macrocell Unit 12.1 12.2 12.3 About the ITM ........................................................................................................ 12-2 ITM functional description ...................................................................................... 12-3 ITM programmers model ....................................................................................... 12-4 Fault detection and handling 13.1 13.2 13.3 About fault detection and handling ........................................................................ 13-2 Cache RAM protection ........................................................................................... 13-3 Logic protection ..................................................................................................... 13-6 Appendix A Revisions ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential v

Preface This preface introduces the Cortex-M7 Processor Technical Reference Manual (TRM). It contains the following sections: • • About this book on page vii. Feedback on page xi. ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential vi

About this book Product revision status This book is for the Cortex-M7 processor. Preface Intended audience Using this book The rnpn identifier indicates the revision status of the product described in this manual, where: rn pn Identifies the major revision of the product. Identifies the minor revision or modification status of the product. This manual is written to help system designers, system integrators, verification engineers, and software programmers who are implementing a System-on-Chip (SoC) device based on the Cortex-M7 processor. This book is organized into the following chapters: Chapter 1 Introduction Read this for a description of the components of the processor, and of the product documentation. Chapter 2 Programmers Model Read this for a description of the processor register set, modes of operation, and other information for programming the processor. Chapter 3 System Control Read this for a description of the registers and programmers model for system control. Chapter 4 Initialization Read this for a description of how to initialize the processor. Chapter 5 Memory System Read this for a description of the processor memory system. Chapter 6 Memory Protection Unit Read this for a description of the Memory Protection Unit (MPU). Chapter 7 Nested Vectored Interrupt Controller Read this for a description of the interrupt processing and control. Chapter 8 Floating Point Unit Read this for a description of the Floating Point Unit (FPU). Chapter 9 Debug Read this for information about debugging and testing the processor. Chapter 10 Cross Trigger Interface Read this for information about how the Cross Trigger Interface (CTI) can be configured. ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential vii

Preface Chapter 11 Data Watchpoint and Trace Unit Read this for a description of the Data Watchpoint and Trace (DWT) unit. Chapter 12 Instrumentation Trace Macrocell Unit Read this for a description of the Instrumentation Trace Macrocell (ITM) unit. Chapter 13 Fault detection and handling Read this for a description about how faults are detected and handled in the Cortex-M7 Processor. Appendix A Revisions Read this for a description of the technical changes between released issues of this book. The ARM® Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM® Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning. See ARM® Glossary, http://infocenter.arm.com/help/topic/com.arm.doc.aeg0014-/index.html. This book uses the conventions that are described in: • • • Typographical conventions. Timing diagrams on page ix. Signals on page ix. Typographical conventions The following table describes the typographical conventions: Glossary Conventions Style italic bold monospace monospace Purpose Introduces special terminology, denotes cross-references, and citations. Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value. monospace bold Denotes language keywords when used outside example code. Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example: LDRSB , [, #] SMALL CAPITALS Used in body text for a few terms that have specific technical meanings, that are defined in the ARM glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE. ARM DDI 0489D ID082615 Copyright © 2014, 2015 ARM. All rights reserved. Non-Confidential viii

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