第1页 / 共175页
第2页 / 共175页
第3页 / 共175页
第4页 / 共175页
第5页 / 共175页
第6页 / 共175页
第7页 / 共175页
第8页 / 共175页
ug1037-vivado-axi-reference-guide.pdf
Vivado Design Suite: AXI Reference Guide
Revision History
Table of Contents
Ch. 1: Introducing AXI for Vivado
Overview
What is AXI?
Summary of AXI4 Benefits
How AXI Works
Combining AXI4-Stream and Memory-Mapped Protocols
IP Interoperability
Data Interpretation
IP Compatibility
AXI4-Stream IP Interoperability
Quick Take Videos
Ch. 2: AXI Support in Xilinx Tools and IP
Introduction
Using Vivado AXI IP in RTL Projects
Using the Create and Package IP Wizard for AXI IP
Adding AXI IP to the IP Catalog Using Vivado IP Packager
Using Vivado IP Integrator to Assemble AXI IP
Using AXI IP in System Generator for DSP
Port Name Truncation
Port Groupings
Breaking Out Multichannel TDATA
Adding AXI Interfaces Using High Level Synthesis
HLS AXI4-Stream Interface
HLS AXI4-Lite Interface
HLS AXI4 Master Interface
Individual Data Transfers
Example 1:
Example 2:
Burst-Mode Transfers
Ch. 3: Samples of Vivado AXI IP and Xilinx Processors
Overview
AXI Infrastructure IP Cores
Xilinx AXI SmartConnect and AXI Interconnect IP
AXI Interconnect Core Features
AXI Interconnect Core Limitations
AXI Interconnect Core Use Models
Conversion Only
N-to-1 Interconnect
1-to-N Interconnect
N-to-M Interconnect (Sparse Crossbar Mode)
Cascading AXI Interconnect Cores Together
AXI SmartConnect IP
Feature Summary
AXI SmartConnect Core Limitations
AXI4-Stream Interconnect Core IP
AXI4-Stream Interconnect Core Features
AXI4-Stream Interconnect Core Diagram
AXI4-Stream Interconnect Core Use Models
Streaming Data Routing and Switching (Crossbar Mode)
Stream Multiplexing and De-multiplexing
AXI Virtual FIFO Controller
The AXI4-Stream interconnect can also perform local FIFO buffering, clock conversion, and width conversion to adapt the interface of the stream endpoints to the data path of the virtual FIFO controller and the AXI memory controller
DataMover
AXI4 DMA
AXI DMA Interfaces
Central DMA
AXI Central DMA Summary
AXI Central DMA Scatter Gather Feature
Central DMA Configurable Features
Video DMA
AXI VDMA Summary
VDMA AXI4 Interfaces
Simulating IP
Using Debug and IP
ILA
VIO
IBERT
JTAG-to-AXI
Performance Monitor IP
Protocol Checkers
AXI Verification IP
Features
Uses
AXI4-Stream Verification IP
Features
Overview
Zynq-7000 AP SoC Verification IP
Features
Additional Features
Limitations
MicroBlaze Debug Module
Zynq UltraScale+ MPSoC Processor Device
PS-PL AXI Interfaces
Zynq-7000 All Programmable SoC Processor IP
Choosing a Programmable Logic Interface
PL Interface Comparison Summary
Cortex-A9 CPU Using General Purpose Masters
PS DMA Controller (DMAC) Using General Purpose Masters
PL DMA Using AXI High-Performance (HP) Interface
PL DMA Using AXI ACP
PL DMA Using General Purpose AXI Slave (GP)
Memory Management Unit (MMU)
MicroBlaze Processor
Overview
MicroBlaze Features
Configurable MicroBlaze Feature Overview
MicroBlaze Memory Architecture
MicroBlaze Hardware AXI Exceptions
Using MicroBlaze AXI Instruction Cache
Using MicroBlaze AXI Data Cache
Using Victim Cache
MicroBlaze Stream Link Interfaces
Ch. 4: AXI Feature Adoption in Xilinx Devices
Introduction
Memory-Mapped IP Feature Adoption and Support
AXI4-Stream Adoption and Support
AXI4-Stream Signals
Numerical Data in an AXI4-Stream
Real Scalar Data Example
Complex Scalar Data Example
Vector Data Example
Sideband Signals
Events
TLAST Events
DSP and Wireless IP: AXI Feature Adoption
Video IP: AXI Feature Adoption
IP Using AXI4-Stream Video Protocol
Signal Interfaces
Input Slave Side Connectors
Output Master Side Signals
Clocking and ACLK
TDATA Structure
Clock Enable, ACLKEN
Reset Requirements, ARESETn
TKEEP and TSTRB
TID
TDEST
TUSER
Signaling Protocol
Channel Structure
READY/VALID Handshake
Guidelines on Driving VALID
Driving READY Guidelines
Interfacing to AXI4-Stream With No READY Signal
Start of Frame Signal - SOF
End Of Line Signal - EOL
Real Time Requirements
Data Format
AXI4-Stream Specific Parameterization
Encoding
Encoding Multiple Pixels
Dynamic TDATA Configuration
Ch. 5: Migrating to Xilinx AXI Protocols
Introduction
Migrating to AXI for IP Cores
Migrating IP Using the Vivado Create and Package Wizard
Using System Generator for DSP for Migrating IP
Migrating a Fast Simplex Link to AXI4-Stream
Master FSL to AXI4-Stream Signal Mapping
Slave FSL to AXI4-Stream Signal Mapping
Differences in Throttling
Migrating HDL Designs to use DSP IP with AXI4-Stream
DSP IP-Specific Migration Instructions
Demonstration Test Bench
Upgrading IP
Latency Changes
Mapping Previously Assigned Ports to An AXI4-Stream Video Protocol
High End Verification Solutions
Ch. 6: AXI System Optimization: Tips and Hints
Introduction
AXI System Optimization
Size/Area Optimization Guidelines
Timing and Fmax Optimization Guidelines
Throughput and Bandwidth Optimization Guidelines
Latency Optimization Guidelines
Ease of Use and Debug Optimization Guidelines
AXI4-based Vivado Multi-Ported Memory Controller: AXI4 System Optimization Example
AXI4 Vivado MPMC Overview
Initial Memory Controller Configuration
Initial AXI Interconnect Configuration
Clock Conversion Recommendation
AXI4 Master Configuration
Maximize Burst Length
No Narrow Burst Transactions
Pipeline Transactions
Single Thread Transactions
Refining the AXI Interconnect Configuration
Independently Configure Converter Banks
Timing Considerations
Setting Issuance and Acceptance Values to 2 or Higher
Adding a Processor to the AXI MPMC System
Considerations When Adding a Processor
Additional Potential Optimizations for AXI MPMC
AXI Interconnect: Shared Address Shared Data Mode
Separate IP Groups into Separate AXI Interconnect Subsystems
Debug and Analysis: Using AXI Debug Monitor and AXI Hardware Protocol Checkers
Floorplanning
AXI Verification IP
More Simple but Wider Interconnect and Memory Controller
Cascading Interconnects
Common Pitfalls Leading to AXI Systems of Poor Quality Results
Oversizing a Memory Controller
Incorrect Core Data Width or Core Clock for AXI Interconnect
Overuse of Register Slices
Skipping Simulation-Based Verification of New IP
Non-contiguous Mapping of Slave Devices in Cascaded Interconnect Scenarios
Optimizing AXI on Zynq-7000 AP SoC Processors
Considerations for High Performance AXI Interface Modules
Ch. 7: AXI4-Stream IP Interoperability: Tips and Hints
Introduction
Key Considerations
AXI4-Stream Protocol
Domain Usage Guidelines and Conventions
Video IP
DSP/Wireless IP
Communications IP
AXI Infrastructure IP
Domain-Specific Data Interpretation and Interoperability Guidelines
Video IP Layered Protocols
DSP/Wireless IP Layered Protocols
Communications IP Layered Protocols
AXI Infrastructure IP Layered Protocols
Appx. A: AXI Adoption Summary
Introduction
Global Signals
AXI4 and AXI4-Lite Signals
AXI4 and AXI4-Lite Write Address Channel Signals
AXI4 and AXI4-Lite Write Data Channel Signals
AXI4 and AXI4-Lite Write Response Channel Signals
AXI4 and AXI4-Lite Read Address Channel Signals
AXI4 and AXI4-Lite Read Data Channel Signals
AXI4-Stream Signal Summary
Appx. B: AXI Terminology
Terminology
Appx. C: Additional Resources and Legal Notices
Xilinx Resources
Solution Centers
Documentation Navigator and Design Hubs
Third-Party Documentation
Xilinx Documentation
Xilinx White Papers and Application Notes
General Xilinx References
Vivado Design Suite Video Tutorials
Please Read: Important Legal Notices
Vivado Design
Suite
Vivado AXI Reference
AXI Reference Guide
[optional]
UG1037 (v4.0) July 15, 2017
UG1037 (v4.0) July 15, 2017 [optional]
Revision History
The following table shows the revision history for this document.
Date
Version
07/15/2017
4.0
06/24/2015
3.0
11/20/2014
11/19/2014
2.1
2.0
04/02/2014
1.0
Revision
Updated to match the new Vivado “Look and Feel”.
Updated all IP to reflect current features.
Added Zynq UltraScale+ MPSoC Processor Device in Chapter 3.
Added AXI SmartConnect IP in Chapter 3, and mention of SmartConnect IP
capabilities throughout the document.
Added AXI Verification IP in Chapter 3.
Added AXI4-Stream Verification IP in Chapter 3.
Added Zynq-7000 AP SoC Verification IP in Chapter 3.
Added Quick Take Videos.
Updated the AXI IP Catalog Figure 2-1.
Updated the IP Project Settings Packaging tab in Figure 2-6.
Changed Features and Limitations in AXI Infrastructure IP Cores.
Updated Vivado Lab Tools to Vivado Lab Edition throughout the document.
Added XAPP1231 document reference to additional resources.
Added direct links to destinations.
Corrected AWCACHE and ARCACHE for AXI4-Lite to “Signal not present” in
Appendix A, Write Data Channel Signals and Appendix A, Read Data Channel Signals.
Changed:
IP Interoperability. Using Vivado AXI IP in RTL Projects.
Using the Create and Package IP Wizard for AXI IP.
Using Vivado IP Integrator to Assemble AXI IP.
Adding AXI IP to the IP Catalog Using Vivado IP Packager.
Using AXI IP in System Generator for DSP.
Added:
Adding AXI Interfaces Using High Level Synthesis.
AXI Virtual FIFO Controller. DataMover
Simulating IP. Using Debug and IP.
Performance Monitor IP. AXI BFM.
Bus Functional Models.
Choosing a Programmable Logic Interface.
Zynq-7000 All Programmable SoC Processor IP.
MicroBlaze Processor.
Added: Migrating to AXI for IP Cores.
Migrating to AXI for IP Cores.
Migrating HDL Designs to use DSP IP with AXI4-Stream.
Migrating IP Using the Vivado Create and Package Wizard.
High End Verification Solutions.
Added Optimizing AXI on Zynq-7000 AP SoC Processors.
Initial release of Vivado AXI Reference Guide.
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
2
Send Feedback
Table of Contents
Chapter 1: Introducing AXI for Vivado
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
What is AXI? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Summary of AXI4 Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
How AXI Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IP Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Quick Take Videos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: AXI Support in Xilinx Tools and IP
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using Vivado AXI IP in RTL Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using the Create and Package IP Wizard for AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Adding AXI IP to the IP Catalog Using Vivado IP Packager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Using Vivado IP Integrator to Assemble AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Using AXI IP in System Generator for DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Adding AXI Interfaces Using High Level Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 3: Samples of Vivado AXI IP and Xilinx Processors
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AXI Infrastructure IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AXI4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Simulating IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Using Debug and IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Zynq UltraScale+ MPSoC Processor Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Zynq-7000 All Programmable SoC Processor IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MicroBlaze Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chapter 4: AXI Feature Adoption in Xilinx Devices
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Memory-Mapped IP Feature Adoption and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AXI4-Stream Adoption and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DSP and Wireless IP: AXI Feature Adoption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Video IP: AXI Feature Adoption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
3
Send Feedback
Chapter 5: Migrating to Xilinx AXI Protocols
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Migrating to AXI for IP Cores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Migrating IP Using the Vivado Create and Package Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Using System Generator for DSP for Migrating IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Migrating a Fast Simplex Link to AXI4-Stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Migrating HDL Designs to use DSP IP with AXI4-Stream. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
High End Verification Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 6: AXI System Optimization: Tips and Hints
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
AXI System Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
AXI4-based Vivado Multi-Ported Memory Controller: AXI4 System Optimization Example . . . . 126
Common Pitfalls Leading to AXI Systems of Poor Quality Results . . . . . . . . . . . . . . . . . . . . . . . . . 142
Optimizing AXI on Zynq-7000 AP SoC Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 7: AXI4-Stream IP Interoperability: Tips and Hints
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Key Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Domain Usage Guidelines and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Domain-Specific Data Interpretation and Interoperability Guidelines . . . . . . . . . . . . . . . . . . . . . 155
Appendix A: AXI Adoption Summary
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
AXI4 and AXI4-Lite Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
AXI4-Stream Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Appendix B: AXI Terminology
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Third-Party Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Xilinx Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Vivado Design Suite Video Tutorials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
4
Send Feedback
Introducing AXI for Vivado
Chapter 1
Overview
Xilinx adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property
(IP) cores beginning with the Xilinx® Spartan®-6 and Virtex®-6 devices. Xilinx continues
the use of the AXI protocol for IP targeting the UltraScale™ architecture, 7 series, and
Zynq®-7000 All Programmable (AP) SoC devices.
This document is intended to: Introduce key concepts of the AXI protocol.
Explain what features of AXI that have been adopted by Xilinx.
Provide guidance on how to migrate your existing design to AXI.
• Give an overview of what Xilinx tools you can use to create AXI-based IP.
•
•
Note: This document is not intended to replace the advanced micro controller bus architecture
(AMBA®) ARM® AXI4 specifications. Before beginning an AXI design, you need to download, read,
and understand the AMBA AXI and ACE Protocol Specification, along with the AMBA4 AXI4-Stream
Protocol. You might need to fill out a brief registration before downloading the documents. See the
AMBA website [Ref 1].
Note: The ACE portion of the AMBA specification is generally not used, except in special cases such
as the connection between a MicroBlaze™ processor and its associated system cache block.
What is AXI?
AXI is part of ARM AMBA, a family of micro controller buses first introduced in 1996. The
first version of AXI was first included in AMBA 3.0, released in 2003. AMBA 4.0, released in
2010, includes the second major version of AXI, AXI4.
There are three types of AXI4 interfaces:
• AXI4: For high-performance memory-mapped requirements.
• AXI4-Lite: For simple, low-throughput memory-mapped communication (for example,
to and from control and status registers).
• AXI4-Stream: For high-speed streaming data.
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
5
Send Feedback
Xilinx introduced these interfaces in the ISE® Design Suite, release 12.3. Xilinx continues to
use and support AXI and AXI4 interfaces in the Vivado® Design Suite.
Chapter 1:
Introducing AXI for Vivado
Summary of AXI4 Benefits
AXI4 is widely adopted in Xilinx product offerings, providing benefits to Productivity,
Flexibility, and Availability:
•
•
Productivity: By standardizing on the AXI interface, developers need to learn only a
single protocol for IP.
Flexibility: Providing the right protocol for the application:
°
°
°
AXI4 is for memory-mapped interfaces and allows high throughput bursts of up to
256 data transfer cycles with just a single address phase.
AXI4-Lite is a light-weight, single transaction memory-mapped interface. It has a
small logic footprint and is a simple interface to work with both in design and
usage.
AXI4-Stream removes the requirement for an address phase altogether and allows
unlimited data burst size. AXI4-Stream interfaces and transfers do not have address
phases and are therefore not considered to be memory-mapped.
• Availability: By moving to an industry-standard, you have access not only to the
Vivado IP Catalog, but also to a worldwide community of ARM partners.
° Many IP providers support the AXI protocol.
°
A robust collection of third-party AXI tool vendors is available that provide many
verification, system development, and performance characterization tools. As you
begin developing higher performance AXI-based systems, the availability of these
tools is essential.
How AXI Works
This section provides a brief overview of how the AXI interface works. Consult the AMBA AXI
specifications [Ref 1] for the complete details on AXI operation.
The AXI specifications describe an interface between a single AXI master and AXI slave,
representing IP cores that exchange information with each other. Multiple memory-mapped
AXI masters and slaves can be connected together using AXI infrastructure IP blocks. The
Xilinx AXI Interconnect IP and the newer AXI SmartConnect IP contain a configurable
number of AXI-compliant master and slave interfaces, and can be used to route transactions
between one or more AXI masters and slaves.
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
6
Send Feedback
Chapter 1:
Introducing AXI for Vivado
The AXI Interconnect is architected using a traditional, monolithic crossbar approach;
described in AXI Infrastructure IP Cores in Chapter 3. The newer SmartConnect IP, which was
production released in 2017.1, contains a more scalable and flexible Network-on-Chip
(NoC) architecture and is described in Xilinx AXI SmartConnect and AXI Interconnect IP in
Chapter 3.
Both AXI4 and AXI4-Lite interfaces consist of five different channels:
•
Read Address Channel
• Write Address Channel
Read Data Channel
•
• Write Data Channel
• Write Response Channel
Data can move in both directions between the master and slave simultaneously, and data
transfer sizes can vary. The limit in AXI4 is a burst transaction of up to 256 data transfers.
AXI4-Lite allows only one data transfer per transaction.
The following figure shows how an AXI4 read transaction uses the read address and read
data channels.
X-Ref Target - Figure 1-1
Address
and
control
Master
interface
Read address channel
Read data channel
Read
data
Read
data
Read
data
Read
data
Slave
interface
X12076
Figure 1-1: Channel Architecture of Reads
Figure 1-2 shows how a write transaction uses the write address, write data, and write
response channels.
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
7
Send Feedback
Chapter 1:
Introducing AXI for Vivado
X-Ref Target - Figure 1-2
Write address channel
Address
and
control
Write data channel
Master
interface
Write
data
Write
data
Write
data
Write
data
Slave
interface
Write response channel
Write
response
X12077
Figure 1-2: Channel Architecture of Writes
As shown in the preceding figures, AXI4:
•
•
Provides separate data and address connections for reads and writes, which allows
simultaneous, bidirectional data transfer.
Requires a single address and then bursts up to 256 words of data.
The AXI4 protocol describes options that allow AXI4-compliant systems to achieve very
high data throughput. Some of these features, in addition to bursting, are: data upsizing
and downsizing, multiple outstanding addresses, and out-of-order transaction processing.
At a hardware level, AXI4 allows systems to be built with a different clock for each AXI
master-slave pair. In addition, the AXI4 protocol allows the insertion of register slices (often
called pipeline stages) to aid in timing closure.
AXI4-Lite is similar to AXI4 with some exceptions: The most notable exception is that
bursting is not supported. The AXI4-Lite chapter of the ARM AMBA AXI Protocol
Specification [Ref 1] describes the AXI4-Lite protocol in more detail.
The AXI4-Stream protocol defines a single channel for transmission of streaming data. The
AXI4-Stream channel models the write data channel of AXI4. Unlike AXI4, AXI4-Stream
interfaces can burst an unlimited amount of data. There are additional, optional capabilities
described in the AMBA4 AXI4-Stream Protocol Specification [Ref 1]. The specification
describes how you can split, merge, interleave, upsize, and downsize AXI4-Stream
compliant interfaces.
IMPORTANT: Unlike AXI4, you cannot reorder AXI4-Stream transfers.
Vivado AXI Reference Guide
UG1037 (v4.0) July 15, 2017
www.xilinx.com
8
Send Feedback
相关推荐
2023年江西萍乡中考道德与法治真题及答案.doc
2012年重庆南川中考生物真题及答案.doc
2013年江西师范大学地理学综合及文艺理论基础考研真题.doc
2020年四川甘孜小升初语文真题及答案I卷.doc
2020年注册岩土工程师专业基础考试真题及答案.doc
2023-2024学年福建省厦门市九年级上学期数学月考试题及答案.doc
2021-2022学年辽宁省沈阳市大东区九年级上学期语文期末试题及答案.doc
2022-2023学年北京东城区初三第一学期物理期末试卷及答案.doc
2018上半年江西教师资格初中地理学科知识与教学能力真题及答案.doc
2012年河北国家公务员申论考试真题及答案-省级.doc
2020-2021学年江苏省扬州市江都区邵樊片九年级上学期数学第一次质量检测试题及答案.doc
2022下半年黑龙江教师资格证中学综合素质真题及答案.doc
