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JESD204B英文原版.pdf
SERIAL INTERFACE FOR DATA CONVERTERS
1 Scope
2 References
2.1 Normative
2.2 Informative
3 Terminology
3.1 Terms and definitions
3.1 Terms and definitions (cont’d)
3.1 Terms and definitions (cont’d)
3.1 Terms and definitions (cont’d)
3.2 Meaning of symbols and abbreviations
3.2 Meaning of symbols and abbreviations (cont’d)
Table 1 — Special symbols and operators
4 Electrical specification
4.1 Electrical specification overview
4.1 Electrical specification overview (cont’d)
4.2 Compliance types
4.3 Interconnect
4.3.1 Interconnect Insertion Loss
4.3.1 Interconnect Insertion Loss (cont’d)
4.4 LV-OIF-SxI5 Data interface signals (Differential)
4.4.1 Compliance verification
4.4.2 LV-OIF-SxI5 Transmitter Electrical Specifications
Table 2 — General differential output DC and AC characteristics for LV-OIF-SxI5 – based operation
4.4.2 LV-OIF-SxI5 Transmitter Electrical Specifications (cont’d)
4.4.3 LV-OIF-SxI5 Receiver Electrical Specifications
4.4.3 LV-OIF-SxI5 Receiver Electrical Specifications (cont’d)
4.5 LV-OIF-6G-SR Data interface signals (Differential)
4.5.1 Compliance verification
4.5.2 LV-OIF-6G-SR Transmitter Electrical specifications
Table 4 — General differential output DC and AC characteristics for LV-OIF-6G-SR – based operation
4.5.2 LV-OIF-6G-SR Transmitter Electrical specifications (cont’d)
4.5.3 LV-OIF-6G-SR Receiver specifications
Table 5 — General Differential Input DC and AC Characteristics for LV-OIF-6G-SR – based operation
4.5.3 LV-OIF-6G-SR Receiver specifications (cont’d)
4.6 LV-OIF-11G-SR Data interface signals (Differential)
4.6.1 Compliance verification
4.6.2 LV-OIF-11G-SR Transmitter Electrical specifications
Table 6 — General differential output DC and AC characteristics for LV-OIF-11G-SR – based operation
4.6.2 LV-OIF-11G-SR Transmitter Electrical specifications (cont’d)
4.6.3 LV-OIF-11G-SR Receiver specifications
Table 7 — General Differential Input DC and AC Characteristics for LV-OIF-11G-SR – based operation
4.6.3 LV-OIF-11G-SR Receiver specifications (cont’d)
4.7 Device clock
4.8 Frame Clock, and Local Multiframe Clock
4.8 Frame Clock, and Local Multiframe Clock (cont’d)
4.9 SYNC interface
4.9 SYNC interface (cont’d)
4.9 SYNC interface (cont’d)
4.10 Lane-to-lane inter-device synchronization interface
4.11 SYSREF signal (Device Subclass 1)
4.11 SYSREF signal (Device Subclass 1) (cont’d)
4.12 Skew and misalignment budget
4.12 Skew and misalignment budget (cont’d)
4.12 Skew and misalignment budget (cont’d)
4.12 Skew and misalignment budget (cont’d)
4.12 Skew and misalignment budget (cont’d)
4.12 Skew and misalignment budget (cont’d)
4.12 Skew and misalignment budget (cont’d)
4.12 Skew and misalignment budget (cont’d)
4.13 Control Interfaces (informative)
5 Data stream
5.1 Transport layer
5.1.1 Overview
5.1.2 User data format for an independent lane
5.1.2.1 User data mapping without oversampling
5.1.2.1 User data mapping without oversampling (cont’d)
5.1.2.1 User data mapping without oversampling (cont’d)
5.1.3 User data format for multiple lanes
5.1.3 User data format for multiple lanes
5.1.3 User data format for multiple lanes (cont’d)
5.1.4 Tail bits
5.1.5 Idle mode
5.1.5.1 General
5.1.5.2 Dummy samples
5.1.6 Test modes (transport layer)
5.1.6.1 General
5.1.6.2 Short transport layer test pattern
5.1.6.3 Long transport layer test pattern
5.2 Scrambling
5.2.1 Scrambler polynomial
5.2.2 Scrambler bit order
5.2.3 Scrambler type
5.2.3 Scrambler type (cont’d)
5.2.4 Early synchronization option
/
5.2.5 Initial state
5.2.6 Scrambling disable
5.3 Data Link Layer
5.3.1 8B/10B encoding
5.3.2 Transmission order
5.3.3 Link operation
5.3.3.1 Code group synchronization
5.3.3.1 Code group synchronization (cont’d)
5.3.3.2 SYNC~ signal combining
5.3.3.2 SYNC~ signal combining (cont’d)
5.3.3.3 Initial frame synchronization
5.3.3.4 Frame alignment monitoring and correction
5.3.3.4.1 Alignment characters
5.3.3.4.2 Character replacement without scrambling
5.3.3.4.3 Character replacement with scrambling
5.3.3.4.4 Frame alignment correction in the RX
5.3.3.5 Initial lane synchronization
5.3.3.5 Initial lane synchronization (cont’d)
5.3.3.6 Lane alignment monitoring and correction
5.3.3.7 Link re-initialization
5.3.3.7 Link re-initialization (cont’d)
5.3.3.8 Test modes
5.3.3.8.1 General
5.3.3.8.2 Test sequences
5.3.3.8.2 Test sequences (cont’d)
6.1 Introduction
6.1 Introduction (cont’d)
6.2 No Support for Determisitic Latency (Device Subclass 0) (Informative)
6.3 Deterministic Latency Using SYSREF (Device Subclass 1)
6.3 Deterministic Latency Using SYSREF (Device Subclass 1) (cont’d)
6.3 Deterministic Latency Using SYSREF (Device Subclass 1) (cont’d)
6.3 Deterministic Latency Using SYSREF (Device Subclass 1) (cont’d)
6.4 Deterministic Latency Using SYNC~ Detection (Device Subclass 2)
6.4 Deterministic Latency Using SYNC~ Detection (Device Subclass 2)
6.4.1 Principles of SYNC~ sampling
6.4.1.1 SYNC~ generation at the RX device
6.4.1.2 Adjustment resolution and adjustment clock
6.4.1.2 Adjustment resolution and adjustment clock (cont’d)
6.4.1.3 Detection resolution at the TX device
6.4.1.4 SYNC~ de-assertion detection and the detection interval
6.4.1.4 SYNC~ de-assertion detection and the detection interval (cont’d)
6.4.2 Master and slave configurations
6.4.2.1 ADC Master and slave configuration
6.4.2.1 ADC Master and slave configuration (cont’d)
6.4.2.2 DAC master and slave configurations
6.4.2.2 DAC master and slave configurations (cont’d)
6.4.2.2 DAC master and slave configurations (cont’d)
6.4.2.2 DAC master and slave configurations (cont’d)
Loop initialization
Latency monitoring:
6.4.3 Summary of requirements for subclass 2 deterministic latency
General requirements for support of subclass 2 protocol.
Requirement for subclass 2 TX converter devices.
Requirement for subclass 2 RX converter devices.
Requirement for a TX logic device for subclass 2 support.
6.5 Interoperability Between JESD204A and JESD204B Devices
7 Receiver Operation
7.1 Code group synchronization
7.1 Code group synchronization (cont’d)
7.2 Initial frame synchronization
7.2 Initial frame synchronization (cont’d)
7.3 Frame alignment monitoring and correction
7.3 Frame alignment monitoring and correction (cont’d)
7.4 Initial lane synchronization
7.5 Lane alignment monitoring and correction
7.5 Lane alignment monitoring and correction (cont’d)
7.6 Error handling
7.6.1 Error kinds
7.6.2 Data output on error
7.6.4 Error reporting via SYNC interface
7.6.5 Error reporting via control interface
8.1 Synchronization
8.1 Synchronization (cont’d)
8.2 Initial lane alignment sequence
8.3 Link configuration data and encoding
8.3 Link configuration data and encoding
8.3 Link configuration data and encoding (cont’d)
8.4 SYNC signal decoding
8.4 SYNC signal decoding (cont’d)
8.5 SYNC~ detection (device subclass 2)
9 Device classification
9.1 Device Subclassification
Annex A (informative) Differences between JESD204B.01 and JESD204B
3.2 Meaning of symbols and abbreviations
Annex A (informative) Differences between JESD204B and JESD204A (cont’d)
4.2 Compliance types
4.3 Interconnect
4.3.1 Interconnect Insertion Loss
4.4 LV-OIF-SxI5 Data interface signals (Differential)
4.4.1 Compliance verification
4.4.2 LV-OIF-SxI5 Transmitter Electrical Specifications
4.4.3 LV-OIF-SxI5 Receiver Electrical Specifications
4.5 LV-OIF-6G-SR Data interface signals (Differential)
4.6 LV-OIF-11G-SR Data interface signals (Differential)
4.7 Device clock
4.8 Frame Clock, and Local Multiframe Clock.
4.9 SYNC interface
Annex A (informative) Differences between JESD204B and JESD204A (cont’d)
4.10 Lane-to-lane inter-device synchronization interface
4.11 SYSREF signal (Device Subclass 1)
4.12 Skew and misalignment budget
4.13 Control Interfaces (informative)
5.1.2 User data format for an independent lane
5.1.3 User data format for multiple lanes
5.1.6 Test modes (transport layer)
5.1.6.1 General
5.1.6.2 Short transport layer test pattern
5.1.6.3 Long transport layer test pattern
5.2 Scrambling
Annex A (informative) Differences between JESD204B and JESD204A (cont’d)
5.2.6 Scrambling disable
5.3.3.1 Code group synchronization
5.3.3.4.2 Character replacement without scrambling
5.3.3.4.3 Character replacement with scrambling
5.3.3.4.4 Frame alignment correction in the RX
5.3.3.5 Initial lane synchronization
5.3.3.6 Lane alignment monitoring and correction
5.3.3.7 Link re-initialization
5.3.3.8 Test modes
5.3.3.8.2 Test sequences
6 Deterministic Latency
7 Receiver Operation
Annex A (informative) Differences between JESD204B and JESD204A (cont’d)
7.1 Code group synchronization
7.4 Initial lane synchronization
7.5 Lane alignment monitoring and correction
7.6.4 Error reporting via SYNC interface
8 Transmitter Operation
8.1 Synchronization
8.2 Initial lane alignment sequence
8.3 Link configuration data and encoding
8.4 SYNC signal decoding
8.5 SYNC~ detection (device subclass 2)
Annex A (informative) Differences between JESD204B and JESD204A (cont’d)
9 Device classification
9.1 Device Subclassification
Annex B (informative) Application overview
Annex C (informative) Device level implementation
Annex E (informative) Instructions for Determining Linear Fitted Insertion Loss
Annex F (informative) Example of device clock and SYSREF generation
Annex G (informative) Clock Terminology
Annex B (informative) Application overview
B.1 Background
B.2 Link properties
B.3 Variants and modes
B.4 Configuration examples
B.4.1 General
B.4.2 Single Device ADC Application
B.4.3 Single Device DAC Application
B.4.4 Multiple Device ADC Application
B.4.5 Multiple Device DAC Application
B.4.6 Interface for Decimating or Oversampled ADC
B.4.7 Interface for Interpolating or Oversampled DAC
Annex C (informative) Device level implementation
C.1 Transmitter block
C.1.1 Generic structure
C.1.2 TX Link Layer
C.1.3 TX Physical Layer
C.2 Receiver block
C.2.1 Generic structure
C.2.2 RX Link Layer
C.2.3 RX Physical Layer
Annex E (informative) Instructions for Determining Linear Fitted Insertion Loss
Annex F (informative) Example of device clock and SYSREF generation
Annex G (informative) Clock Terminology
Standard Improvement Form JEDEC JESD204B.01
Table 21
JEDEC
STANDARD
Serial Interface for Data Converters
JESD204B.01
(Revision of JESD204B, July 2011)
JANUARY 2012
JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
NOTICE
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SERIAL INTERFACE FOR DATA CONVERTERS
Scope
(From JEDEC Board Ballot JCB-08-01 and JCB-11-47, formulated under the cognizance of JC-16
Committee on Interface Technology.)
1
This specification describes a serialized interface between data converters and logic devices. It contains
normative information to enable designers to implement devices that communicate with other devices
covered by this specification. Informative annexes are included to clarify and exemplify the specification.
Due to the range of applications involved, the intention of the document is to completely specify only the
serial data interface and the link protocol. Certain signals common to both the interface and the function
of the device, such as device clocks and control interfaces, have application-dependent requirements.
Devices may also have application-dependent modes, such as a low power / shutdown mode that will
affect the interface. In these instances, the specification merely constrains other device properties as they
relate to the interface, and leaves the specific implementation up to the designer.
Revision A of the standard was expanded to support serial data interfaces consisting of single or multiple
lanes per converter device. In addition, converter functionality (ADC or DAC) can be distributed over
multiple devices:
• All parallel running devices are implemented or specified to run synchronously with each other using
JEDEC Standard No. 204B.01
Page 1
the same data format.
• Normally this means that they are part of the same product family.
Revision B of the standard now supports the following additional functions:
• Mechanism for achieving repeatable, programmable deterministic delay across the JESD204 link.
• Support for serial data rates up to 12.5 Gbps.
• Transition from using frame clock as the main clock source to using device clock as the main clock
source. Device clock frequency requirements offer much more flexibility compared to requiring a
frame clock input.
The logic device (e.g. ASIC or FPGA) is always assumed to be a single device.
Figure 1 compares the scope of the original JESD204 specification and its revisions.
JEDEC Standard No. 204B.01
Page 2
1
Scope (cont’d)
Original JESD204 version 2006
Logic
Device
(FPGA or
ASIC)
1 lane,
1 link
M
converters
Frame
clock
JESD204 revision A
One multipoint link.
All lanes aligned.
1 link,
L lanes
1 link,
L lanes
Logic
Device
(FPGA or
ASIC)
Similar
converters
M
converters
M
converters
Frame
clock
Frame
clock
JESD204 revision B
Frame
clock
Similar
converters
M
converters
M
converters
Device
clock 1
One multipoint link.
All lanes aligned.
1 link,
L lanes
1 link,
L lanes
Logic
Device
(FPGA or
ASIC)
Device
clock 2
Figure 1 — Scope of original JESD204 and revisions A and B
Although not illustrated in the figure, it is possible to apply multiple, independent instances of the
JESD204 standard to the same device.
JEDEC Standard No. 204B.01
Page 3
Normative
References
2
2.1
The following normative documents contain provisions that, through reference in this text, constitute
provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these
publications do not apply. However, parties to agreements based on this standard are encouraged to
investigate the possibility of applying the most recent editions of the normative documents indicated
below. For undated references, the latest edition of the normative document referred to applies.
1. IEEE Std 802.3-2008®, Part 3, Section Three, Local and metropolitan area networks - CSMA/CD
access methods and Physical Layer specifications, 2008. http://standards.ieee.org/getieee802/
2. JEDEC JESD99, Terms, Definitions, and Letter Symbols for Microelectronic Devices.
3. OIF-SxI-5-01.0, System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 –
3.125Gbps Parallel Interfaces, Optical Internetworking Forum, October 2002.
www.oiforum.com/public/documents/OIF-SxI5-01.0.pdf
4. OIF-CEI-02.0, Common Electrical I/O- Electrical and Jitter Interoperability agreements for 6G+ bps
and 11G+ bps I/O, Optical Internetworking Forum, February 2005.
www.oiforum.com/public/documents/OIF_CEI_02.0.pdf
Informative
2.2
The following standards contain provisions that, through references in the text, are informative in this
standard.
5. ANSI T1.523-2001, ATIS Telecom Glossary 2000, February 2001. http://www.atis.org/tg2k/
6. IEEE Std 802.3-2008®, Part 3, Section Four, Local and metropolitan area networks - CSMA/CD
access methods and Physical Layer specifications, 2008. http://standards.ieee.org/getieee802/
7. ANSI/IEEE Std 91a-1991, Graphic symbols for logic functions, IEEE 1991, ANSI 1994. (Summary
available at e.g. http://en.wikipedia.org/wiki/Logic_gate)
8. INCITS 450-2009, Information technology - Fibre Channel - Physical Interface - 4 (FC-PI-4),
available from http://webstore.ansi.org
9. INCITS TR-35-2004 (R2009), Fibre Channel - Methodologies for Jitter and Signal Quality
Specification (FC-MJSQ) , available from http://webstore.ansi.org
Terminology
Terms and definitions
JEDEC Standard No. 204B.01
Page 4
3
For the purposes of this standard, the terms and definitions given in JESD99 (reference 2) and the
following apply:
3.1
8B/10B code: A DC-balanced octet-oriented data encoding specified in reference 1, clause 36.2.4. (Ref.
IEEE 802.3)
ceil(x): The smallest integer greater than or equal to x.
character: A symbol produced by 8B/10B encoding of an octet.
NOTE 1 While all octets can be encoded as data characters, certain octets can also be encoded as control
characters.
NOTE 2 The same character may exist as two different code groups, depending on running disparity.
character clock: A signal used for sequencing the 8B/10B characters or octets.
clock generator: A circuit used to generate synchronous, phase aligned device clocks to various devices
in the JESD204B system.
NOTE A clock generator circuit can include one or more clock generator devices, but they must use a common
source clock.
code group: A set of ten bits that, when representing data, conveys an octet. (Ref. IEEE 802.3)
control interface: An application-specific interface used to pass information (usually status and control
information) between a converter device and a logic device and/or between a device and a higher layer
application level.
NOTE The details of the control interface are outside the scope of the serial interface described by this standard.
conversion clock: A signal used to define the analog sampling moments in a converter.
NOTE Usually the conversion clock is the same as the sample clock, except in case of interpolating DACs or
decimating ADCs, where the conversion clock is faster than the sample clock. In all cases, the conversion clock is
derived from the device clock.
converter: An analog-to-digital converter (ADC) or digital-to-analog converter (DAC).
NOTE
converter device: A component package containing one or more converters.
NOTE This standard specifies the interactions between one logic device and one or more converter devices.
In this standard, a converter is assumed to interface via a single stream of digital samples.
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