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EDA课设出租车计价器程序.doc
1、速度控制模块如右
Speed 程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY speed IS
PORT(
clk,reset,start
: IN
STD_LOGIC;
k : IN
STD_LOGIC_VECTOR(4 downto 0);
clkout : OUT STD_LOGIC);
END speed;
ARCHITECTURE a OF speed IS
--SIGNAL count1 : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL tempclk
SIGNAL kinside : STD_LOGIC_VECTOR(4 downto 0);
: STD_LOGIC;
BEGIN
kinside<="00000"-k;
clks_label:
PROCESS (reset,clk,start)
variable count2 : STD_LOGIC_VECTOR(4 downto 0);
BEGIN
IF reset='1' THEN
count2:="00000";
ELSIF clk'event and clk='1' THEN
if start='1'then
then count2:="00000";
if count2=kinside
end if;
if not (k="00000") then count2:=count2+1; end if;
if count2="00001" then tempclk<=not tempclk; end if;
end if;
END IF;
END PROCESS clks_label;
clkout<=tempclk;
END a;
2、路程显示模块如右
Odemeter 程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity odometer
port (
clk,reset :in std_logic;
is
count1 :out std_logic_vector (3 downto 0);
count2 :out std_logic_vector (3 downto 0);
count3 :out std_logic_vector (3 downto 0);
count4 :out std_logic_vector (3 downto 0));
end odometer ;
architecture aa of odometer is
begin
process(clk,reset)
variable mm : std_logic_vector (15 downto 0);
begin
if reset='1' then
mm:="0000000000000000";
elsif clk'event and clk='1' then
if mm(3 downto 0)="1001" then
mm:=mm+7;else mm:=mm+1;
end if;
if mm(7 downto 4)="1010" then
mm:=mm+"0000000001100000";
end if;
if mm(11 downto 8)="1010" then
mm:=mm+"0000011000000000";
end if;
end if;
count1<=mm(3 downto 0);
count2<=mm(7 downto 4);
count3<=mm(11 downto 8);
count4<=mm(15 downto 12);
end process;
end aa;
3、动态扫描模块如右
Sao 程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY sao IS
PORT(
clk
S8
S7
S6
S5
: IN
: IN
: IN
: IN
: IN
STD_LOGIC;
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
: IN
: IN
: IN
: IN
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
STD_LOGIC_VECTOR(3 downto 0);
S4
S3
S2
S1
choice : OUT STD_LOGIC_VECTOR(7 downto 0);
data
: OUT STD_LOGIC_VECTOR(7 downto 0));
END sao;
ARCHITECTURE art OF sao IS
SIGNAL count : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL temp : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL choicein, datain
: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
P1_PROC:
PROCESS (clk)
BEGIN
IF clk'event and clk='1' THEN
count="111" then count<="000";
if
else count<=count+1;
end if;
END IF;
END PROCESS P1_PROC;
P2_PROC:
PROCESS (clk)
BEGIN
if clk'event and clk='1' then
choice<=choicein;
data(7 downto 1)<=datain(7 downto 1);
if( count="101" or count="010" )then data(0)<= '1';
else data(0)<='0';
end if;
end if;
END PROCESS P2_PROC;
choicein<="00000001" when count="000" else
"00000010" when count="001" else
"00000100" when count="010" else
"00001000" when count="011" else
"00010000" when count="100" else
"00100000" when count="101" else
"01000000" when count="110" else
"10000000";
temp<=
S1 when count="000" else
S2 when count="001" else
S3 when count="010" else
S4 when count="011" else
S5 when count="100" else
S6 when count="101" else
S7 when count="110" else
S8;
WITH temp select
datain <= "11111100" WHEN "0000",
"01100000" WHEN "0001",
"11011010" WHEN "0010",
"11110010" WHEN "0011",
"01100110" WHEN "0100",
"10110110" WHEN "0101",
"10111110" WHEN "0110",
"11100000" WHEN "0111",
"11111110" WHEN "1000",
"11110110" WHEN "1001",
"11101110" WHEN "1010",
"00111110" WHEN "1011",
"10011100" WHEN "1100",
"01111010" WHEN "1101",
"10011110" WHEN "1110",
"10001110" WHEN OTHERS;
END art;
4、计费显示模块如右
Moneyshow 程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity moneyshow is
port (
clk,reset:in std_logic;
judge2 :in std_logic_vector (3 downto 0);
judge3 :in std_logic_vector (3 downto 0);
judge4 :in std_logic_vector (3 downto 0);
count1 :out std_logic_vector(3 downto 0);
count2 :out std_logic_vector(3 downto 0);
count3 :out std_logic_vector(3 downto 0);
count4 :out std_logic_vector(3 downto 0));
end moneyshow ;
architecture aa of moneyshow is
: std_logic;
signal en
signal money
: std_logic_vector(11 downto 0);
signal mcount : std_logic_vector(15 downto 0);
begin
money<="00011001" when mcount < "0011001100100000" else
"01010010" when mcount >="0011001100100000" else
"00000000";
en<='0' when judge4="0000" and judge3="0000" and judge2(3 downto 2)="00" and
((judge2(1)='0') or (judge2(1)='1' and judge2(0)='0')) else
'1';
process(clk,reset)
variable mm : std_logic_vector (15 downto 0);
begin
if reset='1' then
mm:="0000100000000000";
elsif clk'event and clk='1' then
if en='1' then mm:=mm+money; end if;
if mm(3)='1' and (not(mm(2 downto 1)="00")) then
mm:=mm+6; end if;
if mm(7)='1' and (not(mm(6 downto 5)="00")) then
mm:=mm+"01100000"; end if;
if mm(11)='1' and (not(mm(10 downto 9)="00")) then
mm:=mm+"011000000000"; end if;
if mm(15)='1' and (not(mm(14 downto 13)="00")) then
mm:=mm+"0110000000000000"; end if;
end if;
count1<=mm(3 downto 0);
count2<=mm(7 downto 4);
count3<=mm(11 downto 8);
count4<=mm(15 downto 12);
mcount<=mm;
end process;
end aa;
5、计数显示模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity cdu99 is
port (
clk,reset:in
std_logic;
count1 :out std_logic_vector (3 downto 0);
count2 :out std_logic_vector (3 downto 0);
count3 :out std_logic_vector (3 downto 0));
end cdu99 ;
architecture aa of cdu99 is
begin
process(clk,reset)
variable mm : std_logic_vector (11 downto 0);
begin
if reset='1' then
mm:="000000000000";
elsif clk'event and clk='1' then
if mm(3 downto 0)="1001" then
mm:=mm+7;else mm:=mm+1; end if;
if mm(7 downto 4)="1010" then
mm:=mm+"01100000"; end if;
end if;
count1<=mm(3 downto 0);
count2<=mm(7 downto 4);
count3<=mm(11 downto 8);
end process;
end aa;
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