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TMS320C6678数据手册.pdf
1 TMS320C6678 Features and Description
1.1 Features
1.2 Applications
1.3 KeyStone Architecture
1.4 Device Description
1.5 Functional Block Diagram
1.6 Release History
Contents
List of Figures
List of Tables
2 Device Overview
2.1 Device Characteristics
2.2 DSP Core Description
2.3 Memory Map Summary
2.4 Boot Sequence
2.5 Boot Modes Supported and PLL Settings
2.5.1 Boot Device Field
2.5.2 Device Configuration Field
2.5.2.1 No Boot/ EMIF16 Boot Device Configuration
2.5.2.2 Serial Rapid I/O Boot Device Configuration
2.5.2.3 Ethernet (SGMII) Boot Device Configuration
2.5.2.4 PCI Boot Device Configuration
2.5.2.5 I2C Boot Device Configuration
2.5.2.6 SPI Boot Device Configuration
2.5.2.7 HyperLink Boot Device Configuration
2.5.3 Boot Parameter Table
2.5.3.1 EMIF16 Boot Parameter Table
2.5.3.2 SRIO Boot Parameter Table
2.5.3.3 Ethernet Boot Parameter Table
2.5.3.4 PCIe Boot Parameter Table
2.5.3.5 I2C Boot Parameter Table
2.5.3.6 SPI Boot Parameter Table
2.5.3.7 HyperLink Boot Parameter Table
2.5.3.8 DDR3 Configuration Table
2.5.4 PLL Boot Configuration Settings
2.6 Second-Level Bootloaders
2.7 Terminals
2.7.1 Package Terminals
2.7.2 Pin Map
2.8 Terminal Functions
2.9 Development and Support
2.9.1 Development Support
2.9.2 Device Support
2.9.2.1 Device and Development-Support Tool Nomenclature
2.10 Related Documentation from Texas Instruments
3 Device Configuration
3.1 Device Configuration at Device Reset
3.2 Peripheral Selection After Device Reset
3.3 Device State Control Registers
3.3.1 Device Status Register
3.3.2 Device Configuration Register (DEVCFG)
3.3.3 JTAG ID Register (JTAGID) Description
3.3.4 Kicker Mechanism Register (KICK0 and KICK1)
3.3.5 DSP Boot Address Register (DSP_BOOT_ADDRn)
3.3.6 LRESETNMI PIN Status Register (LRSTNMIPINSTAT)
3.3.7 LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)
3.3.8 Reset Status Register (RESET_STAT)
3.3.9 Reset Status Clear Register (RESET_STAT_CLR)
3.3.10 Boot Complete Register (BOOTCOMPLETE)
3.3.11 Power State Control Register (PWRSTATECTL)
3.3.12 NMI Event Generation to CorePac Register (NMIGRx)
3.3.13 IPC Generation Registers (IPCGRx)
3.3.14 IPC Acknowledgement Registers (IPCARx)
3.3.15 IPC Generation Host Register (IPCGRH)
3.3.16 IPC Acknowledgement Host Register (IPCARH)
3.3.17 Timer Input Selection Register (TINPSEL)
3.3.18 Timer Output Selection Register (TOUTPSEL)
3.3.19 Reset Mux Register (RSTMUXx)
3.3.20 DSP Suspension Control Register (DSP_SUSP_CTL)
3.3.21 Device Speed Register (DEVSPEED)
3.3.22 Chip Miscellaneous Control Register (CHIP_MISC_CTL)
3.4 Pullup/Pulldown Resistors
4 System Interconnect
4.1 Internal Buses and Switch Fabrics
4.2 Switch Fabric Connections
4.3 Bus Priorities
5 C66x CorePac
5.1 Memory Architecture
5.1.1 L1P Memory
5.1.2 L1D Memory
5.1.3 L2 Memory
5.1.4 MSM SRAM
5.1.5 L3 Memory
5.2 Memory Protection
5.3 Bandwidth Management
5.4 Power-Down Control
5.5 C66x CorePac Revision
5.6 C66x CorePac Register Descriptions
6 Device Operating Conditions
6.1 Absolute Maximum Ratings
6.2 Recommended Operating Conditions
6.3 Electrical Characteristics
6.4 Power Supply to Peripheral I/O Mapping
7 Peripheral Information and Electrical Specifications
7.1 Parameter Information
7.1.1 Timing Parameters and Board Routing Analysis
7.1.2 1.8-V LVCMOS Signal Transition Levels
7.2 Recommended Clock and Control Signal Transition Behavior
7.3 Power Supplies
7.3.1 Power-Supply Sequencing
7.3.1.1 Core-Before-IO Power Sequencing
7.3.1.2 IO-Before-Core Power Sequencing
7.3.1.3 Prolonged Resets
7.3.1.4 Clocking During Power Sequencing
7.3.2 Power-Down Sequence
7.3.3 Power Supply Decoupling and Bulk Capacitors
7.3.4 SmartReflex
7.4 Power Sleep Controller (PSC)
7.4.1 Power Domains
7.4.2 Clock Domains
7.4.3 PSC Register Memory Map
7.5 Reset Controller
7.5.1 Power-on Reset
7.5.2 Hard Reset
7.5.3 Soft Reset
7.5.4 Local Reset
7.5.5 Reset Priority
7.5.6 Reset Controller Register
7.5.7 Reset Electrical Data / Timing
7.6 Main PLL and PLL Controller
7.6.1 Main PLL Controller Device-Specific Information
7.6.1.1 Internal Clocks and Maximum Operating Frequencies
7.6.1.2 Main PLL Controller Operating Modes
7.6.1.3 Main PLL Stabilization, Lock, and Reset Times
7.6.2 PLL Controller Memory Map
7.6.2.1 PLL Secondary Control Register (SECCTL)
7.6.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
7.6.2.3 PLL Controller Clock Align Control Register (ALNCTL)
7.6.2.4 PLLDIV Divider Ratio Change Status Register (DCHANGE)
7.6.2.5 SYSCLK Status Register (SYSTAT)
7.6.2.6 Reset Type Status Register (RSTYPE)
7.6.2.7 Reset Control Register (RSTCTRL)
7.6.2.8 Reset Configuration Register (RSTCFG)
7.6.2.9 Reset Isolation Register (RSISO)
7.6.3 Main PLL Control Register
7.6.4 Main PLL and PLL Controller Initialization Sequence
7.6.5 Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Electrical Data/Timing
7.7 DD3 PLL
7.7.1 DDR3 PLL Control Register
7.7.2 DDR3 PLL Device-Specific Information
7.7.3 DDR3 PLL Initialization Sequence
7.7.4 DDR3 PLL Input Clock Electrical Data/Timing
7.8 PASS PLL
7.8.1 PASS PLL Control Register
7.8.2 PASS PLL Device-Specific Information
7.8.3 PASS PLL Initialization Sequence
7.8.4 PASS PLL Input Clock Electrical Data/Timing
7.9 Enhanced Direct Memory Access (EDMA3) Controller
7.9.1 EDMA3 Device-Specific Information
7.9.2 EDMA3 Channel Controller Configuration
7.9.3 EDMA3 Transfer Controller Configuration
7.9.4 EDMA3 Channel Synchronization Events
7.10 Interrupts
7.10.1 Interrupt Sources and Interrupt Controller
7.10.2 CIC Registers
7.10.2.1 CIC0/CIC1 Register Map
7.10.2.2 CIC2 Register Map
7.10.2.3 CIC3 Register Map
7.10.3 Inter-Processor Register Map
7.10.4 NMI and LRESET
7.10.5 External Interrupts Electrical Data/Timing
7.10.6 Host Interrupt Output
7.11 Memory Protection Unit (MPU)
7.11.1 MPU Registers
7.11.1.1 MPU Register Map
7.11.1.2 Device-Specific MPU Registers
7.11.2 MPU Programmable Range Registers
7.11.2.1 Programmable Range n Start Address Register (PROGn_MPSAR)
7.11.2.2 Programmable Range n End Address Register (PROGn_MPEAR)
7.11.2.3 Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)
7.11.2.4 MPU Registers Reset Values
7.12 DDR3 Memory Controller
7.12.1 DDR3 Memory Controller Device-Specific Information
7.12.2 DDR3 Memory Controller Race Condition Consideration
7.12.3 DDR3 Memory Controller Electrical Data/Timing
7.13 I2C Peripheral
7.13.1 I2C Device-Specific Information
7.13.2 I2C Peripheral Register Description(s)
7.13.3 I2C Electrical Data/Timing
7.13.3.1 Inter-Integrated Circuits (I2C) Timing
7.14 SPI Peripheral
7.14.1 SPI Electrical Data/Timing
7.14.1.1 SPI Timing
7.15 HyperLink Peripheral
7.15.1 HyperLink Device-Specific Interrupt Event
7.15.2 HyperLink Electrical Data/Timing
7.16 UART Peripheral
7.17 PCIe Peripheral
7.18 TSIP Peripheral
7.18.1 TSIP Electrical Data/Timing
7.19 EMIF16 Peripheral
7.19.1 EMIF16 Electrical Data/Timing
7.20 Packet Accelerator
7.21 Security Accelerator
7.22 Gigabit Ethernet (GbE) Switch Subsystem
7.23 Management Data Input/Output (MDIO)
7.24 Timers
7.24.1 Timers Device-Specific Information
7.24.2 Timers Electrical Data/Timing
7.25 Serial RapidIO (SRIO) Port
7.26 General-Purpose Input/Output (GPIO)
7.26.1 GPIO Device-Specific Information
7.26.2 GPIO Electrical Data/Timing
7.27 Semaphore2
7.28 Emulation Features and Capability
7.28.1 Advanced Event Triggering (AET)
7.28.2 Trace
7.28.2.1 Trace Electrical Data/Timing
7.28.3 IEEE 1149.1 JTAG
7.28.3.1 IEEE 1149.1 JTAG Compatibility Statement
7.28.3.2 JTAG Electrical Data/Timing
8 Revision History
9 Mechanical Data
9.1 Thermal Data
9.2 Packaging Information
Multicore Fixed and Floating-Point Digital Signal Processor
Check for Evaluation Modules (EVM): TMS320C6678
TMS320C6678
SPRS691E—November 2010—Revised March 2014
1 TMS320C6678 Features and Description
1.1 Features
• Eight TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each with
– 1.0 GHz, 1.25 GHz, or 1.4 GHz C66x
Fixed/Floating-Point CPU Core
› 44.8 GMAC/Core for Fixed Point @ 1.4 GHz
› 22.4 GFLOP/Core for Floating Point @ 1.4 GHz
– Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 512K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 4096KB MSM SRAM Memory Shared by Eight DSP
C66x CorePacs
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1-Gbps Wire-Speed Throughput at 1.5 MPackets
Per Second
– Security Accelerator Engine Enables Support for
›
IPSec, SRTP, 3GPP, WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,
GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,
SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
• Peripherals
– Four Lanes of SRIO 2.1
› 1.24/2.5/3.125/5 GBaud Operation Supported Per
Lane
› Supports Direct I/O, Message Passing
› Supports Four 1×, Two 2×, One 4×, and Two 1× +
One 2× Link Configurations
– PCIe Gen2
› Single Port Supporting 1 or 2 Lanes
› Supports Up To 5 GBaud Per Lane
– HyperLink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 50 Gbaud
– Gigabit Ethernet (GbE) Switch Subsystem
› Two SGMII Ports
› Supports 10/100/1000 Mbps Operation
– 64-Bit DDR3 Interface (DDR3-1600)
› 8G Byte Addressable Memory Space
– 16-Bit EMIF
– Two Telecom Serial Ports (TSIP)
› Supports 1024 DS0s Per TSIP
› Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps
Per Lane
– UART Interface
– I2C Interface
– 16 GPIO Pins
– SPI Interface
– Semaphore Module
– Sixteen 64-Bit Timers
– Three On-Chip PLLs
• Commercial Temperature:
– 0°C to 85°C
• Extended Temperature:
– -40°C to 100°C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
1.2 Applications
• Mission-Critical Systems
• High-Performance Computing Systems
• Communications
• Audio
• Video Infrastructure
•
Imaging
• Analytics
• Networking
• Media Processing
•
• Automation and Process Control
Industrial Automation
1.3 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP cores
with application-specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.4 Device Description
The TMS320C6678 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore
architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to
1.4 GHz. For developers of a broad range of applications, such as mission-critical systems, medical imaging, test and
automation, and other applications requiring high performance, TI's TMS320C6678 DSP offers 11.2 GHz
cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward
compatible with all existing C6000 family fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory
subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize
intra-device and inter-device communication that allows the various DSP resources to operate efficiently and
seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data
management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and
contention-free internal data movement. The multicore shared memory controller allows access to shared and
external memory directly without drawing from switch fabric capacity.
2
TMS320C6678 Features and Description
Copyright 2014 Texas Instruments Incorporated
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition,
the C66x core integrates floating point capability and the per-core raw computational performance in an
industry-leading 44.8 GMACS/core and 22.4 GFLOPS/core (@1.4 GHz operating frequency). It can execute 8
single-precision floating point MAC operations per cycle and can perform double- and mixed-precision operations,
and is IEEE754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted
for floating point and vector math oriented processing. These enhancements yield sizeable performance
improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions.
The C66x core is backwards code-compatible with TI's previous generation C6000 fixed and floating point DSP
cores, ensuring software portability and shortened software development cycles for applications migrating to faster
hardware.
The C6678 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache,
there is 512KB of dedicated memory per core that can be configured as mapped RAM or cache. The device also
integrates 4096KB of Multicore Shared Memory that can be used as a shared L2 SRAM and/or shared L3 SRAM. All
L2 memories incorporate error detection and error correction. For fast access to external memory, this device
includes a 64-bit DDR-3 external memory interface (EMIF) running at 1600 MHz and has ECC DRAM support.
This family supports a plethora of high speed standard interfaces including RapidIO ver 2, PCI Express Gen2, and
Gigabit Ethernet, as well as an integrated Ethernet switch. It also includes I2C, UART, Telecom Serial Interface Port
(TSIP), and a 16-bit EMIF, along with general purpose CMOS IO. For high throughput, low latency communication
between devices or with an FPGA, this device also sports a 50-Gbaud full-duplex interface called HyperLink. Adding
to the network awareness of this device is a network co-processor that includes both packet and optional security
acceleration. The packet accelerator can process up to 1.5 M packets/s and enables a single IP address to be used for
the entire multicore C6678 device. It also provides L2 to L4 classification, along with checksum and QoS capabilities.
The C6678 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly
optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source
code execution.
Copyright 2014 Texas Instruments Incorporated
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TMS320C6678 Features and Description
3
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
1.5 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the TMS320C6678 device.
Figure 1-1
Functional Block Diagram
6678
Memory Subsystem
64-Bit
DDR3 EMIF
4MB
MSM
SRAM
MSMC
C66x™
CorePac
C66x™
CorePac
C66x™
CorePac
C66x™
32KB L1
CorePac
P-Cache
32KB L1
D-Cache
C66x™
32KB L1
CorePac
P-Cache
C66x™
32KB L1
CorePac
P-Cache
32KB L1
512KB L2 Cache
D-Cache
32KB L1
512KB L2 Cache
D-Cache
C66x™
32KB L1
CorePac
P-Cache
C66x™
32KB L1
CorePac
P-Cache
32KB L1
512KB L2 Cache
D-Cache
32KB L1
512KB L2 Cache
D-Cache
32KB L1
P-Cache
32KB L1
512KB L2 Cache
D-Cache
32KB L1
P-Cache
32KB L1
512KB L2 Cache
D-Cache
32KB L1
P-Cache
32KB L1
512KB L2 Cache
D-Cache
512KB L2 Cache
8 Cores @ up to 1.4 GHz
Debug & Trace
Boot ROM
Semaphore
Power
Management
PLL
EDMA
´3
´3
HyperLink
TeraNet
TeraNet
6
1
F
M
E
I
I
O
P
G
C
2
I
2
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C
P
T
R
A
U
I
P
S
2
´
I
P
S
T
4
´
I
O
R
S
Multicore Navigator
Queue
Manager
Packet
DMA
t
e
n
r
e
h
t
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h
c
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w
S
I
I
M
G
S
2
´
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i
w
S
Security
Accelerator
Packet
Accelerator
Network Coprocessor
4
TMS320C6678 Features and Description
Copyright 2014 Texas Instruments Incorporated
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
1.6 Release History
Date
Revision
SPRS691E March 2014
SPRS691D April 2013
SPRS691C February 2012
SPRS691B August 2011
SPRS691A
July 2011
SPRS691
November 2010
Description/Comments
• Added 1.4-GHz support
• Added GYP package support
• Added DSP_SUSP_CTL register section
• Updated Core Before IO Power Sequencing diagram, changing clock signal SYSCLK1P&N to REFCLK1P&N
• Updated the Trace timing diagram
• Updated Parameter Table Index bit field in I2C boot configuration
• Updated PKTDMA_PRI_ALLOC register to be CHIP_MSIC_CTL register with new bit field added.
• Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings section
• Updated Chip Select field description in SPI boot device configuration table
• Corrections applied to EMIF16 Boot Device Configuration Bit Fields
• Restored Parameter Information section
• Added Initial Startup row for CVDD in Recommended Operating Conditions table
• Added DDR3PLLCTL1 and PASSPLLCTL1 registers to Device Status Control Registers table
• Added CVDD and SmartReflex voltage parameter in SmartReflex switching table
• Added HOUT timing diagram in Host Interrupt Output section
• Added MPU Registers Reset Values section
• Corrected PASSCLK(N/P) max cycle time from 6.4 ns to 25 ns
• Corrected Reserved to be Assert local reset to all CorePacs in LRESET and NMI decoding table
• Corrected PASS PLL clock to SRIOSGMIICLK in the boot device values table for Ethernet.
• Updated the Timer numbering across the whole document
• Updated DDR3 PLL initialization sequence
• Added TeraNet connection figures and added bridge numbers to the connection tables
• Changed TPCC to EDMA3CC and TPTC to EDMA3TC
• Changed chip level interrupt controller name from INTC to CIC
• Added the DDR3 PLL and PASS PLL Initialization Sequence
• Added DEVSPEED Register section
• Updated device frequency in the feature section
• Corrected the SPI, DDR3, and Hyperbridge config/data memory map addresses
• Restricted Output Divide of SECCTL Register to max value of divide by 2
• Updated the timing and electrical sections of several peripherals
• Updated the core-specific and general-purpose timer numbers
• Updated the connection matrix tables in chapter 4 “System Interconnection”
• Updated device boot configuration tables and figures
• Updated DDR3 and PASS PLL timing figures
• Removed section 7.1 “Parameter Information”
• Added sections: NMI and LRSET
• Added Pin Map diagrams
• Added MAINPLLCTL1, DDR3PLLCTL1 and PAPLLCTL1 registers
• Changed PLL diagrams of MAIN PLL, DDR3 PLL and PASS PLL
• Changed C66x DSP System PLL Configuration table to include 1000 MHz and 1250 MHz columns
• Corrected items in the Memory Map Summary table
• Changed all occurrences of PA_SS to Network Coprocessor
• Updated the complete Power-up sequencing section. RESETFULL must always de-assert after POR
Initial release
For detailed revision information, see ‘‘Revision History’’ on page 236.
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TMS320C6678 Features and Description
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TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
6
TMS320C6678 Features and Description
Copyright 2014 Texas Instruments Incorporated
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Contents
1 TMS320C6678 Features and Description . . . . . . . . . . . . .1
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.2 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.3 KeyStone Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.4 Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1.5 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.6 Release History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 DSP Core Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3 Memory Map Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.4 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.5 Boot Modes Supported and PLL Settings . . . . . . . . . . . . 24
2.5.1 Boot Device Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.2 Device Configuration Field . . . . . . . . . . . . . . . . . . . . 26
2.5.3 Boot Parameter Table . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.4 PLL Boot Configuration Settings. . . . . . . . . . . . . . . 38
2.6 Second-Level Bootloaders . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.7 Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7.1 Package Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.7.2 Pin Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.8 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.9 Development and Support . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.9.1 Development Support . . . . . . . . . . . . . . . . . . . . . . . . 70
2.9.2 Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.10 Related Documentation from Texas Instruments . . . 72
3 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.1 Device Configuration at Device Reset . . . . . . . . . . . . . . . 73
3.2 Peripheral Selection After Device Reset. . . . . . . . . . . . . . 74
3.3 Device State Control Registers . . . . . . . . . . . . . . . . . . . . . . 74
3.3.1 Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.2 Device Configuration Register (DEVCFG). . . . . . . 79
3.3.3 JTAG ID Register (JTAGID) Description . . . . . . . . . 79
3.3.4 Kicker Mechanism Register
(KICK0 and KICK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.5 DSP Boot Address Register
(DSP_BOOT_ADDRn) . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.6 LRESETNMI PIN Status Register
(LRSTNMIPINSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.3.7 LRESETNMI PIN Status Clear Register
(LRSTNMIPINSTAT_CLR) . . . . . . . . . . . . . . . . . . . . . . 81
3.3.8 Reset Status Register (RESET_STAT). . . . . . . . . . . . 83
3.3.9 Reset Status Clear Register
(RESET_STAT_CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.3.10 Boot Complete Register
(BOOTCOMPLETE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.3.11 Power State Control Register
(PWRSTATECTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.3.12 NMI Event Generation to CorePac Register
(NMIGRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.3.13 IPC Generation Registers (IPCGRx) . . . . . . . . . . . . 87
3.3.14 IPC Acknowledgement Registers (IPCARx) . . . . 88
3.3.15 IPC Generation Host Register (IPCGRH) . . . . . . . 88
3.3.16 IPC Acknowledgement Host Register
(IPCARH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3.17 Timer Input Selection Register (TINPSEL) . . . . . 90
Copyright 2014 Texas Instruments Incorporated
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TMS320C6678
SPRS691E—November 2010—Revised March 2014
3.3.18 Timer Output Selection Register
(TOUTPSEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.3.19 Reset Mux Register (RSTMUXx). . . . . . . . . . . . . . . .94
3.3.20 DSP Suspension Control Register
(DSP_SUSP_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3.3.21 Device Speed Register (DEVSPEED) . . . . . . . . . . .96
3.3.22 Chip Miscellaneous Control Register
(CHIP_MISC_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
3.4 Pullup/Pulldown Resistors. . . . . . . . . . . . . . . . . . . . . . . . . . .97
4 System Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1 Internal Buses and Switch Fabrics. . . . . . . . . . . . . . . . . . . .98
4.2 Switch Fabric Connections . . . . . . . . . . . . . . . . . . . . . . . . . .99
4.3 Bus Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
5 C66x CorePac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
5.1 Memory Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
5.1.1 L1P Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
5.1.2 L1D Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
5.1.3 L2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
5.1.4 MSM SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.1.5 L3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
5.2 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
5.3 Bandwidth Management . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.4 Power-Down Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
5.5 C66x CorePac Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
5.6 C66x CorePac Register Descriptions. . . . . . . . . . . . . . . . .115
6 Device Operating Conditions . . . . . . . . . . . . . . . . . . . . . .116
6.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . .116
6.2 Recommended Operating Conditions . . . . . . . . . . . . . .117
6.3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .118
6.4 Power Supply to Peripheral I/O Mapping. . . . . . . . . . . .119
7 Peripheral Information and Electrical
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
7.1 Parameter Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
7.1.1 Timing Parameters and Board Routing
Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
7.1.2 1.8-V LVCMOS Signal Transition Levels . . . . . . . .120
7.2 Recommended Clock and Control Signal
Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
7.3 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
7.3.1 Power-Supply Sequencing . . . . . . . . . . . . . . . . . . . .122
7.3.2 Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . .127
7.3.3 Power Supply Decoupling and
Bulk Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
7.3.4 SmartReflex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
7.4 Power Sleep Controller (PSC) . . . . . . . . . . . . . . . . . . . . . . .129
7.4.1 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
7.4.2 Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
7.4.3 PSC Register Memory Map . . . . . . . . . . . . . . . . . . . .131
7.5 Reset Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
7.5.1 Power-on Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
7.5.2 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
7.5.3 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
7.5.4 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.5.5 Reset Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
7.5.6 Reset Controller Register. . . . . . . . . . . . . . . . . . . . . .137
7.5.7 Reset Electrical Data / Timing . . . . . . . . . . . . . . . . .138
7.6 Main PLL and PLL Controller . . . . . . . . . . . . . . . . . . . . . . . .140
Contents
7
TMS320C6678
SPRS691E—November 2010—Revised March 2014
7.6.1 Main PLL Controller Device-Specific
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
7.6.2 PLL Controller Memory Map. . . . . . . . . . . . . . . . . . 143
7.6.3 Main PLL Control Register . . . . . . . . . . . . . . . . . . . . 150
7.6.4 Main PLL and PLL Controller Initialization
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.6.5 Main PLL Controller/SRIO/HyperLink/PCIe
Clock Input Electrical Data/Timing . . . . . . . . . . . 151
7.7 DD3 PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
7.7.1 DDR3 PLL Control Register . . . . . . . . . . . . . . . . . . . 153
7.7.2 DDR3 PLL Device-Specific Information. . . . . . . . 154
7.7.3 DDR3 PLL Initialization Sequence. . . . . . . . . . . . . 154
7.7.4 DDR3 PLL Input Clock Electrical
Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
7.8 PASS PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
7.8.1 PASS PLL Control Register . . . . . . . . . . . . . . . . . . . . 156
7.8.2 PASS PLL Device-Specific Information . . . . . . . . 157
7.8.3 PASS PLL Initialization Sequence . . . . . . . . . . . . . 157
7.8.4 PASS PLL Input Clock Electrical
Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.9 Enhanced Direct Memory Access (EDMA3)
Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.9.1 EDMA3 Device-Specific Information . . . . . . . . . . 160
7.9.2 EDMA3 Channel Controller Configuration . . . . 160
7.9.3 EDMA3 Transfer Controller Configuration. . . . . 160
7.9.4 EDMA3 Channel Synchronization Events. . . . . . 161
7.10 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
7.10.1 Interrupt Sources and Interrupt Controller. . . 165
7.10.2 CIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
7.10.3 Inter-Processor Register Map. . . . . . . . . . . . . . . . 188
7.10.4 NMI and LRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
7.10.5 External Interrupts Electrical Data/Timing . . . 190
7.10.6 Host Interrupt Output. . . . . . . . . . . . . . . . . . . . . . . 191
7.11 Memory Protection Unit (MPU) . . . . . . . . . . . . . . . . . . . 192
7.11.1 MPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
7.11.2 MPU Programmable Range Registers . . . . . . . . 200
7.12 DDR3 Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . 205
7.12.1 DDR3 Memory Controller Device-Specific
Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.12.2 DDR3 Memory Controller Race Condition
Consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
7.12.3 DDR3 Memory Controller Electrical
Data/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
7.13 I2C Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
7.13.1 I2C Device-Specific Information . . . . . . . . . . . . . .207
7.13.2 I2C Peripheral Register Description(s) . . . . . . . .208
7.13.3 I2C Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .209
7.14 SPI Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
7.14.1 SPI Electrical Data/Timing. . . . . . . . . . . . . . . . . . . .212
7.15 HyperLink Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
7.15.1 HyperLink Device-Specific Interrupt Event. . . .215
7.15.2 HyperLink Electrical Data/Timing . . . . . . . . . . . .217
7.16 UART Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
7.17 PCIe Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
7.18 TSIP Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
7.18.1 TSIP Electrical Data/Timing . . . . . . . . . . . . . . . . . .221
7.19 EMIF16 Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
7.19.1 EMIF16 Electrical Data/Timing . . . . . . . . . . . . . . .223
7.20 Packet Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
7.21 Security Accelerator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
7.22 Gigabit Ethernet (GbE) Switch Subsystem. . . . . . . . . .226
7.23 Management Data Input/Output (MDIO) . . . . . . . . . .228
7.24 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
7.24.1 Timers Device-Specific Information . . . . . . . . . .229
7.24.2 Timers Electrical Data/Timing . . . . . . . . . . . . . . . .230
7.25 Serial RapidIO (SRIO) Port . . . . . . . . . . . . . . . . . . . . . . . . .230
7.26 General-Purpose Input/Output (GPIO) . . . . . . . . . . . . .231
7.26.1 GPIO Device-Specific Information . . . . . . . . . . . .231
7.26.2 GPIO Electrical Data/Timing. . . . . . . . . . . . . . . . . .231
7.27 Semaphore2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232
7.28 Emulation Features and Capability . . . . . . . . . . . . . . . .232
7.28.1 Advanced Event Triggering (AET) . . . . . . . . . . . .232
7.28.2 Trace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
7.28.3 IEEE 1149.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
8 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
9.1 Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
9.2 Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
8
Contents
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