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ISO 16845-1-2016.pdf
© ISO 2016Road vehicles — Controller area network (CAN) conformance test plan —Part 1: Data link layer and physical signallingVéhicules routiers — Plan d’essai de conformité du gestionnaire de réseau de communication (CAN) —Partie 1: Couche liaison de données et signalisation physiqueINTERNATIONAL STANDARDISO16845-1First edition2016-11-01Reference numberISO 16845-1:2016(E)International Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E) ii © ISO 2016 – All rights reservedCOPYRIGHT PROTECTED DOCUMENT© ISO 2016, Published in SwitzerlandAll rights reserved. Unless otherwise specified, no part of this publication may be reproduced or utilized otherwise in any form or by any means, electronic or mechanical, including photocopying, or posting on the internet or an intranet, without prior written permission. Permission can be requested from either ISO at the address below or ISO’s member body in the country of the requester.ISO copyright officeCh. de Blandonnet 8 • CP 401CH-1214 Vernier, Geneva, SwitzerlandTel. +41 22 749 01 11Fax +41 22 749 09 47copyright@iso.orgwww.iso.orgInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E) Foreword ......................................................................................................................................................................................................................................viiIntroduction ............................................................................................................................................................................................................................viii1 Scope .................................................................................................................................................................................................................................12 Normative references ......................................................................................................................................................................................13 Terms and definitions .....................................................................................................................................................................................14 Abbreviated terms ..............................................................................................................................................................................................35 Global overview .....................................................................................................................................................................................................45.1 Scope of test plan ..................................................................................................................................................................................45.2 Architecture of test plan .................................................................................................................................................................45.3 Organization ..............................................................................................................................................................................................55.3.1 General organization ....................................................................................................................................................55.3.2 Test case organization .................................................................................................................................................65.3.3 Hierarchical structure of tests ..............................................................................................................................76 LT parameters ..........................................................................................................................................................................................................86.1 Overview ......................................................................................................................................................................................................86.2 Description of parameters ............................................................................................................................................................86.2.1 Communication parameters ..................................................................................................................................86.2.2 Application parameters .............................................................................................................................................96.2.3 Bit rate configuration parameter variation for bit timing tests ...........................................107 Test type 1, received frame .....................................................................................................................................................................107.1 Test class 1, valid frame format .............................................................................................................................................107.1.1 Identifier and number of data test in base format...........................................................................107.1.2 Identifier and number of data test in extended format ...............................................................117.1.3 Reception after arbitration lost ........................................................................................................................127.1.4 Acceptance of non-nominal bit in base format frame ...................................................................137.1.5 Acceptance of non-nominal bit in extended format frame .......................................................137.1.6 Protocol exception behaviour on non-nominal bit ..........................................................................147.1.7 Minimum time for bus idle after protocol exception handling .............................................157.1.8 DLC greater than 8 ......................................................................................................................................................157.1.9 Absent bus idle — Valid frame reception ................................................................................................167.1.10 Stuff acceptance test in base format frame ............................................................................................167.1.11 Stuff acceptance test in extended format frame ................................................................................177.1.12 Message validation ......................................................................................................................................................187.2 Test class 2, error detection ......................................................................................................................................................197.2.1 Bit error in data frame .............................................................................................................................................197.2.2 Stuff error for basic frame ....................................................................................................................................197.2.3 Stuff error for extended frame ..........................................................................................................................207.2.4 Stuff error for FD frame payload bytes ......................................................................................................217.2.5 CRC error .............................................................................................................................................................................227.2.6 Combination of CRC error and form error ..............................................................................................237.2.7 Form error in data frame at “CRC delimiter” bit position .........................................................247.2.8 Form error at fixed stuff bit in FD frames ...............................................................................................247.2.9 Form error in data frame at “ACK delimiter” bit position ..........................................................257.2.10 Form error in data frame at “EOF” ................................................................................................................257.2.11 Message non-validation ..........................................................................................................................................267.3 Test class 3, error frame management ............................................................................................................................267.3.1 Error flag longer than 6 bits ................................................................................................................................267.3.2 Data frame starting on the third bit of intermission field .........................................................277.3.3 Bit error in error flag .................................................................................................................................................277.3.4 Form error in error delimiter ............................................................................................................................287.4 Test class 4, overload frame management ...................................................................................................................287.4.1 MAC overload generation during intermission field .....................................................................28© ISO 2016 – All rights reserved iiiContents PageInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E) 7.4.2 Last bit of EOF .................................................................................................................................................................297.4.3 Eighth bit of an error and overload delimiter ......................................................................................297.4.4 Bit error in overload flag ........................................................................................................................................307.4.5 Form error in overload delimiter ...................................................................................................................307.4.6 MAC overload generation during intermission field following an error frame ......317.4.7 MAC overload generation during intermission field following an overload frame ................................................................................................................................................................317.5 Test class 5, passive error state class ................................................................................................................................327.5.1 Passive error flag completion test 1 .............................................................................................................327.5.2 Data frame acceptance after passive error frame transmission ..........................................337.5.3 Acceptance of 7 consecutive dominant bits after passive error flag ................................337.5.4 Passive state unchanged on further errors ............................................................................................347.5.5 Passive error flag completion — Test case 2 ........................................................................................347.5.6 Form error in passive error delimiter ........................................................................................................357.5.7 Transition from active to passive ERROR FLAG .................................................................................357.6 Test class 6, error counter management........................................................................................................................367.6.1 REC increment on bit error in active error flag ..................................................................................367.6.2 REC increment on bit error in overload flag .........................................................................................377.6.3 REC increment when active error flag is longer than 13 bits .................................................377.6.4 REC increment when overload flag is longer than 13 bits ........................................................387.6.5 REC increment on bit error in the ACK field .........................................................................................387.6.6 REC increment on form error in CRC delimiter..................................................................................387.6.7 REC increment on form error in ACK delimiter .................................................................................397.6.8 REC increment on form error in EOF field .............................................................................................397.6.9 REC increment on stuff error .............................................................................................................................407.6.10 REC increment on CRC error ..............................................................................................................................417.6.11 REC increment on dominant bit after end of error flag ..............................................................417.6.12 REC increment on form error in error delimiter ..............................................................................427.6.13 REC increment on form error in overload delimiter......................................................................427.6.14 REC decrement on valid frame reception ................................................................................................437.6.15 REC decrement on valid frame reception during passive state ............................................437.6.16 REC non-increment on last bit of EOF field ...........................................................................................447.6.17 REC non-increment on 13-bit length overload flag ........................................................................447.6.18 REC non-increment on 13-bit length error flag .................................................................................457.6.19 REC non-increment on last bit of error delimiter ............................................................................457.6.20 REC non-increment on last bit of overload delimiter ...................................................................467.6.21 REC non-decrement on transmission .........................................................................................................467.6.22 REC increment on form error at fixed stuff bit in FD frames ..................................................477.6.23 REC non-increment on protocol exception in FD frames...........................................................477.7 Test class 7, bit timing Classical CAN frame format .............................................................................................487.7.1 Sample point test ..........................................................................................................................................................487.7.2 Hard synchronization on SOF reception ..................................................................................................497.7.3 Synchronization when e > 0 and e ≤ SJW(N) ........................................................................................497.7.4 Synchronization when e > 0 and e > SJW(N) ........................................................................................507.7.5 Synchronization when e < 0 and |e| ≤ SJW(N) ....................................................................................507.7.6 Synchronization when e < 0 and |e| > SJW(N) ....................................................................................517.7.7 Glitch filtering test on positive phase error ...........................................................................................517.7.8 Glitch filtering test on negative phase error..........................................................................................527.7.9 Glitch filtering test in idle state ........................................................................................................................537.7.10 Non-Synchronization after a dominant sampled bit ......................................................................547.7.11 Synchronization when e < 0 and |e| ≤ SJW(N) at “ACK” bit position ................................557.8 Test class 8, bit timing CAN FD frame format ............................................................................................................557.8.1 Sample point test ..........................................................................................................................................................557.8.2 Hard synchronization on “res” bit ................................................................................................................587.8.3 Synchronization when e > 0 and e ≤ SJW(D) ........................................................................................597.8.4 Synchronization when e > 0 and e > SJW(D) ........................................................................................617.8.5 Synchronization when e < 0 and |e| ≤ SJW .............................................................................................637.8.6 Synchronization when e < 0 and |e| > SJW .............................................................................................65iv © ISO 2016 – All rights reservedInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E) 7.8.7 Glitch filtering test on positive phase error ...........................................................................................677.8.8 Glitch filtering test on negative phase error..........................................................................................697.8.9 No synchronization after a dominant sampled bit ..........................................................................718 Test type 2, transmitted frame ............................................................................................................................................................738.1 Test class 1, valid frame format .............................................................................................................................................738.1.1 Identifier and number of data bytes test in base format ............................................................738.1.2 Identifier and number of data bytes test in extended format ................................................738.1.3 Arbitration in base format frame ....................................................................................................................748.1.4 Arbitration in extended format frame test .............................................................................................758.1.5 Message validation ......................................................................................................................................................768.1.6 Stuff bit generation capability in base format frame .....................................................................768.1.7 Stuff bit generation capability in extended frame ............................................................................778.1.8 Transmission on the third bit of intermission field after arbitration lost ...................788.2 Test class 2, error detection ......................................................................................................................................................798.2.1 Bit error test in base format frame ...............................................................................................................798.2.2 Bit error in extended format frame ..............................................................................................................808.2.3 Stuff error test in base format frame ...........................................................................................................818.2.4 Stuff error test in extended frame format ...............................................................................................818.2.5 Form error test ...............................................................................................................................................................828.2.6 Acknowledgement error ........................................................................................................................................838.2.7 Form field tolerance test for FD frame format ....................................................................................848.2.8 Bit error at stuff bit position for FD frame payload bytes .........................................................848.3 Test class 3, error frame management ............................................................................................................................858.3.1 Error flag longer than 6 bit ..................................................................................................................................858.3.2 Transmission on the third bit of intermission field after error frame ............................858.3.3 Bit error in error flag .................................................................................................................................................868.3.4 Form error in error delimiter ............................................................................................................................868.4 Test class 4, overload frame management ...................................................................................................................878.4.1 MAC overload generation in intermission field..................................................................................878.4.2 Eighth bit of an error and overload delimiter ......................................................................................888.4.3 Transmission on the third bit of intermission after overload frame ...............................888.4.4 Bit error in overload flag ........................................................................................................................................898.4.5 Form error in overload delimiter ...................................................................................................................898.5 Test class 5, passive error state and bus-off ...............................................................................................................908.5.1 Acceptance of active error flag overwriting passive error flag .............................................908.5.2 Frame acceptance after passive error frame transmission ......................................................908.5.3 Acceptance of 7 consecutive dominant bits after passive error flag ................................918.5.4 Reception of a frame during suspend transmission .......................................................................928.5.5 Transmission of a frame after suspend transmission — Test case 1 .............................928.5.6 Transmission of a frame after suspend transmission — Test case 2 ...............................938.5.7 Transmission of a frame after suspend transmission — Test case 3 ...............................938.5.8 Transmission of a frame without suspend transmission ...........................................................938.5.9 No transmission of a frame between the third bit of intermission field and eighth bit of suspend transmission ...............................................................................................................948.5.10 Bus-off state ......................................................................................................................................................................948.5.11 Bus-off recovery ............................................................................................................................................................958.5.12 Completion condition for a passive error flag .....................................................................................968.5.13 Form error in passive error delimiter ........................................................................................................968.5.14 Maximum recovery time after a corrupted frame ............................................................................978.5.15 Transition from active to passive ERROR FLAG .................................................................................978.6 Test class 6, error counter management........................................................................................................................988.6.1 TEC increment on bit error during active error flag ......................................................................988.6.2 TEC increment on bit error during overload flag .............................................................................998.6.3 TEC increment when active error flag is followed by dominant bits ..............................998.6.4 TEC increment when passive error flag is followed by dominant bits ........................1008.6.5 TEC increment when overload flag is followed by dominant bits ...................................1008.6.6 TEC increment on bit error in data frame ............................................................................................1018.6.7 TEC increment on form error in a frame ...............................................................................................102© ISO 2016 – All rights reserved vInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E) 8.6.8 TEC increment on acknowledgement error .......................................................................................1028.6.9 TEC increment on form error in error delimiter ............................................................................1038.6.10 TEC increment on form error in overload delimiter ...................................................................1038.6.11 TEC decrement on successful frame transmission for TEC < 128...................................1048.6.12 TEC decrement on successful frame transmission for TEC > 127...................................1048.6.13 TEC non-increment on 13-bit long overload flag ..........................................................................1058.6.14 TEC non-increment on 13-bit long error flag ...................................................................................1058.6.15 TEC non-increment on form error at last bit of overload delimiter ..............................1068.6.16 TEC non-increment on form error at last bit of error delimiter .......................................1068.6.17 TEC non-increment on acknowledgement error in passive state ...................................1078.6.18 TEC increment after acknowledgement error in passive state ..........................................1078.6.19 TEC non-increment on stuff error during arbitration ...............................................................1088.6.20 TEC non-decrement on transmission while arbitration lost ...............................................1088.6.21 TEC non-increment after arbitration lost and error ...................................................................1098.7 Test class 7, bit timing .................................................................................................................................................................1098.7.1 Sample point test .......................................................................................................................................................1098.7.2 Hard synchronization on SOF reception before sample point ...........................................1108.7.3 Hard synchronization on SOF reception after sample point ................................................1118.7.4 Synchronization when e < 0 and |e| ≤ SJW(N) .................................................................................1118.7.5 Synchronization for e < 0 and |e| > SJW(N) ........................................................................................1128.7.6 Glitch filtering test on negative phase error.......................................................................................1138.7.7 Non-synchronization on dominant bit transmission .................................................................1138.7.8 Synchronization before information processing time ...............................................................1148.7.9 Synchronization after sample point while sending a dominant bit ...............................1148.8 Test class 8, bit timing CAN FD frame format .........................................................................................................1158.8.1 Sample point test .......................................................................................................................................................1158.8.2 Secondary sample point test ...........................................................................................................................1188.8.3 No synchronization within data phase bits when e < 0; |e| ≤ SJW(D) .........................1218.8.4 Glitch filtering test on negative phase error within FD frame bits .................................1238.8.5 No synchronization on dominant bit transmission in FD frames ....................................1249 Test type 3, bi-directional frame ...................................................................................................................................................1259.1 Test class 1, valid frame format ..........................................................................................................................................1259.2 Test class 2, error detection ...................................................................................................................................................1259.3 Test class 3, active error frame management .........................................................................................................1259.4 Test class 4, overload frame management ................................................................................................................1259.5 Test class 5, passive-error state and bus-off ............................................................................................................1259.6 Test class 6, error counter management.....................................................................................................................1269.6.1 REC unaffected when increasing TEC ......................................................................................................1269.6.2 TEC unaffected when increasing REC ......................................................................................................126vi © ISO 2016 – All rights reservedInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E)ForewordISO (the International Organization for Standardization) is a worldwide federation of national standards bodies (ISO member bodies). The work of preparing International Standards is normally carried out through ISO technical committees. Each member body interested in a subject for which a technical committee has been established has the right to be represented on that committee. International organizations, governmental and non-governmental, in liaison with ISO, also take part in the work. ISO collaborates closely with the International Electrotechnical Commission (IEC) on all matters of electrotechnical standardization.The procedures used to develop this document and those intended for its further maintenance are described in the ISO/IEC Directives, Part 1. In particular the different approval criteria needed for the different types of ISO documents should be noted. This document was drafted in accordance with the editorial rules of the ISO/IEC Directives, Part 2 (see www.iso.org/directives).Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. ISO shall not be held responsible for identifying any or all such patent rights. Details of any patent rights identified during the development of the document will be in the Introduction and/or on the ISO list of patent declarations received (see www.iso.org/patents).Any trade name used in this document is information given for the convenience of users and does not constitute an endorsement.For an explanation on the meaning of ISO specific terms and expressions related to conformity assessment, as well as information about ISO’s adherence to the World Trade Organization (WTO) principles in the Technical Barriers to Trade (TBT) see the following URL: www.iso.org/iso/foreword.html.The committee responsible for this document is ISO/TC 22, Road vehicles, Subcommittee SC 31, Data communication.This first edition of ISO 16845-1 cancels and replaces ISO 16845:2004, which has been technically revised.A list of all parts in the ISO 16845 series can be found on the ISO website. © ISO 2016 – All rights reserved viiInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
ISO 16845-1:2016(E)IntroductionISO 16845 was first published in 2004 to provide the methodology and abstract test suite necessary for checking the conformance of any CAN implementation of the CAN specified in ISO 11898-1. viii © ISO 2016 – All rights reservedInternational Organization for StandardizationProvided by IHS under license with ISO Licensee=ZHEJIANG INST OF STANDARDIZATION C1 5956617Not for Resale, 2016/12/22 00:57:39 No reproduction or networking permitted without license from IHS--`,``,`,```,,`,,,,,,`,,`-`-``,```,,,`---
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